Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27135

1

T1

31

T2

8

T3

14

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21416

1

T3

14

T4

2

T5

38

auto[ADC_CTRL_FILTER_COND_OUT]

5719

1

T1

31

T2

8

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20806

1

T3

14

T5

25

T6

2

auto[1]

6329

1

T1

31

T2

8

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22883

1

T1

31

T2

1

T3

14

auto[1]

4252

1

T2

7

T5

12

T7

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	346	1			T204	21		T173	1		T130	21
values[0]	5	1			T248	1		T52	3		T303	1
values[1]	711	1			T65	12		T40	35		T157	26
values[2]	582	1			T4	1		T6	1		T8	1
values[3]	929	1			T6	1		T65	12		T40	24
values[4]	861	1			T40	5		T66	10		T183	1
values[5]	664	1			T68	25		T183	1		T166	6
values[6]	875	1			T8	3		T9	11		T31	3
values[7]	504	1			T65	4		T231	1		T33	1
values[8]	632	1			T5	13		T10	9		T64	1
values[9]	3509	1			T1	31		T2	8		T4	1
minimum	17517	1			T3	14		T5	25		T31	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	599	1			T40	35		T157	21		T34	19
values[1]	3000	1			T1	31		T2	8		T4	1
values[2]	955	1			T6	1		T65	12		T40	24
values[3]	913	1			T40	5		T66	10		T68	25
values[4]	721	1			T9	3		T183	1		T46	12
values[5]	849	1			T8	3		T9	8		T65	4
values[6]	441	1			T10	9		T33	1		T204	3
values[7]	645	1			T5	13		T64	1		T163	18
values[8]	1096	1			T4	1		T9	9		T31	1
values[9]	186	1			T204	11		T174	4		T50	20
minimum	17730	1			T3	14		T5	25		T65	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

4440

1

T1

28

T65

25

T40

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	17		T171	1		T196	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T40	15		T157	1		T255	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	1		T66	7		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1728	1			T1	31		T2	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T6	1		T68	13		T165	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T65	12		T40	12		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T66	10		T165	5		T34	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	1		T68	12		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T183	1		T46	8		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T210	12		T232	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	1		T65	4		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T231	1		T68	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T204	3		T129	5		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T10	1		T33	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T163	9		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T64	1		T234	1		T194	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T4	1		T9	1		T161	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T31	1		T32	12		T63	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T174	2		T135	14		T303	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T204	11		T50	15		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17428	1			T3	14		T5	25		T31	141
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T65	12		T157	2		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T34	2		T171	16		T51	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	20		T157	20		T255	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T232	11		T239	9		T298	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1035	1			T2	7		T7	19		T10	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T68	11		T165	8		T166	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	12		T43	6		T34	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T34	16		T248	10		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	4		T68	13		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	4		T166	5		T187	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	2		T232	9		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	7		T31	2		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	2		T68	6		T54	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	3		T232	7		T175	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	8		T47	1		T306	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	12		T163	9		T197	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T234	2		T194	11		T259	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	8		T162	1		T174	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T32	11		T47	10		T246	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T174	2		T135	4		T189	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T50	5		T278	2		T274	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T31	1		T32	2		T46	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T157	3		T52	1		T264	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T204	10		T173	1		T328	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T204	11		T130	12		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T248	1		T52	2		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	17		T171	1		T196	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T65	12		T40	15		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	1		T161	1		T232	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	1		T8	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T66	7		T68	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T65	12		T40	12		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T66	10		T165	5		T34	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T40	1		T183	1		T246	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T183	1		T166	1		T292	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T68	12		T210	12		T232	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	1		T31	1		T46	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T9	1		T68	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T65	4		T204	3		T232	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T231	1		T33	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T163	9		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T10	1		T64	1		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T4	1		T9	1		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1849	1			T1	31		T2	1		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T3	14		T5	25		T31	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T325	11		T237	13		T329	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T130	9		T278	2		T311	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T52	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	2		T171	16		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	20		T157	23		T255	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T232	11		T51	2		T239	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	2		T67	22		T130	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T68	11		T165	8		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	12		T43	6		T33	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	16		T248	10		T168	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	4		T246	9		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T166	5		T174	10		T187	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T68	13		T232	9		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	7		T31	2		T46	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	2		T9	2		T68	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T232	7		T239	15		T175	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T47	1		T229	8		T306	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	12		T163	9		T197	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	8		T194	1		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	8		T162	1		T174	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1103	1			T2	7		T7	19		T37	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	1		T32	2		T46	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	3		T171	17		T196	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	22		T157	21		T255	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	1		T66	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1381	1			T1	3		T2	8		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T6	1		T68	12		T165	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T65	1		T40	13		T43	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T66	1		T165	1		T34	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T40	5		T68	14		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T183	1		T46	9		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	3		T210	1		T232	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T9	8		T65	1		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	3		T231	1		T68	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T204	1		T129	4		T232	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T10	9		T33	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	13		T163	10		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T64	1		T234	3		T194	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T4	1		T9	9		T161	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T31	1		T32	12		T63	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T174	3		T135	10		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T204	1		T50	11		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17575	1			T3	14		T5	25		T31	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T65	1		T157	4		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	16		T196	9		T51	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T40	13		T255	5		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T66	6		T232	12		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T1	28		T67	14		T58	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T68	12		T165	8		T168	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T65	11		T40	11		T66	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T66	9		T165	4		T34	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T68	11		T207	10		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	3		T177	3		T187	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T210	11		T232	12		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T65	3		T162	11		T172	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T68	12		T164	10		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T204	2		T129	4		T232	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T47	1		T177	15		T309	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T163	8		T197	4		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T194	3		T170	6		T254	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T204	9		T174	10		T258	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T32	11		T63	9		T47	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T174	1		T135	8		T303	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T204	10		T50	9		T274	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T55	1		T286	6		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T65	11		T157	1		T52	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T204	1		T173	1		T328	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T204	1		T130	10		T278	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T248	1		T52	2		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	3		T171	17		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T65	1		T40	22		T157	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	1		T161	1		T232	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T8	1		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T6	1		T66	1		T68	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T65	1		T40	13		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T66	1		T165	1		T34	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T40	5		T183	1		T246	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T183	1		T166	6		T292	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T68	14		T210	1		T232	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T9	8		T31	3		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	3		T9	3		T68	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T65	1		T204	1		T232	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T231	1		T33	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	13		T163	10		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	9		T64	1		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T4	1		T9	9		T161	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T1	3		T2	8		T7	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17517	1			T3	14		T5	25		T31	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T204	9		T328	13		T325	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T204	10		T130	11		T311	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T52	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	16		T196	9		T55	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T65	11		T40	13		T157	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T232	12		T51	2		T170	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T67	14		T130	10		T252	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T66	6		T68	12		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	11		T40	11		T66	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T66	9		T165	4		T34	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T246	12		T48	1		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T177	3		T174	12		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T68	11		T210	11		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T46	3		T162	11		T187	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T68	12		T54	5		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T65	3		T204	2		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	1		T177	15		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T163	8		T197	4		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T254	21		T310	7		T312	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T174	11		T258	6		T211	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1483	1			T1	28		T32	11		T58	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22695

1

T1

3

T2

8

T3

14

auto[1]

auto[0]

4440

1

T1

28

T65

25

T40

24