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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.09


Total test records in report: 919
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T797 /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3673518143 Mar 24 12:50:21 PM PDT 24 Mar 24 12:50:55 PM PDT 24 29376427227 ps
T798 /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2973062612 Mar 24 12:50:13 PM PDT 24 Mar 24 12:53:51 PM PDT 24 355453344012 ps
T799 /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3976929733 Mar 24 12:52:16 PM PDT 24 Mar 24 12:55:43 PM PDT 24 170244270112 ps
T353 /workspace/coverage/default/40.adc_ctrl_filters_interrupt.249263762 Mar 24 12:53:57 PM PDT 24 Mar 24 01:13:29 PM PDT 24 493212429969 ps
T91 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.67316648 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:23 PM PDT 24 599371090 ps
T151 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1873039865 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:29 PM PDT 24 358605482 ps
T77 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3307909159 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:38 PM PDT 24 8001230824 ps
T95 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.110955465 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:12 PM PDT 24 552230756 ps
T94 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3289406686 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:33 PM PDT 24 350192820 ps
T85 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.891337055 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:35 PM PDT 24 538077298 ps
T800 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.340852455 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 407252689 ps
T801 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1927932813 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 296599923 ps
T802 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2490895931 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 543583139 ps
T803 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2129402708 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:42 PM PDT 24 313457578 ps
T73 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.740562041 Mar 24 12:33:45 PM PDT 24 Mar 24 12:34:09 PM PDT 24 4736375848 ps
T86 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1088825885 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:35 PM PDT 24 489983755 ps
T152 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4238416724 Mar 24 12:33:32 PM PDT 24 Mar 24 12:33:34 PM PDT 24 2528226756 ps
T87 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4036293759 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:24 PM PDT 24 966640701 ps
T804 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.874217894 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:36 PM PDT 24 496483621 ps
T153 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.827729490 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:35 PM PDT 24 496427184 ps
T805 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3948934438 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:39 PM PDT 24 416203680 ps
T806 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3753124784 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:45 PM PDT 24 455561767 ps
T807 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1057117984 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:47 PM PDT 24 496422411 ps
T90 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2261664463 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:34 PM PDT 24 578545894 ps
T78 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1534663727 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:28 PM PDT 24 4296615911 ps
T93 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.200046807 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:31 PM PDT 24 426984234 ps
T137 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2748927579 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:19 PM PDT 24 703633729 ps
T74 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1914043418 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:32 PM PDT 24 450695136 ps
T92 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3940450200 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:28 PM PDT 24 640672143 ps
T138 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2614884477 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:17 PM PDT 24 1080445013 ps
T76 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2712800698 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:36 PM PDT 24 2473923177 ps
T79 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2711155283 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:46 PM PDT 24 8835932154 ps
T808 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.591474875 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 313168437 ps
T358 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1200695361 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:35 PM PDT 24 4267043576 ps
T809 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1156698367 Mar 24 12:33:01 PM PDT 24 Mar 24 12:33:15 PM PDT 24 4446701909 ps
T810 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.570109330 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 708510530 ps
T811 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4266833823 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 458537890 ps
T156 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3909720560 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:27 PM PDT 24 874070373 ps
T812 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1685216134 Mar 24 12:33:40 PM PDT 24 Mar 24 12:33:43 PM PDT 24 464987093 ps
T813 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1743054926 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 344512632 ps
T154 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.675034381 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 454697736 ps
T139 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2794010586 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:33 PM PDT 24 325647066 ps
T814 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.263241260 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 293429045 ps
T354 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4272871475 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:34 PM PDT 24 4632534917 ps
T359 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3493580168 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:41 PM PDT 24 4868418145 ps
T815 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1880934811 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:25 PM PDT 24 449956600 ps
T816 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.6922532 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:27 PM PDT 24 485166698 ps
T155 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.157571906 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:36 PM PDT 24 2561347901 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3642498503 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:16 PM PDT 24 612916350 ps
T140 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1071762199 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:38 PM PDT 24 387241849 ps
T818 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.668247599 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 418028889 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1636413066 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:30 PM PDT 24 566691636 ps
T820 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.926348561 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:50 PM PDT 24 7677915320 ps
T821 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1737960739 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 318664130 ps
T146 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1075746274 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:30 PM PDT 24 398128433 ps
T822 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.178400303 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:13 PM PDT 24 309324854 ps
T823 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3506814719 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:31 PM PDT 24 556366139 ps
T824 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.606540637 Mar 24 12:33:44 PM PDT 24 Mar 24 12:33:48 PM PDT 24 552010051 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3288658784 Mar 24 12:33:49 PM PDT 24 Mar 24 12:34:03 PM PDT 24 4358478647 ps
T825 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1816995479 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:43 PM PDT 24 26432926888 ps
T826 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2060150259 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:29 PM PDT 24 467248737 ps
T827 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3144416086 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:52 PM PDT 24 602890908 ps
T141 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3203456204 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:25 PM PDT 24 414157554 ps
T828 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3767441121 Mar 24 12:32:59 PM PDT 24 Mar 24 12:33:02 PM PDT 24 2320410961 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2246140751 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:28 PM PDT 24 521384835 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.171820337 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:15 PM PDT 24 488041396 ps
T142 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1724023851 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:26 PM PDT 24 1309920025 ps
T831 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.505936933 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:44 PM PDT 24 8341491093 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2212363039 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:28 PM PDT 24 596312924 ps
T833 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1730071901 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:33 PM PDT 24 366542967 ps
T834 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2509499433 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:28 PM PDT 24 380643915 ps
T143 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3189174193 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:31 PM PDT 24 416989119 ps
T144 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4290645923 Mar 24 12:33:22 PM PDT 24 Mar 24 12:33:23 PM PDT 24 383549838 ps
T835 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1488596237 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:23 PM PDT 24 309207618 ps
T836 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2392108130 Mar 24 12:33:33 PM PDT 24 Mar 24 12:33:36 PM PDT 24 782909407 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.354309264 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 331625252 ps
T360 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2664176913 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:36 PM PDT 24 4102712025 ps
T145 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3333633166 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:39 PM PDT 24 777561959 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1072208786 Mar 24 12:33:52 PM PDT 24 Mar 24 12:33:54 PM PDT 24 574958467 ps
T839 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1483183834 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:39 PM PDT 24 298842148 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2860978824 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:28 PM PDT 24 1233675919 ps
T841 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2126861272 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:24 PM PDT 24 555687683 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4048660387 Mar 24 12:33:43 PM PDT 24 Mar 24 12:33:44 PM PDT 24 475972941 ps
T843 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1093951258 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:36 PM PDT 24 367647526 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.419020221 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:26 PM PDT 24 426069847 ps
T845 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.22913035 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:38 PM PDT 24 491722367 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.901613989 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:27 PM PDT 24 471254421 ps
T847 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1533722419 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:42 PM PDT 24 713828371 ps
T848 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1621863696 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:28 PM PDT 24 534281292 ps
T849 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3612066337 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 430284766 ps
T850 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2203608385 Mar 24 12:33:18 PM PDT 24 Mar 24 12:33:20 PM PDT 24 421341229 ps
T851 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1452897933 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:33 PM PDT 24 4948549963 ps
T852 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3845315261 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:38 PM PDT 24 462813434 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3176450793 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 628306565 ps
T854 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1356781515 Mar 24 12:33:41 PM PDT 24 Mar 24 12:33:43 PM PDT 24 501650959 ps
T147 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2540750665 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:21 PM PDT 24 1246573079 ps
T355 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4080297660 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:47 PM PDT 24 8057367284 ps
T855 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3405722263 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:26 PM PDT 24 661264654 ps
T856 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3331786354 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:36 PM PDT 24 465868421 ps
T857 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.942339703 Mar 24 12:33:38 PM PDT 24 Mar 24 12:33:45 PM PDT 24 4078547470 ps
T858 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3365733897 Mar 24 12:33:17 PM PDT 24 Mar 24 12:33:22 PM PDT 24 2194201339 ps
T859 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3478986702 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:37 PM PDT 24 452885265 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4101861717 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:46 PM PDT 24 5258039977 ps
T861 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2044848068 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:31 PM PDT 24 498644769 ps
T148 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.405069479 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:23 PM PDT 24 412130140 ps
T149 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.328440420 Mar 24 12:33:07 PM PDT 24 Mar 24 12:33:14 PM PDT 24 2257967457 ps
T862 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1860948571 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:20 PM PDT 24 433813418 ps
T863 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3299909268 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:52 PM PDT 24 4583592426 ps
T864 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.184632640 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:31 PM PDT 24 535217638 ps
T150 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1191450596 Mar 24 12:33:16 PM PDT 24 Mar 24 12:33:45 PM PDT 24 10675970637 ps
T356 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4161603151 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:28 PM PDT 24 4167793462 ps
T865 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1309437786 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:36 PM PDT 24 454182764 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1492222429 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 425363740 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.46847654 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:32 PM PDT 24 315266268 ps
T868 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1856748113 Mar 24 12:33:35 PM PDT 24 Mar 24 12:33:36 PM PDT 24 366561796 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2761684221 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 370047541 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2844376940 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:33 PM PDT 24 5039149752 ps
T871 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1422111572 Mar 24 12:33:43 PM PDT 24 Mar 24 12:33:45 PM PDT 24 353475961 ps
T872 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.548956204 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 407433607 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1222358078 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 503971481 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3867711850 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:33 PM PDT 24 4649734471 ps
T875 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2226187131 Mar 24 12:33:24 PM PDT 24 Mar 24 12:33:31 PM PDT 24 2487886715 ps
T876 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3569958348 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:25 PM PDT 24 527595046 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.324571930 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:28 PM PDT 24 4668275032 ps
T878 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.945781639 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:35 PM PDT 24 8257495962 ps
T879 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.34018056 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:29 PM PDT 24 534100196 ps
T880 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.297378844 Mar 24 12:33:23 PM PDT 24 Mar 24 12:33:25 PM PDT 24 352495511 ps
T881 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2531233654 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 380929868 ps
T96 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3998352695 Mar 24 12:33:36 PM PDT 24 Mar 24 12:33:57 PM PDT 24 8415685031 ps
T882 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.678990648 Mar 24 12:33:29 PM PDT 24 Mar 24 12:33:31 PM PDT 24 520301918 ps
T883 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2619521309 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 499142503 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1160670476 Mar 24 12:33:19 PM PDT 24 Mar 24 12:33:24 PM PDT 24 969414928 ps
T885 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2838563156 Mar 24 12:33:27 PM PDT 24 Mar 24 12:33:28 PM PDT 24 2303814779 ps
T886 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2175001648 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:50 PM PDT 24 1316641369 ps
T887 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2951282399 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:41 PM PDT 24 357227100 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.373882365 Mar 24 12:33:38 PM PDT 24 Mar 24 12:33:39 PM PDT 24 352469341 ps
T97 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2271384754 Mar 24 12:33:28 PM PDT 24 Mar 24 12:33:51 PM PDT 24 8247039745 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.926796208 Mar 24 12:33:06 PM PDT 24 Mar 24 12:33:09 PM PDT 24 739641926 ps
T890 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4280595306 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:17 PM PDT 24 376831863 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1120624767 Mar 24 12:33:14 PM PDT 24 Mar 24 12:33:15 PM PDT 24 415159214 ps
T892 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1056167660 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:32 PM PDT 24 8450207687 ps
T893 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1304842246 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:35 PM PDT 24 452983159 ps
T894 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2678968514 Mar 24 12:33:39 PM PDT 24 Mar 24 12:33:46 PM PDT 24 487318964 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1040011521 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:23 PM PDT 24 438791775 ps
T896 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2040675250 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:17 PM PDT 24 553797827 ps
T897 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.319405402 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:32 PM PDT 24 297992845 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2010945673 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:13 PM PDT 24 559243999 ps
T899 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2657479132 Mar 24 12:33:32 PM PDT 24 Mar 24 12:33:33 PM PDT 24 411505583 ps
T900 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2703962565 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:25 PM PDT 24 2501040361 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.218247055 Mar 24 12:33:12 PM PDT 24 Mar 24 12:33:16 PM PDT 24 4137216266 ps
T902 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.513180582 Mar 24 12:33:20 PM PDT 24 Mar 24 12:33:25 PM PDT 24 882094439 ps
T903 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2842630857 Mar 24 12:33:14 PM PDT 24 Mar 24 12:33:16 PM PDT 24 701099542 ps
T904 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.138456029 Mar 24 12:33:05 PM PDT 24 Mar 24 12:34:15 PM PDT 24 52652822941 ps
T357 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2572696795 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:48 PM PDT 24 8154697513 ps
T905 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.447093767 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:35 PM PDT 24 447400970 ps
T906 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.283714965 Mar 24 12:33:13 PM PDT 24 Mar 24 12:33:15 PM PDT 24 523130571 ps
T907 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1425020639 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:37 PM PDT 24 2045881478 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2095167092 Mar 24 12:33:21 PM PDT 24 Mar 24 12:33:23 PM PDT 24 403021399 ps
T909 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3016670503 Mar 24 12:33:56 PM PDT 24 Mar 24 12:33:57 PM PDT 24 432475237 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.311986975 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:41 PM PDT 24 2492590822 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4041348161 Mar 24 12:33:37 PM PDT 24 Mar 24 12:33:39 PM PDT 24 598087416 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3502719191 Mar 24 12:33:32 PM PDT 24 Mar 24 12:33:38 PM PDT 24 2310675163 ps
T913 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.318292737 Mar 24 12:33:38 PM PDT 24 Mar 24 12:33:39 PM PDT 24 533704520 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4149451968 Mar 24 12:33:26 PM PDT 24 Mar 24 12:33:40 PM PDT 24 3264455158 ps
T915 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3556304116 Mar 24 12:33:11 PM PDT 24 Mar 24 12:33:14 PM PDT 24 538887225 ps
T916 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1704348731 Mar 24 12:33:15 PM PDT 24 Mar 24 12:33:22 PM PDT 24 2642957586 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.273260093 Mar 24 12:33:30 PM PDT 24 Mar 24 12:33:37 PM PDT 24 5343694414 ps
T918 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3289076427 Mar 24 12:33:25 PM PDT 24 Mar 24 12:33:28 PM PDT 24 415125322 ps
T919 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1228895231 Mar 24 12:33:34 PM PDT 24 Mar 24 12:33:36 PM PDT 24 445758585 ps

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1638080090
Short name T5
Test name
Test status
Simulation time 203708596880 ps
CPU time 467.87 seconds
Started Mar 24 12:51:34 PM PDT 24
Finished Mar 24 12:59:22 PM PDT 24
Peak memory 201896 kb
Host smart-0b60616a-3c64-4d81-978d-2b1ee3f71ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638080090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1638080090
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3205017306
Short name T31
Test name
Test status
Simulation time 408264466215 ps
CPU time 515 seconds
Started Mar 24 12:55:18 PM PDT 24
Finished Mar 24 01:03:53 PM PDT 24
Peak memory 212588 kb
Host smart-1ca2c9db-7d6e-4382-8abc-addd49ee31a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205017306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3205017306
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1436658549
Short name T65
Test name
Test status
Simulation time 523702714620 ps
CPU time 318.24 seconds
Started Mar 24 12:51:47 PM PDT 24
Finished Mar 24 12:57:05 PM PDT 24
Peak memory 201720 kb
Host smart-61c8e288-3d02-4b45-8c81-be14f95937ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436658549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1436658549
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.993565885
Short name T48
Test name
Test status
Simulation time 35388770952 ps
CPU time 100.35 seconds
Started Mar 24 12:51:17 PM PDT 24
Finished Mar 24 12:52:58 PM PDT 24
Peak memory 210440 kb
Host smart-56f99e38-1bd5-4960-84bd-5a40b566a624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993565885 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.993565885
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1953372098
Short name T40
Test name
Test status
Simulation time 664513707908 ps
CPU time 1266.58 seconds
Started Mar 24 12:51:09 PM PDT 24
Finished Mar 24 01:12:15 PM PDT 24
Peak memory 201760 kb
Host smart-ed4e97e5-3058-4a1e-9800-753da0d5d656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953372098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1953372098
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1582553755
Short name T174
Test name
Test status
Simulation time 493609048912 ps
CPU time 299.76 seconds
Started Mar 24 12:51:11 PM PDT 24
Finished Mar 24 12:56:11 PM PDT 24
Peak memory 201888 kb
Host smart-0a08d5bc-c534-4c75-9507-33eba3c5aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582553755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1582553755
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4143971282
Short name T54
Test name
Test status
Simulation time 546119889856 ps
CPU time 584.25 seconds
Started Mar 24 12:52:19 PM PDT 24
Finished Mar 24 01:02:04 PM PDT 24
Peak memory 210508 kb
Host smart-f20a3bbf-393c-435d-ba4d-9a9107c563d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143971282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4143971282
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.519232738
Short name T197
Test name
Test status
Simulation time 525227733204 ps
CPU time 898.53 seconds
Started Mar 24 12:50:33 PM PDT 24
Finished Mar 24 01:05:32 PM PDT 24
Peak memory 202164 kb
Host smart-25a4efaf-1a5a-4d80-9078-b874066e18cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519232738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.519232738
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.320043125
Short name T16
Test name
Test status
Simulation time 114505427285 ps
CPU time 82.08 seconds
Started Mar 24 12:54:23 PM PDT 24
Finished Mar 24 12:55:45 PM PDT 24
Peak memory 210552 kb
Host smart-738e0790-9030-424e-a3ee-18bfc5279969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320043125 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.320043125
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1503618112
Short name T34
Test name
Test status
Simulation time 543407398696 ps
CPU time 1221.24 seconds
Started Mar 24 12:52:54 PM PDT 24
Finished Mar 24 01:13:16 PM PDT 24
Peak memory 201876 kb
Host smart-5ba3d927-8725-4480-8370-ab9d46d4ad00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503618112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1503618112
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.893548664
Short name T232
Test name
Test status
Simulation time 497086088320 ps
CPU time 205.96 seconds
Started Mar 24 12:54:58 PM PDT 24
Finished Mar 24 12:58:24 PM PDT 24
Peak memory 201920 kb
Host smart-f06319b1-8ff7-49cf-b0df-48a47c628d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893548664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.893548664
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.950646484
Short name T204
Test name
Test status
Simulation time 600904977402 ps
CPU time 1487.88 seconds
Started Mar 24 12:55:17 PM PDT 24
Finished Mar 24 01:20:05 PM PDT 24
Peak memory 201840 kb
Host smart-a0d3d75b-d296-4619-a011-7190b961ebb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950646484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.950646484
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3307909159
Short name T77
Test name
Test status
Simulation time 8001230824 ps
CPU time 8.88 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 201916 kb
Host smart-3bc569e5-bf90-4e2e-988a-5a7915ee551b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307909159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3307909159
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1777024488
Short name T130
Test name
Test status
Simulation time 515951015952 ps
CPU time 278.76 seconds
Started Mar 24 12:52:06 PM PDT 24
Finished Mar 24 12:56:45 PM PDT 24
Peak memory 202176 kb
Host smart-d800abef-115e-4c2a-872d-9a5b2bb1f4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777024488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1777024488
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2872220703
Short name T187
Test name
Test status
Simulation time 324029151247 ps
CPU time 195.72 seconds
Started Mar 24 12:51:23 PM PDT 24
Finished Mar 24 12:54:39 PM PDT 24
Peak memory 201924 kb
Host smart-7b486822-5932-4454-97c6-ce1b2a1c81a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872220703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2872220703
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4050563692
Short name T2
Test name
Test status
Simulation time 167773487720 ps
CPU time 66.48 seconds
Started Mar 24 12:54:15 PM PDT 24
Finished Mar 24 12:55:22 PM PDT 24
Peak memory 202148 kb
Host smart-c9072d43-406e-4dd3-a368-88bfb720e63a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050563692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4050563692
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.814222140
Short name T207
Test name
Test status
Simulation time 546039695161 ps
CPU time 342.73 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:56:11 PM PDT 24
Peak memory 201804 kb
Host smart-a59327ec-5aa3-458f-a6c5-8940f3f8e80b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814222140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.814222140
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4161248989
Short name T89
Test name
Test status
Simulation time 360608047 ps
CPU time 0.82 seconds
Started Mar 24 12:50:54 PM PDT 24
Finished Mar 24 12:50:55 PM PDT 24
Peak memory 201548 kb
Host smart-4a5b16c6-d5a7-4c15-a614-9d2165d14f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161248989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4161248989
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.673679876
Short name T33
Test name
Test status
Simulation time 405526068985 ps
CPU time 1239.71 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 01:11:15 PM PDT 24
Peak memory 202152 kb
Host smart-69da7fff-6301-49be-9f41-186a5b3aa0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673679876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.673679876
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3189174193
Short name T143
Test name
Test status
Simulation time 416989119 ps
CPU time 1.75 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201588 kb
Host smart-b3a453d1-b4a9-4680-a7b3-2aa3a8488fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189174193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3189174193
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.728021772
Short name T228
Test name
Test status
Simulation time 860706272715 ps
CPU time 1857.9 seconds
Started Mar 24 12:51:40 PM PDT 24
Finished Mar 24 01:22:40 PM PDT 24
Peak memory 201764 kb
Host smart-ea59fb0a-092f-49c4-bf1b-8e9be0528d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728021772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
728021772
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.891337055
Short name T85
Test name
Test status
Simulation time 538077298 ps
CPU time 2.53 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201880 kb
Host smart-505f811a-0d07-4036-8635-d254667992aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891337055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.891337055
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3218792110
Short name T246
Test name
Test status
Simulation time 329518161156 ps
CPU time 188.26 seconds
Started Mar 24 12:55:08 PM PDT 24
Finished Mar 24 12:58:17 PM PDT 24
Peak memory 201716 kb
Host smart-9a2daaa8-6be7-4b74-aad7-3c5e709302b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218792110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3218792110
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.954642020
Short name T162
Test name
Test status
Simulation time 329790863911 ps
CPU time 397.29 seconds
Started Mar 24 12:54:39 PM PDT 24
Finished Mar 24 01:01:17 PM PDT 24
Peak memory 201776 kb
Host smart-8bc0a31d-1d48-4644-82ac-bebfc6aeec1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954642020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.954642020
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1750801632
Short name T285
Test name
Test status
Simulation time 510683568341 ps
CPU time 1141.12 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 201864 kb
Host smart-f89a8360-c0db-40a3-97b4-3a0e8da7f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750801632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1750801632
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1929730586
Short name T196
Test name
Test status
Simulation time 538698767533 ps
CPU time 650.34 seconds
Started Mar 24 12:52:45 PM PDT 24
Finished Mar 24 01:03:36 PM PDT 24
Peak memory 201940 kb
Host smart-e9797074-be92-4485-8c84-f0e47023ca4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929730586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1929730586
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2303834232
Short name T194
Test name
Test status
Simulation time 502593785139 ps
CPU time 210.3 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:53:53 PM PDT 24
Peak memory 201856 kb
Host smart-65e719d8-d35b-4254-bca0-24b336c40582
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303834232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2303834232
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1614123037
Short name T298
Test name
Test status
Simulation time 139449859518 ps
CPU time 65.37 seconds
Started Mar 24 12:55:07 PM PDT 24
Finished Mar 24 12:56:13 PM PDT 24
Peak memory 210232 kb
Host smart-66ab14cb-881c-4ca6-9ca4-3ab9c2fcd37d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614123037 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1614123037
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.496383978
Short name T311
Test name
Test status
Simulation time 496301458557 ps
CPU time 597.16 seconds
Started Mar 24 12:55:18 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 201864 kb
Host smart-36ebb4cc-7ebe-4f11-8181-85861ba33f9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496383978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.496383978
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.731384276
Short name T290
Test name
Test status
Simulation time 496227876332 ps
CPU time 756.76 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 01:03:39 PM PDT 24
Peak memory 201868 kb
Host smart-531f9410-61e8-4dca-9fc8-0f41c9f8716f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731384276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.731384276
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1182603595
Short name T247
Test name
Test status
Simulation time 329690286419 ps
CPU time 221.02 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:54:41 PM PDT 24
Peak memory 201924 kb
Host smart-ea4cb4b1-f230-427e-884d-f1a9aceae7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182603595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1182603595
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3993095379
Short name T178
Test name
Test status
Simulation time 510626455192 ps
CPU time 1208.2 seconds
Started Mar 24 12:52:47 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 201816 kb
Host smart-51b811f4-ee24-4308-ad7b-a13ceb23af3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993095379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3993095379
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1119475861
Short name T98
Test name
Test status
Simulation time 7438899319 ps
CPU time 7.15 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:50:22 PM PDT 24
Peak memory 218620 kb
Host smart-4d1537e2-0092-483b-9ef2-4b3581b653bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119475861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1119475861
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.367266467
Short name T281
Test name
Test status
Simulation time 488095468467 ps
CPU time 261.76 seconds
Started Mar 24 12:53:35 PM PDT 24
Finished Mar 24 12:57:57 PM PDT 24
Peak memory 201812 kb
Host smart-fd90398e-63ea-4a3b-9395-70008a112a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367266467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.367266467
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1873039865
Short name T151
Test name
Test status
Simulation time 358605482 ps
CPU time 1.1 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201472 kb
Host smart-c9e73162-d828-4e40-b5cd-d2da5d03ddba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873039865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1873039865
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2245826117
Short name T235
Test name
Test status
Simulation time 362120912287 ps
CPU time 793.72 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 201828 kb
Host smart-48b9ccf0-0ea0-48b4-ac2b-9589a621f26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245826117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2245826117
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3017047099
Short name T303
Test name
Test status
Simulation time 567163434919 ps
CPU time 647.94 seconds
Started Mar 24 12:54:15 PM PDT 24
Finished Mar 24 01:05:03 PM PDT 24
Peak memory 201816 kb
Host smart-92cf7363-e04a-4051-930a-844153e141a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017047099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3017047099
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.964237060
Short name T243
Test name
Test status
Simulation time 493713131715 ps
CPU time 432.8 seconds
Started Mar 24 12:52:14 PM PDT 24
Finished Mar 24 12:59:29 PM PDT 24
Peak memory 201872 kb
Host smart-1c6f60f2-6ea1-4941-9665-404ac1d2d6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964237060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.964237060
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2327702393
Short name T233
Test name
Test status
Simulation time 398638657493 ps
CPU time 238.68 seconds
Started Mar 24 12:53:31 PM PDT 24
Finished Mar 24 12:57:30 PM PDT 24
Peak memory 201836 kb
Host smart-d9a57bc7-c9cd-4234-9105-88496eb7681c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327702393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2327702393
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2290909873
Short name T322
Test name
Test status
Simulation time 592335206406 ps
CPU time 208.82 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:57:56 PM PDT 24
Peak memory 210492 kb
Host smart-008c8e12-c0fb-4dd3-aa3a-ab2886c55014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290909873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2290909873
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3638292138
Short name T58
Test name
Test status
Simulation time 195011481470 ps
CPU time 209.79 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:54:33 PM PDT 24
Peak memory 201904 kb
Host smart-fc0c92b9-0a1e-4678-866e-c37994013413
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638292138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3638292138
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.201874242
Short name T168
Test name
Test status
Simulation time 162881912726 ps
CPU time 61.3 seconds
Started Mar 24 12:51:42 PM PDT 24
Finished Mar 24 12:52:44 PM PDT 24
Peak memory 201736 kb
Host smart-075e4914-f319-4963-b53a-9902792cd941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201874242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.201874242
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2844150546
Short name T175
Test name
Test status
Simulation time 487368822210 ps
CPU time 1072.84 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 01:08:34 PM PDT 24
Peak memory 201920 kb
Host smart-f7ef0cf3-b9e8-4aef-82d4-c1207e8122d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844150546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2844150546
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2653507787
Short name T229
Test name
Test status
Simulation time 330630534686 ps
CPU time 125.12 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:52:55 PM PDT 24
Peak memory 201752 kb
Host smart-2770b7aa-1de5-409c-9ee1-90472e3241f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653507787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2653507787
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2038493367
Short name T317
Test name
Test status
Simulation time 500386025687 ps
CPU time 1122.8 seconds
Started Mar 24 12:51:15 PM PDT 24
Finished Mar 24 01:09:58 PM PDT 24
Peak memory 201924 kb
Host smart-43c541d9-8ba2-4611-a379-ac02b66a2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038493367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2038493367
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2968557647
Short name T273
Test name
Test status
Simulation time 563156383515 ps
CPU time 1294.26 seconds
Started Mar 24 12:53:05 PM PDT 24
Finished Mar 24 01:14:40 PM PDT 24
Peak memory 201836 kb
Host smart-2cc2cdd4-2855-43e6-af7c-8045ce7b5b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968557647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2968557647
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1253653437
Short name T294
Test name
Test status
Simulation time 165548541318 ps
CPU time 54.62 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:51:23 PM PDT 24
Peak memory 201868 kb
Host smart-6cfb7ddd-b0bf-4909-b010-0e2ce27d8b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253653437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1253653437
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2540252823
Short name T289
Test name
Test status
Simulation time 324105744733 ps
CPU time 378.57 seconds
Started Mar 24 12:51:17 PM PDT 24
Finished Mar 24 12:57:36 PM PDT 24
Peak memory 201928 kb
Host smart-6186b79a-8f9e-481f-a8d7-bb8cef6fd2dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540252823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2540252823
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1755203812
Short name T258
Test name
Test status
Simulation time 215574328912 ps
CPU time 237.86 seconds
Started Mar 24 12:53:38 PM PDT 24
Finished Mar 24 12:57:36 PM PDT 24
Peak memory 201836 kb
Host smart-882ac6fc-a507-46e3-b987-4a78d6903806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755203812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1755203812
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2535750765
Short name T276
Test name
Test status
Simulation time 403796413502 ps
CPU time 779.24 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 01:03:23 PM PDT 24
Peak memory 201836 kb
Host smart-5964abc2-20d0-4753-a2d7-0b7f204e61ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535750765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2535750765
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3161977957
Short name T293
Test name
Test status
Simulation time 171733693891 ps
CPU time 105.55 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:52:06 PM PDT 24
Peak memory 202184 kb
Host smart-d882b058-2929-40f5-8252-26748605636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161977957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3161977957
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1778015324
Short name T308
Test name
Test status
Simulation time 72957668309 ps
CPU time 137.1 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:52:34 PM PDT 24
Peak memory 202572 kb
Host smart-72754965-864a-4f3d-b4c1-fe48b0972267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778015324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1778015324
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3574719325
Short name T52
Test name
Test status
Simulation time 27786684939 ps
CPU time 36.16 seconds
Started Mar 24 12:52:17 PM PDT 24
Finished Mar 24 12:52:54 PM PDT 24
Peak memory 201972 kb
Host smart-373ee940-27aa-4342-8344-39c7b757022f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574719325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3574719325
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.18471936
Short name T50
Test name
Test status
Simulation time 379129834955 ps
CPU time 380.67 seconds
Started Mar 24 12:52:58 PM PDT 24
Finished Mar 24 12:59:19 PM PDT 24
Peak memory 210572 kb
Host smart-82fc7b06-08e8-41a0-8d39-5433474e7d10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18471936 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.18471936
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.33015890
Short name T198
Test name
Test status
Simulation time 575231703708 ps
CPU time 330.58 seconds
Started Mar 24 12:53:08 PM PDT 24
Finished Mar 24 12:58:38 PM PDT 24
Peak memory 201916 kb
Host smart-fd3a8327-dc1c-4a7d-925b-f54100dd5c92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_w
akeup.33015890
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3039657137
Short name T343
Test name
Test status
Simulation time 340270382125 ps
CPU time 213.23 seconds
Started Mar 24 12:53:18 PM PDT 24
Finished Mar 24 12:56:51 PM PDT 24
Peak memory 201812 kb
Host smart-97b41281-5ea9-4470-b672-dd80648d4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039657137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3039657137
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4186581748
Short name T313
Test name
Test status
Simulation time 590794631373 ps
CPU time 972.75 seconds
Started Mar 24 12:53:41 PM PDT 24
Finished Mar 24 01:09:54 PM PDT 24
Peak memory 202160 kb
Host smart-dca1ada9-3fbe-4dc2-adc8-e474c4353156
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186581748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4186581748
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3106213425
Short name T15
Test name
Test status
Simulation time 412203374186 ps
CPU time 561.51 seconds
Started Mar 24 12:50:34 PM PDT 24
Finished Mar 24 12:59:55 PM PDT 24
Peak memory 210636 kb
Host smart-4bf2def5-bb07-4aad-95d3-a663b2eb6eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106213425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3106213425
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4036293759
Short name T87
Test name
Test status
Simulation time 966640701 ps
CPU time 1.81 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:24 PM PDT 24
Peak memory 201912 kb
Host smart-ea31bc63-2a84-46d1-a6ea-47f235ec8f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036293759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4036293759
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2459987584
Short name T219
Test name
Test status
Simulation time 375991350607 ps
CPU time 2028.52 seconds
Started Mar 24 12:50:36 PM PDT 24
Finished Mar 24 01:24:24 PM PDT 24
Peak memory 202252 kb
Host smart-c946e24f-0ecc-47c2-9cba-67239becd041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459987584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2459987584
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3888663768
Short name T129
Test name
Test status
Simulation time 347126021254 ps
CPU time 191.7 seconds
Started Mar 24 12:51:12 PM PDT 24
Finished Mar 24 12:54:24 PM PDT 24
Peak memory 201936 kb
Host smart-5e2a951f-5f88-41a9-9007-58da44a3ac7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888663768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3888663768
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1715286615
Short name T176
Test name
Test status
Simulation time 528587637601 ps
CPU time 1046.74 seconds
Started Mar 24 12:51:15 PM PDT 24
Finished Mar 24 01:08:42 PM PDT 24
Peak memory 201832 kb
Host smart-3fd2c003-b631-425c-acf3-cf070d58efd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715286615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1715286615
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4206198604
Short name T237
Test name
Test status
Simulation time 488555978932 ps
CPU time 1182.66 seconds
Started Mar 24 12:52:22 PM PDT 24
Finished Mar 24 01:12:05 PM PDT 24
Peak memory 201792 kb
Host smart-71dce75a-841c-46a3-92dd-87b67f10c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206198604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4206198604
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1530082075
Short name T349
Test name
Test status
Simulation time 523395977910 ps
CPU time 310.33 seconds
Started Mar 24 12:52:29 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 201948 kb
Host smart-405dfbf4-70e6-4a8a-a263-3e0562aa53c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530082075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1530082075
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.182748063
Short name T346
Test name
Test status
Simulation time 498902270063 ps
CPU time 1234.14 seconds
Started Mar 24 12:54:22 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 201864 kb
Host smart-fbd51b85-6c43-4b09-af01-7c740ddec898
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182748063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.182748063
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3249875383
Short name T179
Test name
Test status
Simulation time 356200523520 ps
CPU time 838.56 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 01:04:23 PM PDT 24
Peak memory 201828 kb
Host smart-9538e84c-e2f0-4956-94ff-0823cb885525
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249875383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3249875383
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4080297660
Short name T355
Test name
Test status
Simulation time 8057367284 ps
CPU time 20.37 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:47 PM PDT 24
Peak memory 201888 kb
Host smart-b3664624-16b5-44e2-967d-9c38677b08ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080297660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4080297660
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2981716008
Short name T344
Test name
Test status
Simulation time 161150666796 ps
CPU time 201.98 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:53:46 PM PDT 24
Peak memory 201796 kb
Host smart-44884c41-38d1-4454-bc40-8244775b6332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981716008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2981716008
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3958994832
Short name T302
Test name
Test status
Simulation time 173160394801 ps
CPU time 400.54 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:57:15 PM PDT 24
Peak memory 201816 kb
Host smart-fb41353e-19c6-40f4-a2ca-f4858025595c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958994832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3958994832
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2565462864
Short name T35
Test name
Test status
Simulation time 528733146311 ps
CPU time 362.03 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:56:59 PM PDT 24
Peak memory 202144 kb
Host smart-148cda36-ecb8-45fb-a7bd-00eb28c89101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565462864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2565462864
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2570129924
Short name T297
Test name
Test status
Simulation time 334632818129 ps
CPU time 797.96 seconds
Started Mar 24 12:51:20 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 201832 kb
Host smart-cca944eb-75b8-4926-af4f-41411e794923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570129924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2570129924
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3331978839
Short name T64
Test name
Test status
Simulation time 503319392393 ps
CPU time 689.56 seconds
Started Mar 24 12:53:05 PM PDT 24
Finished Mar 24 01:04:35 PM PDT 24
Peak memory 212768 kb
Host smart-22e435fc-6236-43b6-91f1-82060e2dde22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331978839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3331978839
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.470771687
Short name T236
Test name
Test status
Simulation time 366943763341 ps
CPU time 873.13 seconds
Started Mar 24 12:53:50 PM PDT 24
Finished Mar 24 01:08:24 PM PDT 24
Peak memory 201880 kb
Host smart-90665089-9167-48a0-9c09-7db4d05dde26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470771687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
470771687
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1155098021
Short name T286
Test name
Test status
Simulation time 506444831462 ps
CPU time 1142.47 seconds
Started Mar 24 12:54:13 PM PDT 24
Finished Mar 24 01:13:16 PM PDT 24
Peak memory 201836 kb
Host smart-383f00ad-99b6-435c-878e-91d3709634f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155098021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1155098021
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3998352695
Short name T96
Test name
Test status
Simulation time 8415685031 ps
CPU time 19.6 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:57 PM PDT 24
Peak memory 201944 kb
Host smart-d48454f0-2112-4179-b593-338de7c33d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998352695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3998352695
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3729027040
Short name T224
Test name
Test status
Simulation time 126236218241 ps
CPU time 432.15 seconds
Started Mar 24 12:50:45 PM PDT 24
Finished Mar 24 12:57:58 PM PDT 24
Peak memory 202384 kb
Host smart-1840160c-711e-4e5d-91e0-15804aca3919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729027040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3729027040
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2680474562
Short name T20
Test name
Test status
Simulation time 105007249966 ps
CPU time 266.97 seconds
Started Mar 24 12:50:44 PM PDT 24
Finished Mar 24 12:55:12 PM PDT 24
Peak memory 210396 kb
Host smart-2a5327aa-fba8-423c-a0c1-c52515b732bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680474562 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2680474562
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.4208126514
Short name T335
Test name
Test status
Simulation time 181173339925 ps
CPU time 445.81 seconds
Started Mar 24 12:51:05 PM PDT 24
Finished Mar 24 12:58:31 PM PDT 24
Peak memory 201824 kb
Host smart-82b6ef32-6fcc-466b-a7a4-4e39ff0db08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208126514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.4208126514
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.924258885
Short name T269
Test name
Test status
Simulation time 123942301653 ps
CPU time 66.75 seconds
Started Mar 24 12:52:32 PM PDT 24
Finished Mar 24 12:53:39 PM PDT 24
Peak memory 210192 kb
Host smart-8864edc6-416b-49df-b63b-d50e807932b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924258885 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.924258885
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.955445370
Short name T164
Test name
Test status
Simulation time 163373101710 ps
CPU time 41.74 seconds
Started Mar 24 12:52:34 PM PDT 24
Finished Mar 24 12:53:16 PM PDT 24
Peak memory 202156 kb
Host smart-17af4adc-00c2-491a-bcce-4d8aa15ea2b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955445370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.955445370
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.414641215
Short name T318
Test name
Test status
Simulation time 140638681806 ps
CPU time 379.62 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 12:58:56 PM PDT 24
Peak memory 216308 kb
Host smart-293c9c0a-234f-454a-b8db-bd3a7d5dc356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414641215 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.414641215
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.751437593
Short name T301
Test name
Test status
Simulation time 525762488394 ps
CPU time 630.02 seconds
Started Mar 24 12:54:33 PM PDT 24
Finished Mar 24 01:05:03 PM PDT 24
Peak memory 201812 kb
Host smart-afa5e927-f5f2-493d-aa68-f6e1faa22304
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751437593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.751437593
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3582775345
Short name T225
Test name
Test status
Simulation time 118097615809 ps
CPU time 520.48 seconds
Started Mar 24 12:54:49 PM PDT 24
Finished Mar 24 01:03:30 PM PDT 24
Peak memory 202208 kb
Host smart-f18a3fb6-c396-4d29-aa81-a968ca0babe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582775345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3582775345
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2748927579
Short name T137
Test name
Test status
Simulation time 703633729 ps
CPU time 3.08 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:19 PM PDT 24
Peak memory 201780 kb
Host smart-b2b50192-f335-4855-b009-63383d4edf47
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748927579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2748927579
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4149451968
Short name T914
Test name
Test status
Simulation time 3264455158 ps
CPU time 9.22 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:40 PM PDT 24
Peak memory 201968 kb
Host smart-e3081af7-8414-4417-b765-0849269cd05e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149451968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4149451968
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2540750665
Short name T147
Test name
Test status
Simulation time 1246573079 ps
CPU time 3.69 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:21 PM PDT 24
Peak memory 201588 kb
Host smart-f81849f3-104a-4696-ad51-099a99a52ec3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540750665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2540750665
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3176450793
Short name T853
Test name
Test status
Simulation time 628306565 ps
CPU time 1.31 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201696 kb
Host smart-b3666cea-b241-42ec-ae28-481519e88b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176450793 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3176450793
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1075746274
Short name T146
Test name
Test status
Simulation time 398128433 ps
CPU time 1.71 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:30 PM PDT 24
Peak memory 201576 kb
Host smart-3f4ce730-2d38-4b47-9139-ac5dae6f267d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075746274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1075746274
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.901613989
Short name T846
Test name
Test status
Simulation time 471254421 ps
CPU time 1.66 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:27 PM PDT 24
Peak memory 201548 kb
Host smart-1430469c-c6d3-49bc-ab75-2e3bdf160d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901613989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.901613989
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.218247055
Short name T901
Test name
Test status
Simulation time 4137216266 ps
CPU time 3.24 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:16 PM PDT 24
Peak memory 201904 kb
Host smart-0cf49b87-e6cd-437b-b7f9-b20b7d975089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218247055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.218247055
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1160670476
Short name T884
Test name
Test status
Simulation time 969414928 ps
CPU time 2.25 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:24 PM PDT 24
Peak memory 201860 kb
Host smart-e3f2a1d1-014f-4345-99f0-c015413c46af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160670476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1160670476
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.945781639
Short name T878
Test name
Test status
Simulation time 8257495962 ps
CPU time 21.55 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201880 kb
Host smart-0cf14175-e033-4c0f-a99b-a8403bb037f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945781639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.945781639
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3909720560
Short name T156
Test name
Test status
Simulation time 874070373 ps
CPU time 2.41 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:27 PM PDT 24
Peak memory 201848 kb
Host smart-c94ef2c9-4873-4b1c-b7e1-0558146140ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909720560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3909720560
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1191450596
Short name T150
Test name
Test status
Simulation time 10675970637 ps
CPU time 29.15 seconds
Started Mar 24 12:33:16 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 201936 kb
Host smart-657a6bd1-a422-4557-811a-1581763de227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191450596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1191450596
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2614884477
Short name T138
Test name
Test status
Simulation time 1080445013 ps
CPU time 1.36 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 201616 kb
Host smart-180f94dc-8f78-493e-b1c9-d4ebad11b1e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614884477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2614884477
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.419020221
Short name T844
Test name
Test status
Simulation time 426069847 ps
CPU time 1.55 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 201800 kb
Host smart-76b41576-53ca-474f-af49-7a7316c36a5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419020221 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.419020221
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4290645923
Short name T144
Test name
Test status
Simulation time 383549838 ps
CPU time 1.24 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201616 kb
Host smart-957f5e4d-9f0c-4f21-b6be-fa0c07e31909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290645923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4290645923
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1120624767
Short name T891
Test name
Test status
Simulation time 415159214 ps
CPU time 0.98 seconds
Started Mar 24 12:33:14 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 201580 kb
Host smart-1c60625f-aa5e-4d06-94ac-b530c1fa9111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120624767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1120624767
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.273260093
Short name T917
Test name
Test status
Simulation time 5343694414 ps
CPU time 6.16 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 201952 kb
Host smart-6e77d3cd-9a5f-44a9-ab61-a110dc45dc07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273260093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.273260093
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2126861272
Short name T841
Test name
Test status
Simulation time 555687683 ps
CPU time 2.64 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:24 PM PDT 24
Peak memory 201912 kb
Host smart-2cb8ff0f-6abb-42f4-a012-7e73788626ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126861272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2126861272
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1056167660
Short name T892
Test name
Test status
Simulation time 8450207687 ps
CPU time 4.83 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201880 kb
Host smart-9c2eff72-9e73-4c6e-8e85-820498d990f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056167660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1056167660
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3506814719
Short name T823
Test name
Test status
Simulation time 556366139 ps
CPU time 2.13 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201616 kb
Host smart-e24d4d5e-cf1f-461d-8248-4a17252f3d5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506814719 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3506814719
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1685216134
Short name T812
Test name
Test status
Simulation time 464987093 ps
CPU time 1.67 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 201580 kb
Host smart-010bc862-f976-4174-b4a9-442f485de3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685216134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1685216134
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2703962565
Short name T900
Test name
Test status
Simulation time 2501040361 ps
CPU time 2.92 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201692 kb
Host smart-2929a6c2-9581-4c6c-9efe-85e5e0c8b111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703962565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2703962565
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2212363039
Short name T832
Test name
Test status
Simulation time 596312924 ps
CPU time 1.58 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201904 kb
Host smart-7d9e330d-21ea-4537-acc8-716418923307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212363039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2212363039
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.570109330
Short name T810
Test name
Test status
Simulation time 708510530 ps
CPU time 1.24 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201636 kb
Host smart-2f9545cc-06b8-4dee-abd9-ee73a85bd209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570109330 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.570109330
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.405069479
Short name T148
Test name
Test status
Simulation time 412130140 ps
CPU time 0.99 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201608 kb
Host smart-d584e766-0fca-49d7-8774-255b3af2dacc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405069479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.405069479
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.591474875
Short name T808
Test name
Test status
Simulation time 313168437 ps
CPU time 0.95 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201616 kb
Host smart-db21cc96-1ec6-4fc5-b2e9-5fbb396aaf9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591474875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.591474875
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.157571906
Short name T155
Test name
Test status
Simulation time 2561347901 ps
CPU time 1.78 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201708 kb
Host smart-62ffb6db-1011-4880-b6b2-492a6896f162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157571906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.157571906
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3478986702
Short name T859
Test name
Test status
Simulation time 452885265 ps
CPU time 2.47 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 201872 kb
Host smart-606e6b75-9f6a-47d8-8b16-3cc0e7ec9df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478986702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3478986702
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2664176913
Short name T360
Test name
Test status
Simulation time 4102712025 ps
CPU time 12.38 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201924 kb
Host smart-7065f607-70b7-45a7-8a05-3b2408b55f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664176913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2664176913
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4041348161
Short name T911
Test name
Test status
Simulation time 598087416 ps
CPU time 1.6 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 210024 kb
Host smart-29624d13-3569-464b-96a6-5f593b6765b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041348161 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4041348161
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.46847654
Short name T867
Test name
Test status
Simulation time 315266268 ps
CPU time 1.49 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201572 kb
Host smart-fa5c8902-fecf-47b5-a0f1-620e47740944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46847654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.46847654
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.373882365
Short name T888
Test name
Test status
Simulation time 352469341 ps
CPU time 0.86 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 201568 kb
Host smart-d31cb2b2-9e01-4d19-9766-9d97d72ad84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373882365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.373882365
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2838563156
Short name T885
Test name
Test status
Simulation time 2303814779 ps
CPU time 1.45 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201740 kb
Host smart-f5175aa9-e37f-4def-a122-0a5337aff086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838563156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2838563156
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4272871475
Short name T354
Test name
Test status
Simulation time 4632534917 ps
CPU time 4 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:34 PM PDT 24
Peak memory 201912 kb
Host smart-dd887e6c-c8ad-47f8-b3d9-7f1421c9587f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272871475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4272871475
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2203608385
Short name T850
Test name
Test status
Simulation time 421341229 ps
CPU time 1.36 seconds
Started Mar 24 12:33:18 PM PDT 24
Finished Mar 24 12:33:20 PM PDT 24
Peak memory 201636 kb
Host smart-e3e1de5b-7108-4373-9efe-27ec0426213c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203608385 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2203608385
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2951282399
Short name T887
Test name
Test status
Simulation time 357227100 ps
CPU time 1.69 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201596 kb
Host smart-89ee624f-5420-4b77-81c6-c801d0ac3363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951282399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2951282399
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.297378844
Short name T880
Test name
Test status
Simulation time 352495511 ps
CPU time 0.77 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201336 kb
Host smart-b19f0a89-1dea-4a17-a543-5e482d51cfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297378844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.297378844
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3867711850
Short name T874
Test name
Test status
Simulation time 4649734471 ps
CPU time 10.83 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201068 kb
Host smart-c09487f6-46f8-4cf2-a892-04bf2999bf29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867711850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3867711850
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2060150259
Short name T826
Test name
Test status
Simulation time 467248737 ps
CPU time 1.37 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201628 kb
Host smart-a2e7ee8b-a04a-4be1-b798-7fb5f41eebd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060150259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2060150259
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.942339703
Short name T857
Test name
Test status
Simulation time 4078547470 ps
CPU time 6.5 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 202416 kb
Host smart-97a350c8-8559-4671-8cc3-70b1a9bdbb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942339703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.942339703
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1072208786
Short name T838
Test name
Test status
Simulation time 574958467 ps
CPU time 1.44 seconds
Started Mar 24 12:33:52 PM PDT 24
Finished Mar 24 12:33:54 PM PDT 24
Peak memory 201816 kb
Host smart-9ae24047-5c64-4f84-9b54-325c38d0c403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072208786 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1072208786
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3642498503
Short name T817
Test name
Test status
Simulation time 612916350 ps
CPU time 0.82 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:16 PM PDT 24
Peak memory 201604 kb
Host smart-558c90e0-40e1-4609-98ea-214e302180ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642498503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3642498503
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2095167092
Short name T908
Test name
Test status
Simulation time 403021399 ps
CPU time 1.57 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201580 kb
Host smart-154b1b9d-d66a-4f8a-af34-865e3de34b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095167092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2095167092
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2226187131
Short name T875
Test name
Test status
Simulation time 2487886715 ps
CPU time 6.23 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201740 kb
Host smart-4ae024ba-d97b-4f08-bfad-2ddd2d6ebc5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226187131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2226187131
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2044848068
Short name T861
Test name
Test status
Simulation time 498644769 ps
CPU time 1.96 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201704 kb
Host smart-a7dce07f-e9c5-4f27-bda8-123a2f7283f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044848068 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2044848068
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1860948571
Short name T862
Test name
Test status
Simulation time 433813418 ps
CPU time 1.1 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:20 PM PDT 24
Peak memory 201548 kb
Host smart-77102b99-b4e6-4e3e-878e-53f3390638b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860948571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1860948571
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.740562041
Short name T73
Test name
Test status
Simulation time 4736375848 ps
CPU time 23.69 seconds
Started Mar 24 12:33:45 PM PDT 24
Finished Mar 24 12:34:09 PM PDT 24
Peak memory 201964 kb
Host smart-765242f9-fbcc-401a-8831-f288865afaee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740562041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.740562041
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.606540637
Short name T824
Test name
Test status
Simulation time 552010051 ps
CPU time 2.66 seconds
Started Mar 24 12:33:44 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 201904 kb
Host smart-1d804701-a5a5-4d18-b7bc-dd39df2eacc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606540637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.606540637
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1200695361
Short name T358
Test name
Test status
Simulation time 4267043576 ps
CPU time 5.91 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201844 kb
Host smart-16d1a042-b146-4a1f-ad4e-3debbe6b2775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200695361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1200695361
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4266833823
Short name T811
Test name
Test status
Simulation time 458537890 ps
CPU time 1.44 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201684 kb
Host smart-bd507036-a81f-4fa2-91f7-31b03eb9163d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266833823 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.4266833823
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2794010586
Short name T139
Test name
Test status
Simulation time 325647066 ps
CPU time 1.54 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201580 kb
Host smart-556baf97-c2ea-465c-8605-2e0ccf2376ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794010586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2794010586
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1880934811
Short name T815
Test name
Test status
Simulation time 449956600 ps
CPU time 0.76 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201632 kb
Host smart-cc0bb57c-184b-47ab-841b-b8e7e26d2673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880934811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1880934811
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1425020639
Short name T907
Test name
Test status
Simulation time 2045881478 ps
CPU time 6.39 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:37 PM PDT 24
Peak memory 201608 kb
Host smart-a47bb8ee-5511-4e13-942d-25fd4572dd58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425020639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1425020639
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2842630857
Short name T903
Test name
Test status
Simulation time 701099542 ps
CPU time 2.18 seconds
Started Mar 24 12:33:14 PM PDT 24
Finished Mar 24 12:33:16 PM PDT 24
Peak memory 201872 kb
Host smart-464922b1-714a-46e5-86df-eec94fa5fb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842630857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2842630857
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1534663727
Short name T78
Test name
Test status
Simulation time 4296615911 ps
CPU time 3.98 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201928 kb
Host smart-4ffa09cb-15ff-487d-a12f-9f9faa3862a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534663727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1534663727
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3405722263
Short name T855
Test name
Test status
Simulation time 661264654 ps
CPU time 2.36 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 202052 kb
Host smart-19d43b1f-643c-4afd-a5bc-14484dfb73ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405722263 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3405722263
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.675034381
Short name T154
Test name
Test status
Simulation time 454697736 ps
CPU time 0.94 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201560 kb
Host smart-f73ab621-5ed5-4092-9c1b-00b2a04382a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675034381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.675034381
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2509499433
Short name T834
Test name
Test status
Simulation time 380643915 ps
CPU time 1.52 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201592 kb
Host smart-f359bc24-854f-42a1-81eb-a49334d3722d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509499433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2509499433
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2712800698
Short name T76
Test name
Test status
Simulation time 2473923177 ps
CPU time 3.27 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201712 kb
Host smart-e7859014-4e4f-4d5b-b4df-7aac0a1205ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712800698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2712800698
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2261664463
Short name T90
Test name
Test status
Simulation time 578545894 ps
CPU time 3.29 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:34 PM PDT 24
Peak memory 218260 kb
Host smart-b243f527-db6e-4445-beae-d32306be27e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261664463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2261664463
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4161603151
Short name T356
Test name
Test status
Simulation time 4167793462 ps
CPU time 3.91 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201932 kb
Host smart-67765136-378a-4350-8246-ad70b82cc88a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161603151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4161603151
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.184632640
Short name T864
Test name
Test status
Simulation time 535217638 ps
CPU time 1.1 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201676 kb
Host smart-09895cb0-9b41-4dc1-a4d9-3c937d8d9a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184632640 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.184632640
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2246140751
Short name T829
Test name
Test status
Simulation time 521384835 ps
CPU time 0.87 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201620 kb
Host smart-8a3238dc-2217-4d3d-b320-eba910fd2d67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246140751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2246140751
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3612066337
Short name T849
Test name
Test status
Simulation time 430284766 ps
CPU time 0.86 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201628 kb
Host smart-fbc6e80d-2006-425c-87c1-f3950495ded4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612066337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3612066337
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3299909268
Short name T863
Test name
Test status
Simulation time 4583592426 ps
CPU time 17.61 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 202004 kb
Host smart-fd13f0d3-86d4-4d85-9419-d4cb566ac289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299909268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3299909268
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1088825885
Short name T86
Test name
Test status
Simulation time 489983755 ps
CPU time 3.03 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201880 kb
Host smart-43b247a0-8c8f-46ab-8cff-cda1458a2343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088825885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1088825885
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.926348561
Short name T820
Test name
Test status
Simulation time 7677915320 ps
CPU time 19.71 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 201944 kb
Host smart-6f3dd07c-f737-400b-8025-c4a5d25034cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926348561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.926348561
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2761684221
Short name T869
Test name
Test status
Simulation time 370047541 ps
CPU time 1.45 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201652 kb
Host smart-f6493108-49a4-4ad5-b85b-978eab41fdb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761684221 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2761684221
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1492222429
Short name T866
Test name
Test status
Simulation time 425363740 ps
CPU time 0.97 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201620 kb
Host smart-4280f209-1e64-483f-a731-4d5c090ba399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492222429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1492222429
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.874217894
Short name T804
Test name
Test status
Simulation time 496483621 ps
CPU time 1.26 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201992 kb
Host smart-50dd789f-ee71-4e9f-96ae-95ca79f1b2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874217894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.874217894
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3288658784
Short name T75
Test name
Test status
Simulation time 4358478647 ps
CPU time 13.95 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:34:03 PM PDT 24
Peak memory 201908 kb
Host smart-419a17fb-629f-4122-95d6-4790f50472a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288658784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3288658784
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3144416086
Short name T827
Test name
Test status
Simulation time 602890908 ps
CPU time 2.68 seconds
Started Mar 24 12:33:49 PM PDT 24
Finished Mar 24 12:33:52 PM PDT 24
Peak memory 201860 kb
Host smart-53c01d8a-8684-47b7-a61f-faf852c2a695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144416086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3144416086
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2175001648
Short name T886
Test name
Test status
Simulation time 1316641369 ps
CPU time 3.05 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:50 PM PDT 24
Peak memory 201768 kb
Host smart-0f37d93d-246a-4a12-923a-3ef9ed8610f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175001648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2175001648
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1816995479
Short name T825
Test name
Test status
Simulation time 26432926888 ps
CPU time 30.02 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 202312 kb
Host smart-ec9b6d47-ee8f-47ec-9d39-5477973594a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816995479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1816995479
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2860978824
Short name T840
Test name
Test status
Simulation time 1233675919 ps
CPU time 1.49 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201632 kb
Host smart-6b2bce42-a4c8-4659-b07f-ea4a49130dec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860978824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2860978824
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.6922532
Short name T816
Test name
Test status
Simulation time 485166698 ps
CPU time 1.08 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:27 PM PDT 24
Peak memory 201652 kb
Host smart-cc82352e-09c1-4549-9a39-ac85342cb4b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6922532 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.6922532
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.678990648
Short name T882
Test name
Test status
Simulation time 520301918 ps
CPU time 1.07 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201604 kb
Host smart-b4bac6c8-f03e-4228-87bf-7aa9c6ebd8eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678990648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.678990648
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4280595306
Short name T890
Test name
Test status
Simulation time 376831863 ps
CPU time 1.44 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 201584 kb
Host smart-8bcf40ba-9c68-433f-88e8-12f35062e5ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280595306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4280595306
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1704348731
Short name T916
Test name
Test status
Simulation time 2642957586 ps
CPU time 6.55 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:22 PM PDT 24
Peak memory 201932 kb
Host smart-b6220e76-f153-4979-8c09-c9d0045ed8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704348731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1704348731
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3289076427
Short name T918
Test name
Test status
Simulation time 415125322 ps
CPU time 3.38 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201864 kb
Host smart-6cb9b3cd-bb2c-4c39-baa7-1c333c669994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289076427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3289076427
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2711155283
Short name T79
Test name
Test status
Simulation time 8835932154 ps
CPU time 21.38 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 201944 kb
Host smart-cfb7f20b-2da0-4ed9-a316-c1ef484b71f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711155283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2711155283
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2657479132
Short name T899
Test name
Test status
Simulation time 411505583 ps
CPU time 0.77 seconds
Started Mar 24 12:33:32 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201544 kb
Host smart-65cf5317-144d-491e-8807-0fb095247de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657479132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2657479132
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2678968514
Short name T894
Test name
Test status
Simulation time 487318964 ps
CPU time 1.61 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 201564 kb
Host smart-c7e16411-fdfe-499b-9e7f-bc791fb0244f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678968514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2678968514
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.263241260
Short name T814
Test name
Test status
Simulation time 293429045 ps
CPU time 0.99 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201544 kb
Host smart-57cbb470-5a1b-4f21-bbf4-d7838401cc33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263241260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.263241260
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3331786354
Short name T856
Test name
Test status
Simulation time 465868421 ps
CPU time 0.87 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201592 kb
Host smart-f1766879-9b80-4c09-8ea3-22bfeabf887a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331786354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3331786354
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1422111572
Short name T871
Test name
Test status
Simulation time 353475961 ps
CPU time 1.04 seconds
Started Mar 24 12:33:43 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 201988 kb
Host smart-3a431bf1-5e8f-4247-ab01-1bc88002d778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422111572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1422111572
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.548956204
Short name T872
Test name
Test status
Simulation time 407433607 ps
CPU time 1.05 seconds
Started Mar 24 12:33:47 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 201576 kb
Host smart-a3ca587a-7286-45d3-bf05-b21e101c318f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548956204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.548956204
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1488596237
Short name T835
Test name
Test status
Simulation time 309207618 ps
CPU time 1.35 seconds
Started Mar 24 12:33:19 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201608 kb
Host smart-8be376ad-2f73-43ec-b3f8-9e49fa8f9651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488596237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1488596237
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.340852455
Short name T800
Test name
Test status
Simulation time 407252689 ps
CPU time 1.12 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201596 kb
Host smart-65e19796-0098-4fbe-ba63-77666925a01d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340852455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.340852455
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.34018056
Short name T879
Test name
Test status
Simulation time 534100196 ps
CPU time 1 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201608 kb
Host smart-1b681054-8f21-431f-856b-7268a92eb881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.34018056
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3948934438
Short name T805
Test name
Test status
Simulation time 416203680 ps
CPU time 0.71 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 201612 kb
Host smart-e9db621b-c368-4e67-bb0c-d3fe6b1a2493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948934438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3948934438
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3333633166
Short name T145
Test name
Test status
Simulation time 777561959 ps
CPU time 4.19 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 201828 kb
Host smart-efcda472-74b5-481c-966b-44f0a0908620
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333633166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3333633166
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.328440420
Short name T149
Test name
Test status
Simulation time 2257967457 ps
CPU time 4.44 seconds
Started Mar 24 12:33:07 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 201892 kb
Host smart-b4350d73-a96f-452a-aadd-2a1fa0c94be9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328440420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.328440420
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1724023851
Short name T142
Test name
Test status
Simulation time 1309920025 ps
CPU time 1.49 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:26 PM PDT 24
Peak memory 201616 kb
Host smart-2d1c15d4-75e1-41ad-9a61-92317f68bfb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724023851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1724023851
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1222358078
Short name T873
Test name
Test status
Simulation time 503971481 ps
CPU time 1.28 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201688 kb
Host smart-28cac5d3-7d2f-42d1-a7f1-e1ac46ccbfa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222358078 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1222358078
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3556304116
Short name T915
Test name
Test status
Simulation time 538887225 ps
CPU time 2.25 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:14 PM PDT 24
Peak memory 201596 kb
Host smart-b7b9e062-1433-4688-8379-9b6bc4157528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556304116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3556304116
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1743054926
Short name T813
Test name
Test status
Simulation time 344512632 ps
CPU time 0.76 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201616 kb
Host smart-cd05a844-8073-46a5-9c49-5563c194e401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743054926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1743054926
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4101861717
Short name T860
Test name
Test status
Simulation time 5258039977 ps
CPU time 20.48 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:46 PM PDT 24
Peak memory 201924 kb
Host smart-bb9c6a17-316a-4133-8815-ba569ecc72df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101861717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4101861717
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3940450200
Short name T92
Test name
Test status
Simulation time 640672143 ps
CPU time 2.12 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201912 kb
Host smart-dbc2dd0b-7b4c-48c7-a82a-f86eabec6927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940450200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3940450200
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1156698367
Short name T809
Test name
Test status
Simulation time 4446701909 ps
CPU time 12.48 seconds
Started Mar 24 12:33:01 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 201872 kb
Host smart-3ebc4e4f-d842-4546-81a8-e2d209411864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156698367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1156698367
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.668247599
Short name T818
Test name
Test status
Simulation time 418028889 ps
CPU time 1.58 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201520 kb
Host smart-f61533b8-3f75-4dbc-9be7-282a10da69fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668247599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.668247599
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1228895231
Short name T919
Test name
Test status
Simulation time 445758585 ps
CPU time 1.78 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201592 kb
Host smart-0ddd1d31-b0c4-49ec-bfed-6a14765aa262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228895231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1228895231
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1309437786
Short name T865
Test name
Test status
Simulation time 454182764 ps
CPU time 1.25 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201612 kb
Host smart-44bc6b2c-80e6-42fe-9728-321deca769fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309437786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1309437786
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3753124784
Short name T806
Test name
Test status
Simulation time 455561767 ps
CPU time 0.78 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:45 PM PDT 24
Peak memory 201588 kb
Host smart-937ce521-d4e5-4649-bfd8-9069e1d995e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753124784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3753124784
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1304842246
Short name T893
Test name
Test status
Simulation time 452983159 ps
CPU time 0.83 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201576 kb
Host smart-e02ff5fc-17c7-41f0-b633-a251a3f13959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304842246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1304842246
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1356781515
Short name T854
Test name
Test status
Simulation time 501650959 ps
CPU time 0.9 seconds
Started Mar 24 12:33:41 PM PDT 24
Finished Mar 24 12:33:43 PM PDT 24
Peak memory 201592 kb
Host smart-a7d5b88e-e5af-4044-afee-98ca8da0cc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356781515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1356781515
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1856748113
Short name T868
Test name
Test status
Simulation time 366561796 ps
CPU time 0.87 seconds
Started Mar 24 12:33:35 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201580 kb
Host smart-82d52d43-9fd4-45d1-ae39-85e12618af81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856748113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1856748113
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.22913035
Short name T845
Test name
Test status
Simulation time 491722367 ps
CPU time 0.82 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 201528 kb
Host smart-1d5df5c6-0f44-4439-8ab0-ba35010bee35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.22913035
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1057117984
Short name T807
Test name
Test status
Simulation time 496422411 ps
CPU time 0.89 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:47 PM PDT 24
Peak memory 201596 kb
Host smart-6523a89f-1b87-492b-a7dc-b0f2478968a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057117984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1057117984
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1730071901
Short name T833
Test name
Test status
Simulation time 366542967 ps
CPU time 1.57 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201512 kb
Host smart-568a271f-21fb-4006-a5f5-83f913969454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730071901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1730071901
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.926796208
Short name T889
Test name
Test status
Simulation time 739641926 ps
CPU time 3.26 seconds
Started Mar 24 12:33:06 PM PDT 24
Finished Mar 24 12:33:09 PM PDT 24
Peak memory 201828 kb
Host smart-8ed36085-b914-439a-af46-5a8585e26bbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926796208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.926796208
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.138456029
Short name T904
Test name
Test status
Simulation time 52652822941 ps
CPU time 69.68 seconds
Started Mar 24 12:33:05 PM PDT 24
Finished Mar 24 12:34:15 PM PDT 24
Peak memory 201892 kb
Host smart-1d5b1984-eee2-4ce9-a535-36031dae1a3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138456029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.138456029
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1533722419
Short name T847
Test name
Test status
Simulation time 713828371 ps
CPU time 2.28 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:42 PM PDT 24
Peak memory 201516 kb
Host smart-b3388065-6c84-468a-ae21-d1fa87d86244
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533722419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1533722419
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1621863696
Short name T848
Test name
Test status
Simulation time 534281292 ps
CPU time 2.04 seconds
Started Mar 24 12:33:26 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201688 kb
Host smart-8c5585b7-a304-4d1c-89b8-6e4fe5bae8cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621863696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1621863696
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2010945673
Short name T898
Test name
Test status
Simulation time 559243999 ps
CPU time 1.04 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:13 PM PDT 24
Peak memory 201744 kb
Host smart-c0d32d79-535d-449b-90a4-05b98866c5b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010945673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2010945673
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1040011521
Short name T895
Test name
Test status
Simulation time 438791775 ps
CPU time 0.86 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201744 kb
Host smart-049784ba-7f48-48f6-98e0-628ff6867596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040011521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1040011521
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.311986975
Short name T910
Test name
Test status
Simulation time 2492590822 ps
CPU time 3.57 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201652 kb
Host smart-1c974059-3d79-47c5-927c-72b50a3763a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311986975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.311986975
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.171820337
Short name T830
Test name
Test status
Simulation time 488041396 ps
CPU time 2.4 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 201932 kb
Host smart-3b4901ca-8395-4fad-a40c-d107329c6e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171820337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.171820337
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2271384754
Short name T97
Test name
Test status
Simulation time 8247039745 ps
CPU time 22.33 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:51 PM PDT 24
Peak memory 201936 kb
Host smart-c6d49c09-e21f-4f58-814b-16f87a209a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271384754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2271384754
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2129402708
Short name T803
Test name
Test status
Simulation time 313457578 ps
CPU time 1.33 seconds
Started Mar 24 12:33:40 PM PDT 24
Finished Mar 24 12:33:42 PM PDT 24
Peak memory 201516 kb
Host smart-d26ee858-21fb-48f3-bd3e-f3284688e7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129402708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2129402708
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2619521309
Short name T883
Test name
Test status
Simulation time 499142503 ps
CPU time 0.95 seconds
Started Mar 24 12:33:55 PM PDT 24
Finished Mar 24 12:33:56 PM PDT 24
Peak memory 201636 kb
Host smart-bdd3187d-97ae-454b-bbc7-3ad5791c2939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619521309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2619521309
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1483183834
Short name T839
Test name
Test status
Simulation time 298842148 ps
CPU time 1.39 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 201612 kb
Host smart-0d0bf0d1-0042-40ff-9cab-20131f725fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483183834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1483183834
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1737960739
Short name T821
Test name
Test status
Simulation time 318664130 ps
CPU time 0.81 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201604 kb
Host smart-782b44c1-3c04-4fb1-9b26-e955a237bb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737960739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1737960739
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2490895931
Short name T802
Test name
Test status
Simulation time 543583139 ps
CPU time 0.96 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201596 kb
Host smart-33f8ef56-bef5-4de1-9a0a-ed8906b748eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490895931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2490895931
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3016670503
Short name T909
Test name
Test status
Simulation time 432475237 ps
CPU time 0.86 seconds
Started Mar 24 12:33:56 PM PDT 24
Finished Mar 24 12:33:57 PM PDT 24
Peak memory 201636 kb
Host smart-3facc2f6-ddfb-4b71-9643-3bbc15e89fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016670503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3016670503
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.319405402
Short name T897
Test name
Test status
Simulation time 297992845 ps
CPU time 1.37 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201632 kb
Host smart-a51f5cd1-a873-42a9-8753-4d566dbcc10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319405402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.319405402
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2531233654
Short name T881
Test name
Test status
Simulation time 380929868 ps
CPU time 0.85 seconds
Started Mar 24 12:33:39 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201604 kb
Host smart-98395853-15bd-4533-92fb-55637c96ed45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531233654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2531233654
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.318292737
Short name T913
Test name
Test status
Simulation time 533704520 ps
CPU time 0.72 seconds
Started Mar 24 12:33:38 PM PDT 24
Finished Mar 24 12:33:39 PM PDT 24
Peak memory 201992 kb
Host smart-2c56db89-3ea0-4337-b8af-57395eb1accd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318292737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.318292737
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.447093767
Short name T905
Test name
Test status
Simulation time 447400970 ps
CPU time 1.15 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201568 kb
Host smart-a01c30c9-dc13-4c11-bb37-e46e035cddc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447093767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.447093767
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.110955465
Short name T95
Test name
Test status
Simulation time 552230756 ps
CPU time 1.35 seconds
Started Mar 24 12:33:11 PM PDT 24
Finished Mar 24 12:33:12 PM PDT 24
Peak memory 201656 kb
Host smart-7e57c49e-04a7-418c-bc1f-6409b705b446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110955465 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.110955465
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3203456204
Short name T141
Test name
Test status
Simulation time 414157554 ps
CPU time 0.98 seconds
Started Mar 24 12:33:24 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201632 kb
Host smart-43462556-c488-40d3-8ac7-ec97f244477b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203456204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3203456204
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.178400303
Short name T822
Test name
Test status
Simulation time 309324854 ps
CPU time 0.82 seconds
Started Mar 24 12:33:12 PM PDT 24
Finished Mar 24 12:33:13 PM PDT 24
Peak memory 201732 kb
Host smart-09251482-c45c-4491-989f-1de506349531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178400303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.178400303
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1452897933
Short name T851
Test name
Test status
Simulation time 4948549963 ps
CPU time 6.05 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201876 kb
Host smart-c3d71aab-1c0a-4031-b3e8-8882b0864b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452897933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1452897933
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.513180582
Short name T902
Test name
Test status
Simulation time 882094439 ps
CPU time 2.85 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 201888 kb
Host smart-77e093be-ba7d-4f4b-9074-0622000dc0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513180582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.513180582
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3493580168
Short name T359
Test name
Test status
Simulation time 4868418145 ps
CPU time 11.84 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:41 PM PDT 24
Peak memory 201928 kb
Host smart-d2ab207b-0ecf-45de-9c94-6c25f65bc4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493580168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3493580168
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1636413066
Short name T819
Test name
Test status
Simulation time 566691636 ps
CPU time 0.97 seconds
Started Mar 24 12:33:23 PM PDT 24
Finished Mar 24 12:33:30 PM PDT 24
Peak memory 201664 kb
Host smart-12b0aac8-0e12-4d14-a6f6-7087dfc304f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636413066 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1636413066
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.354309264
Short name T837
Test name
Test status
Simulation time 331625252 ps
CPU time 1.41 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201976 kb
Host smart-6548c963-0da4-4094-8cd8-1ec45a5e39ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354309264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.354309264
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1093951258
Short name T843
Test name
Test status
Simulation time 367647526 ps
CPU time 0.88 seconds
Started Mar 24 12:33:34 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201568 kb
Host smart-7828a770-638d-4c1f-aae4-dc0c0ecb9ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093951258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1093951258
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3767441121
Short name T828
Test name
Test status
Simulation time 2320410961 ps
CPU time 2.64 seconds
Started Mar 24 12:32:59 PM PDT 24
Finished Mar 24 12:33:02 PM PDT 24
Peak memory 201696 kb
Host smart-f071ace2-c9e9-4c9e-bde0-d660c303ac36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767441121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3767441121
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3569958348
Short name T876
Test name
Test status
Simulation time 527595046 ps
CPU time 3.55 seconds
Started Mar 24 12:33:21 PM PDT 24
Finished Mar 24 12:33:25 PM PDT 24
Peak memory 217724 kb
Host smart-eb1be899-a305-4d35-93d7-6d22b75d9ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569958348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3569958348
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.505936933
Short name T831
Test name
Test status
Simulation time 8341491093 ps
CPU time 21.72 seconds
Started Mar 24 12:33:20 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 201896 kb
Host smart-4e276b0a-b94d-487b-8174-c550852e0603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505936933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.505936933
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3289406686
Short name T94
Test name
Test status
Simulation time 350192820 ps
CPU time 1.53 seconds
Started Mar 24 12:33:31 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201644 kb
Host smart-63097548-6a36-4a0c-b4ff-0980f839e93d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289406686 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3289406686
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.827729490
Short name T153
Test name
Test status
Simulation time 496427184 ps
CPU time 1.44 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:35 PM PDT 24
Peak memory 201576 kb
Host smart-57270bbc-b023-4c74-afdc-4d0a0fe94769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827729490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.827729490
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3845315261
Short name T852
Test name
Test status
Simulation time 462813434 ps
CPU time 0.95 seconds
Started Mar 24 12:33:37 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 201532 kb
Host smart-b3388f9f-f853-4270-a468-69994f39b6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845315261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3845315261
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3502719191
Short name T912
Test name
Test status
Simulation time 2310675163 ps
CPU time 5.66 seconds
Started Mar 24 12:33:32 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 202116 kb
Host smart-8c62851a-5f87-4f47-a9c9-fb62a14c8726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502719191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3502719191
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2040675250
Short name T896
Test name
Test status
Simulation time 553797827 ps
CPU time 3.93 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:17 PM PDT 24
Peak memory 217752 kb
Host smart-b31022f2-44ed-4934-a64c-7013718880e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040675250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2040675250
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2572696795
Short name T357
Test name
Test status
Simulation time 8154697513 ps
CPU time 23.22 seconds
Started Mar 24 12:33:25 PM PDT 24
Finished Mar 24 12:33:48 PM PDT 24
Peak memory 201872 kb
Host smart-f06fef97-5a49-48c9-92b9-598dcdafcfab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572696795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2572696795
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4048660387
Short name T842
Test name
Test status
Simulation time 475972941 ps
CPU time 0.94 seconds
Started Mar 24 12:33:43 PM PDT 24
Finished Mar 24 12:33:44 PM PDT 24
Peak memory 201588 kb
Host smart-d1a88e10-8118-4c22-86dd-c732e9fd8ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048660387 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4048660387
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1071762199
Short name T140
Test name
Test status
Simulation time 387241849 ps
CPU time 0.95 seconds
Started Mar 24 12:33:36 PM PDT 24
Finished Mar 24 12:33:38 PM PDT 24
Peak memory 201976 kb
Host smart-ac2bd48f-d83a-4910-ae63-f8e01988d19a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071762199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1071762199
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.283714965
Short name T906
Test name
Test status
Simulation time 523130571 ps
CPU time 1.18 seconds
Started Mar 24 12:33:13 PM PDT 24
Finished Mar 24 12:33:15 PM PDT 24
Peak memory 201612 kb
Host smart-1f5c8a94-ad45-4526-8ad0-acd56acdd153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283714965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.283714965
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3365733897
Short name T858
Test name
Test status
Simulation time 2194201339 ps
CPU time 4.39 seconds
Started Mar 24 12:33:17 PM PDT 24
Finished Mar 24 12:33:22 PM PDT 24
Peak memory 201680 kb
Host smart-ec421b87-f279-4436-9bd1-9c99efb0dd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365733897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3365733897
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.200046807
Short name T93
Test name
Test status
Simulation time 426984234 ps
CPU time 1.66 seconds
Started Mar 24 12:33:29 PM PDT 24
Finished Mar 24 12:33:31 PM PDT 24
Peak memory 201856 kb
Host smart-4ea0ef20-0591-433c-bcd0-15636aa73b03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200046807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.200046807
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2844376940
Short name T870
Test name
Test status
Simulation time 5039149752 ps
CPU time 4.17 seconds
Started Mar 24 12:33:28 PM PDT 24
Finished Mar 24 12:33:33 PM PDT 24
Peak memory 201840 kb
Host smart-5de92bb0-3363-4519-9585-141f9ecc6d39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844376940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2844376940
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.67316648
Short name T91
Test name
Test status
Simulation time 599371090 ps
CPU time 1.17 seconds
Started Mar 24 12:33:22 PM PDT 24
Finished Mar 24 12:33:23 PM PDT 24
Peak memory 201664 kb
Host smart-00392204-1d8b-43ff-9110-edee061e8036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67316648 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.67316648
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1914043418
Short name T74
Test name
Test status
Simulation time 450695136 ps
CPU time 1.79 seconds
Started Mar 24 12:33:30 PM PDT 24
Finished Mar 24 12:33:32 PM PDT 24
Peak memory 201540 kb
Host smart-12b344cb-3941-4325-af4d-d2eab9e237a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914043418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1914043418
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1927932813
Short name T801
Test name
Test status
Simulation time 296599923 ps
CPU time 1.28 seconds
Started Mar 24 12:33:27 PM PDT 24
Finished Mar 24 12:33:29 PM PDT 24
Peak memory 201616 kb
Host smart-d9dd8620-b9f8-4fa2-9730-48f2a4d062db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927932813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1927932813
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4238416724
Short name T152
Test name
Test status
Simulation time 2528226756 ps
CPU time 2.47 seconds
Started Mar 24 12:33:32 PM PDT 24
Finished Mar 24 12:33:34 PM PDT 24
Peak memory 201740 kb
Host smart-62698d43-fe9b-4c64-9877-e7408e3fd5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238416724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4238416724
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2392108130
Short name T836
Test name
Test status
Simulation time 782909407 ps
CPU time 2.35 seconds
Started Mar 24 12:33:33 PM PDT 24
Finished Mar 24 12:33:36 PM PDT 24
Peak memory 201900 kb
Host smart-0c6fecb1-34e7-43b0-8207-babb85c79b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392108130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2392108130
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.324571930
Short name T877
Test name
Test status
Simulation time 4668275032 ps
CPU time 12.22 seconds
Started Mar 24 12:33:15 PM PDT 24
Finished Mar 24 12:33:28 PM PDT 24
Peak memory 201856 kb
Host smart-beef274c-c65f-4eb4-898a-473be44eea3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324571930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.324571930
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2079599791
Short name T494
Test name
Test status
Simulation time 495768812 ps
CPU time 0.92 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 201544 kb
Host smart-06db129e-19be-4d55-aaa6-da73565cf98d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079599791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2079599791
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1419772367
Short name T710
Test name
Test status
Simulation time 502135695589 ps
CPU time 844.68 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 01:04:18 PM PDT 24
Peak memory 201828 kb
Host smart-0611566d-bfd7-40dc-9cba-3008e5669f1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419772367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1419772367
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.82864184
Short name T163
Test name
Test status
Simulation time 499964128208 ps
CPU time 1186.48 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 01:10:06 PM PDT 24
Peak memory 201820 kb
Host smart-96339dcd-59a8-4900-aea8-f8a13944bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82864184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.82864184
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3693893810
Short name T333
Test name
Test status
Simulation time 164760068027 ps
CPU time 100.68 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:51:55 PM PDT 24
Peak memory 201776 kb
Host smart-56862a7b-28db-4f4c-ba6e-d82d16adc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693893810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3693893810
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2962216211
Short name T578
Test name
Test status
Simulation time 164459484940 ps
CPU time 113.54 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:52:08 PM PDT 24
Peak memory 201716 kb
Host smart-034a1361-4111-48bf-8a04-44042475d287
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962216211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2962216211
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2525181231
Short name T432
Test name
Test status
Simulation time 160830315851 ps
CPU time 178.66 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:53:21 PM PDT 24
Peak memory 201812 kb
Host smart-a87b04fc-a2bc-41bb-aa1f-4765e8f6bb68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525181231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2525181231
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2973062612
Short name T798
Test name
Test status
Simulation time 355453344012 ps
CPU time 218.05 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:53:51 PM PDT 24
Peak memory 201772 kb
Host smart-349e3201-63a8-4ede-ab53-e375f474bbd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973062612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2973062612
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3048210976
Short name T111
Test name
Test status
Simulation time 580582411301 ps
CPU time 370.95 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:56:26 PM PDT 24
Peak memory 201944 kb
Host smart-7d397a81-551f-4f6b-9ad2-f63d5a40b2f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048210976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3048210976
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1233378285
Short name T592
Test name
Test status
Simulation time 128749681067 ps
CPU time 707.68 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 01:02:09 PM PDT 24
Peak memory 202168 kb
Host smart-7ca47842-46c1-402d-8bf6-1a14fa107256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233378285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1233378285
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3229249473
Short name T558
Test name
Test status
Simulation time 24501236010 ps
CPU time 9.95 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:50:25 PM PDT 24
Peak memory 201644 kb
Host smart-736f5f67-d9fd-4b90-be37-14658b7ac2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229249473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3229249473
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1110654549
Short name T376
Test name
Test status
Simulation time 3940901574 ps
CPU time 4.63 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 201472 kb
Host smart-243f6805-e8b3-471c-88b3-fec36ce74064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110654549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1110654549
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2499443114
Short name T123
Test name
Test status
Simulation time 5893527459 ps
CPU time 4.21 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:24 PM PDT 24
Peak memory 201580 kb
Host smart-0ccd5e48-348b-4f17-80ae-4ccc651d4465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499443114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2499443114
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2574372298
Short name T261
Test name
Test status
Simulation time 332115504604 ps
CPU time 800.77 seconds
Started Mar 24 12:50:16 PM PDT 24
Finished Mar 24 01:03:38 PM PDT 24
Peak memory 202116 kb
Host smart-24fafd37-7fe7-44ea-8108-eed8e47446b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574372298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2574372298
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.308364641
Short name T46
Test name
Test status
Simulation time 37037988754 ps
CPU time 28.41 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 210256 kb
Host smart-c5bf7092-56ae-4588-8cb8-f7d1280415ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308364641 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.308364641
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2702533958
Short name T671
Test name
Test status
Simulation time 353450216 ps
CPU time 1.47 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:50:19 PM PDT 24
Peak memory 201788 kb
Host smart-4460704f-f16b-45e3-9912-abead1f91d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702533958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2702533958
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1351634149
Short name T201
Test name
Test status
Simulation time 327585342774 ps
CPU time 88.2 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:51:43 PM PDT 24
Peak memory 201892 kb
Host smart-1cf0f605-5365-4a6a-aa32-a3612c6c1045
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351634149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1351634149
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3575789730
Short name T238
Test name
Test status
Simulation time 159762599161 ps
CPU time 285.77 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:55:10 PM PDT 24
Peak memory 201764 kb
Host smart-91c2a4d5-3169-4c1d-b101-7b5780ea9efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575789730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3575789730
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1406810484
Short name T265
Test name
Test status
Simulation time 330623578235 ps
CPU time 373.06 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:56:37 PM PDT 24
Peak memory 201800 kb
Host smart-d227698f-65b2-4960-89ce-1a087086f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406810484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1406810484
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3188114458
Short name T517
Test name
Test status
Simulation time 158925987696 ps
CPU time 376.93 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:56:32 PM PDT 24
Peak memory 201912 kb
Host smart-ef2ea50f-470d-4899-bce9-6e6650edeee0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188114458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3188114458
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1357274873
Short name T105
Test name
Test status
Simulation time 164608705359 ps
CPU time 400.49 seconds
Started Mar 24 12:50:12 PM PDT 24
Finished Mar 24 12:56:53 PM PDT 24
Peak memory 201848 kb
Host smart-593f041d-93a8-43b0-b5fc-abfd2288f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357274873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1357274873
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1044522254
Short name T620
Test name
Test status
Simulation time 164822884582 ps
CPU time 386.4 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:56:53 PM PDT 24
Peak memory 201880 kb
Host smart-7f025af6-6e04-4c31-8eba-f3d29e9fc56d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044522254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1044522254
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1674067775
Short name T459
Test name
Test status
Simulation time 199292614207 ps
CPU time 319.46 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:55:47 PM PDT 24
Peak memory 201928 kb
Host smart-532e9d15-a007-4cc8-a3fa-888f19a3cffb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674067775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1674067775
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2829659088
Short name T503
Test name
Test status
Simulation time 201278241888 ps
CPU time 120.14 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:52:22 PM PDT 24
Peak memory 201688 kb
Host smart-48c469c7-b1a3-4b6f-a450-05e09124d1cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829659088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2829659088
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1386868984
Short name T361
Test name
Test status
Simulation time 75101647396 ps
CPU time 431.25 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 202184 kb
Host smart-717ce35e-f013-4dc1-a105-9fa5f49c279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386868984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1386868984
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.324060727
Short name T565
Test name
Test status
Simulation time 45624424025 ps
CPU time 26.93 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 201640 kb
Host smart-5406b612-14c3-46f8-8f1b-fbb52eab68d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324060727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.324060727
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1460841060
Short name T597
Test name
Test status
Simulation time 5206451988 ps
CPU time 6.42 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:32 PM PDT 24
Peak memory 201636 kb
Host smart-23d74f48-d58f-4510-b3b1-286031ba0eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460841060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1460841060
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.681179111
Short name T99
Test name
Test status
Simulation time 4029613164 ps
CPU time 9.7 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 217352 kb
Host smart-e43fe3f6-160c-4833-b39b-5b8775843cf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681179111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.681179111
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1239929380
Short name T426
Test name
Test status
Simulation time 5937084337 ps
CPU time 13.42 seconds
Started Mar 24 12:50:19 PM PDT 24
Finished Mar 24 12:50:33 PM PDT 24
Peak memory 201632 kb
Host smart-b899ad7b-8d57-4b5e-ae3f-2bc86afe2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239929380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1239929380
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3829572470
Short name T248
Test name
Test status
Simulation time 388129522928 ps
CPU time 918.81 seconds
Started Mar 24 12:50:16 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 202104 kb
Host smart-248efb70-b9c1-452d-8af1-6ad7f39655e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829572470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3829572470
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2046007144
Short name T299
Test name
Test status
Simulation time 280483248974 ps
CPU time 156.6 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:52:50 PM PDT 24
Peak memory 210084 kb
Host smart-98e95690-c9d2-4c09-9117-d3109f2fe01c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046007144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2046007144
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.673205259
Short name T484
Test name
Test status
Simulation time 522607288 ps
CPU time 1.91 seconds
Started Mar 24 12:50:39 PM PDT 24
Finished Mar 24 12:50:41 PM PDT 24
Peak memory 201532 kb
Host smart-89d95abd-51d3-4929-a50f-e34083c9514b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673205259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.673205259
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2125975133
Short name T260
Test name
Test status
Simulation time 191346643106 ps
CPU time 435.19 seconds
Started Mar 24 12:50:36 PM PDT 24
Finished Mar 24 12:57:56 PM PDT 24
Peak memory 201912 kb
Host smart-0f081b55-4591-4852-a702-c91f461dfa83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125975133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2125975133
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3920141174
Short name T718
Test name
Test status
Simulation time 203177341264 ps
CPU time 41 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:51:16 PM PDT 24
Peak memory 201832 kb
Host smart-e0714112-7e58-40e2-88d9-1fa36c1b5bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920141174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3920141174
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3844286618
Short name T605
Test name
Test status
Simulation time 163972930287 ps
CPU time 403.07 seconds
Started Mar 24 12:50:33 PM PDT 24
Finished Mar 24 12:57:16 PM PDT 24
Peak memory 201840 kb
Host smart-d8601a33-d390-4ea8-9d3a-ebbe94fc27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844286618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3844286618
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2727803324
Short name T640
Test name
Test status
Simulation time 490373689325 ps
CPU time 613.85 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 01:00:50 PM PDT 24
Peak memory 201896 kb
Host smart-0427b05b-5923-490e-ac06-e95fac39a380
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727803324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2727803324
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1330358061
Short name T748
Test name
Test status
Simulation time 331888837419 ps
CPU time 291.63 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:55:27 PM PDT 24
Peak memory 201848 kb
Host smart-71a778c4-df25-4987-9937-ec52df0a248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330358061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1330358061
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1074658563
Short name T749
Test name
Test status
Simulation time 330500325504 ps
CPU time 202.42 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:53:58 PM PDT 24
Peak memory 201936 kb
Host smart-40e8a608-b6b8-4859-a307-04cacbf171bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074658563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1074658563
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.978651806
Short name T746
Test name
Test status
Simulation time 593548992680 ps
CPU time 1422.31 seconds
Started Mar 24 12:50:40 PM PDT 24
Finished Mar 24 01:14:23 PM PDT 24
Peak memory 201864 kb
Host smart-74f32d46-86c8-40c1-badb-b3c3998e2af5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978651806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.978651806
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2883861501
Short name T39
Test name
Test status
Simulation time 134871620057 ps
CPU time 490.98 seconds
Started Mar 24 12:50:40 PM PDT 24
Finished Mar 24 12:58:52 PM PDT 24
Peak memory 202188 kb
Host smart-90668ac6-1ef4-41f0-8665-76a94b2f21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883861501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2883861501
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3388694431
Short name T788
Test name
Test status
Simulation time 22664633528 ps
CPU time 26.88 seconds
Started Mar 24 12:50:34 PM PDT 24
Finished Mar 24 12:51:01 PM PDT 24
Peak memory 201540 kb
Host smart-de262b44-5d4e-4f42-8124-83346d32d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388694431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3388694431
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3246464690
Short name T191
Test name
Test status
Simulation time 4724112518 ps
CPU time 11.09 seconds
Started Mar 24 12:50:37 PM PDT 24
Finished Mar 24 12:50:48 PM PDT 24
Peak memory 201608 kb
Host smart-10b54461-6285-42f1-9705-8bcb02129cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246464690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3246464690
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3881304095
Short name T504
Test name
Test status
Simulation time 5968394487 ps
CPU time 3.06 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:50:38 PM PDT 24
Peak memory 201640 kb
Host smart-0b7cef9c-443f-46c1-b95a-3d62369d518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881304095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3881304095
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2962447377
Short name T736
Test name
Test status
Simulation time 19985566030 ps
CPU time 44.59 seconds
Started Mar 24 12:50:35 PM PDT 24
Finished Mar 24 12:51:20 PM PDT 24
Peak memory 210220 kb
Host smart-0e26ed67-b419-4297-a275-62b82585d7fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962447377 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2962447377
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1121654039
Short name T25
Test name
Test status
Simulation time 421181661 ps
CPU time 0.86 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:50:42 PM PDT 24
Peak memory 201500 kb
Host smart-e70793ee-7344-4702-a24d-c89e4d8195cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121654039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1121654039
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.971737533
Short name T188
Test name
Test status
Simulation time 354027930824 ps
CPU time 79.37 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:52:02 PM PDT 24
Peak memory 201888 kb
Host smart-dcff1551-bce9-4345-a46c-9a469ef0ef21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971737533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.971737533
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.922689461
Short name T271
Test name
Test status
Simulation time 507907937010 ps
CPU time 143.17 seconds
Started Mar 24 12:50:39 PM PDT 24
Finished Mar 24 12:53:02 PM PDT 24
Peak memory 201948 kb
Host smart-46afe2ac-ee10-4892-978e-0c6bd6758fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922689461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.922689461
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2224525048
Short name T268
Test name
Test status
Simulation time 171523965475 ps
CPU time 109.13 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:52:31 PM PDT 24
Peak memory 201896 kb
Host smart-5549f3b0-0b38-4cd9-b6bb-18b5eedce091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224525048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2224525048
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1626045253
Short name T564
Test name
Test status
Simulation time 160621705661 ps
CPU time 24.94 seconds
Started Mar 24 12:50:37 PM PDT 24
Finished Mar 24 12:51:02 PM PDT 24
Peak memory 201868 kb
Host smart-f20e34cd-c86d-4281-b19e-f5352c039b13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626045253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1626045253
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.649119685
Short name T679
Test name
Test status
Simulation time 494395531088 ps
CPU time 599.01 seconds
Started Mar 24 12:50:42 PM PDT 24
Finished Mar 24 01:00:42 PM PDT 24
Peak memory 201816 kb
Host smart-3d647c22-ff48-42cb-8b30-dc697b5678c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649119685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.649119685
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.849413995
Short name T428
Test name
Test status
Simulation time 482394993515 ps
CPU time 282.43 seconds
Started Mar 24 12:50:39 PM PDT 24
Finished Mar 24 12:55:21 PM PDT 24
Peak memory 201820 kb
Host smart-1403d7a6-01a2-4ef1-9b47-2179f2532570
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=849413995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.849413995
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2488328425
Short name T702
Test name
Test status
Simulation time 183143313918 ps
CPU time 106.08 seconds
Started Mar 24 12:50:38 PM PDT 24
Finished Mar 24 12:52:25 PM PDT 24
Peak memory 201944 kb
Host smart-9d9e00ec-b58c-4cb8-81d4-eee9d5f48361
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488328425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2488328425
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1354503038
Short name T465
Test name
Test status
Simulation time 618607342024 ps
CPU time 148.33 seconds
Started Mar 24 12:50:40 PM PDT 24
Finished Mar 24 12:53:09 PM PDT 24
Peak memory 201836 kb
Host smart-c83d3cad-ae2f-42be-a22f-65380ed0e1ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354503038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1354503038
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3833221712
Short name T218
Test name
Test status
Simulation time 134736237956 ps
CPU time 472.67 seconds
Started Mar 24 12:50:47 PM PDT 24
Finished Mar 24 12:58:40 PM PDT 24
Peak memory 202216 kb
Host smart-e66b0456-3939-4a1e-bbe3-904c1ffb3305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833221712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3833221712
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.387668888
Short name T391
Test name
Test status
Simulation time 42262441860 ps
CPU time 96.84 seconds
Started Mar 24 12:50:37 PM PDT 24
Finished Mar 24 12:52:14 PM PDT 24
Peak memory 201632 kb
Host smart-665d151d-ef35-47b7-a6fa-ab062e95861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387668888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.387668888
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1587475628
Short name T657
Test name
Test status
Simulation time 5149200508 ps
CPU time 12.24 seconds
Started Mar 24 12:50:42 PM PDT 24
Finished Mar 24 12:50:56 PM PDT 24
Peak memory 201620 kb
Host smart-82c59ba0-2ad7-4c75-90de-222dbbe8fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587475628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1587475628
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2529081391
Short name T103
Test name
Test status
Simulation time 5850927936 ps
CPU time 7.98 seconds
Started Mar 24 12:50:40 PM PDT 24
Finished Mar 24 12:50:49 PM PDT 24
Peak memory 201688 kb
Host smart-5f1188e1-51b8-4d2d-82f9-e04383ad1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529081391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2529081391
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3118292119
Short name T230
Test name
Test status
Simulation time 341722854230 ps
CPU time 162.05 seconds
Started Mar 24 12:50:39 PM PDT 24
Finished Mar 24 12:53:21 PM PDT 24
Peak memory 201832 kb
Host smart-6eed7673-cbc7-405e-9390-51ba2cf9e02d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118292119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3118292119
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1682011462
Short name T160
Test name
Test status
Simulation time 231757477093 ps
CPU time 232.84 seconds
Started Mar 24 12:50:50 PM PDT 24
Finished Mar 24 12:54:43 PM PDT 24
Peak memory 210168 kb
Host smart-d5f61f73-7f24-411a-9c33-630e26424500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682011462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1682011462
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3087240393
Short name T754
Test name
Test status
Simulation time 512099009 ps
CPU time 1.75 seconds
Started Mar 24 12:50:44 PM PDT 24
Finished Mar 24 12:50:46 PM PDT 24
Peak memory 201568 kb
Host smart-13189f9d-bb47-49f4-a08a-53dff7b25200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087240393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3087240393
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3160045433
Short name T291
Test name
Test status
Simulation time 491503116058 ps
CPU time 316.7 seconds
Started Mar 24 12:50:42 PM PDT 24
Finished Mar 24 12:56:00 PM PDT 24
Peak memory 201848 kb
Host smart-13d13b5f-393f-44db-9753-1c5816628e21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160045433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3160045433
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2990734029
Short name T482
Test name
Test status
Simulation time 162691058748 ps
CPU time 333.84 seconds
Started Mar 24 12:50:38 PM PDT 24
Finished Mar 24 12:56:12 PM PDT 24
Peak memory 201772 kb
Host smart-ff904666-4fcd-4aba-8af8-c556a22bf262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990734029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2990734029
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.148425928
Short name T569
Test name
Test status
Simulation time 485392431618 ps
CPU time 1206.52 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 01:10:49 PM PDT 24
Peak memory 201884 kb
Host smart-af50811b-3a62-4ca4-a753-91f1e6276b79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=148425928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.148425928
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.359054598
Short name T320
Test name
Test status
Simulation time 331098519811 ps
CPU time 178.68 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:53:41 PM PDT 24
Peak memory 201856 kb
Host smart-226e224c-0e0a-41d7-b78d-2b345c826ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359054598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.359054598
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1074657259
Short name T184
Test name
Test status
Simulation time 168681987165 ps
CPU time 193.35 seconds
Started Mar 24 12:50:38 PM PDT 24
Finished Mar 24 12:53:51 PM PDT 24
Peak memory 201820 kb
Host smart-d97f0715-b6da-44d9-b6b7-d61b6247fa93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074657259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1074657259
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.591602685
Short name T612
Test name
Test status
Simulation time 480208288504 ps
CPU time 203.62 seconds
Started Mar 24 12:50:38 PM PDT 24
Finished Mar 24 12:54:02 PM PDT 24
Peak memory 201852 kb
Host smart-e9ee8dce-b9ab-4fc5-b7cb-71852ef1e66f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591602685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.591602685
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3425233885
Short name T451
Test name
Test status
Simulation time 410679252858 ps
CPU time 456.61 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:58:19 PM PDT 24
Peak memory 201924 kb
Host smart-5c573d4d-ecc0-4b67-b494-316530894482
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425233885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3425233885
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3842291329
Short name T654
Test name
Test status
Simulation time 44671555589 ps
CPU time 24.78 seconds
Started Mar 24 12:50:43 PM PDT 24
Finished Mar 24 12:51:09 PM PDT 24
Peak memory 201632 kb
Host smart-7409eb7e-73b9-44a5-918e-11fbc835b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842291329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3842291329
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3482526555
Short name T602
Test name
Test status
Simulation time 3456989961 ps
CPU time 8.63 seconds
Started Mar 24 12:50:41 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 201612 kb
Host smart-ef24a69f-f5fb-4cf1-87ea-da946eb0468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482526555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3482526555
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2969957676
Short name T419
Test name
Test status
Simulation time 5705996966 ps
CPU time 14.04 seconds
Started Mar 24 12:50:38 PM PDT 24
Finished Mar 24 12:50:53 PM PDT 24
Peak memory 201652 kb
Host smart-a19e4a25-87b2-4f3c-be7e-9682d1cc6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969957676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2969957676
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.4067702432
Short name T752
Test name
Test status
Simulation time 12278168147 ps
CPU time 31.65 seconds
Started Mar 24 12:50:46 PM PDT 24
Finished Mar 24 12:51:18 PM PDT 24
Peak memory 201684 kb
Host smart-106bd4b1-e8b1-4b1e-9af3-ccb4695b8e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067702432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.4067702432
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2619080483
Short name T648
Test name
Test status
Simulation time 330768564326 ps
CPU time 407.3 seconds
Started Mar 24 12:50:45 PM PDT 24
Finished Mar 24 12:57:32 PM PDT 24
Peak memory 201892 kb
Host smart-b5cc273f-cd09-4161-b2ef-fdcfd1fe007c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619080483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2619080483
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2162047359
Short name T526
Test name
Test status
Simulation time 339593975870 ps
CPU time 865.26 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 201832 kb
Host smart-5ac1c7b9-748d-4e95-a6f7-bd78895024dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162047359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2162047359
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.544653011
Short name T543
Test name
Test status
Simulation time 167916316025 ps
CPU time 200.41 seconds
Started Mar 24 12:50:42 PM PDT 24
Finished Mar 24 12:54:03 PM PDT 24
Peak memory 201928 kb
Host smart-c07639a1-5e41-44e5-809d-67bb11aec715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544653011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.544653011
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.52212624
Short name T546
Test name
Test status
Simulation time 495209631977 ps
CPU time 990.34 seconds
Started Mar 24 12:50:45 PM PDT 24
Finished Mar 24 01:07:17 PM PDT 24
Peak memory 201824 kb
Host smart-e00ab7a7-b0e0-466e-89a6-1974cd22533f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=52212624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt
_fixed.52212624
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2349503649
Short name T266
Test name
Test status
Simulation time 325808116245 ps
CPU time 372.2 seconds
Started Mar 24 12:50:45 PM PDT 24
Finished Mar 24 12:56:58 PM PDT 24
Peak memory 201840 kb
Host smart-4223f2cb-b9ae-476c-a7bb-d63b7bb8664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349503649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2349503649
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3574849267
Short name T530
Test name
Test status
Simulation time 166694012709 ps
CPU time 385.59 seconds
Started Mar 24 12:50:43 PM PDT 24
Finished Mar 24 12:57:09 PM PDT 24
Peak memory 201796 kb
Host smart-388c3ced-350e-4c65-8b2f-669285f5aaef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574849267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3574849267
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3398266744
Short name T554
Test name
Test status
Simulation time 371890519778 ps
CPU time 819.27 seconds
Started Mar 24 12:50:42 PM PDT 24
Finished Mar 24 01:04:22 PM PDT 24
Peak memory 201880 kb
Host smart-3166a95a-419b-4537-97e8-ccce0ea0267c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398266744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3398266744
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3414374952
Short name T113
Test name
Test status
Simulation time 396763946201 ps
CPU time 246.95 seconds
Started Mar 24 12:50:51 PM PDT 24
Finished Mar 24 12:54:58 PM PDT 24
Peak memory 201928 kb
Host smart-e7d8a959-ebd5-431e-a691-46e66ff82c52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414374952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3414374952
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4026399720
Short name T59
Test name
Test status
Simulation time 123793140799 ps
CPU time 427.49 seconds
Started Mar 24 12:50:44 PM PDT 24
Finished Mar 24 12:57:52 PM PDT 24
Peak memory 202084 kb
Host smart-5b3e0c48-8470-4881-84f3-5d9aea3391fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026399720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4026399720
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1048561954
Short name T705
Test name
Test status
Simulation time 28359292645 ps
CPU time 12.94 seconds
Started Mar 24 12:50:44 PM PDT 24
Finished Mar 24 12:50:57 PM PDT 24
Peak memory 201612 kb
Host smart-28065d5e-dd18-48ed-a78d-59823e7db133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048561954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1048561954
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1727306979
Short name T559
Test name
Test status
Simulation time 4469595592 ps
CPU time 3.29 seconds
Started Mar 24 12:50:48 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 201632 kb
Host smart-1b8554fe-f99e-4ca0-a572-1cab533b08b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727306979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1727306979
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.118328040
Short name T423
Test name
Test status
Simulation time 5717826155 ps
CPU time 15.39 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:51:05 PM PDT 24
Peak memory 201520 kb
Host smart-cc38311b-1d3c-454e-bc68-8d5b052139c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118328040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.118328040
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3079245934
Short name T345
Test name
Test status
Simulation time 328706642539 ps
CPU time 792.23 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 01:04:01 PM PDT 24
Peak memory 201908 kb
Host smart-a809d55d-943f-40c1-9995-d7f5455230c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079245934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3079245934
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1276666560
Short name T124
Test name
Test status
Simulation time 100819782836 ps
CPU time 74.04 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:52:03 PM PDT 24
Peak memory 216796 kb
Host smart-f1253c6b-5669-475e-84c0-734be8c9195e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276666560 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1276666560
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4080771217
Short name T615
Test name
Test status
Simulation time 571584513 ps
CPU time 0.71 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:50:56 PM PDT 24
Peak memory 201572 kb
Host smart-7aa04c11-130e-44a5-94f8-128a2d3325cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080771217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4080771217
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.807091193
Short name T209
Test name
Test status
Simulation time 383505579231 ps
CPU time 227.86 seconds
Started Mar 24 12:50:55 PM PDT 24
Finished Mar 24 12:54:43 PM PDT 24
Peak memory 201928 kb
Host smart-dd5e115b-333d-47af-be99-40281180e791
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807091193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.807091193
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3631189415
Short name T245
Test name
Test status
Simulation time 342257098728 ps
CPU time 200.24 seconds
Started Mar 24 12:50:48 PM PDT 24
Finished Mar 24 12:54:09 PM PDT 24
Peak memory 201792 kb
Host smart-dbb8e971-404f-4bad-9c66-e9819dabfe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631189415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3631189415
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1679618859
Short name T452
Test name
Test status
Simulation time 331291152662 ps
CPU time 726.74 seconds
Started Mar 24 12:50:54 PM PDT 24
Finished Mar 24 01:03:01 PM PDT 24
Peak memory 201916 kb
Host smart-89606a05-1a90-450d-9051-8b1a405cd3f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679618859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1679618859
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1742724816
Short name T214
Test name
Test status
Simulation time 333824521331 ps
CPU time 190.76 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:54:00 PM PDT 24
Peak memory 201840 kb
Host smart-a814330a-4e3a-47f1-b344-ad2800773257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742724816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1742724816
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2073319404
Short name T638
Test name
Test status
Simulation time 494474405613 ps
CPU time 263.08 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:55:13 PM PDT 24
Peak memory 201740 kb
Host smart-dc560a8b-9121-461c-8f9b-902ebe9632aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073319404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2073319404
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.892212323
Short name T253
Test name
Test status
Simulation time 340213578101 ps
CPU time 198.9 seconds
Started Mar 24 12:50:53 PM PDT 24
Finished Mar 24 12:54:12 PM PDT 24
Peak memory 201928 kb
Host smart-ecf9051e-d089-49a8-8995-33695dafa53b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892212323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.892212323
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3956263079
Short name T723
Test name
Test status
Simulation time 413663913929 ps
CPU time 1018.98 seconds
Started Mar 24 12:50:54 PM PDT 24
Finished Mar 24 01:07:53 PM PDT 24
Peak memory 201856 kb
Host smart-97d16744-8cf9-4d0c-be88-276a925ed6ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956263079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3956263079
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3108777032
Short name T386
Test name
Test status
Simulation time 66177738642 ps
CPU time 353.85 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:56:50 PM PDT 24
Peak memory 202128 kb
Host smart-ec8eb62a-8bf3-444c-ae04-d2f0f99c1589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108777032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3108777032
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2804401023
Short name T733
Test name
Test status
Simulation time 34309747001 ps
CPU time 77.33 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:52:20 PM PDT 24
Peak memory 201612 kb
Host smart-ca4acb57-bb00-49ca-b6c9-be35c5aeed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804401023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2804401023
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.572156228
Short name T399
Test name
Test status
Simulation time 3542297514 ps
CPU time 2.41 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:50:59 PM PDT 24
Peak memory 201608 kb
Host smart-05e9ad07-119b-43b8-a6cf-0cc260951a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572156228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.572156228
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2054801708
Short name T600
Test name
Test status
Simulation time 5929596465 ps
CPU time 8.45 seconds
Started Mar 24 12:50:49 PM PDT 24
Finished Mar 24 12:50:58 PM PDT 24
Peak memory 201652 kb
Host smart-0882b82c-c8e2-49b9-a8f4-992975ce7ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054801708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2054801708
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2691554430
Short name T589
Test name
Test status
Simulation time 168347766181 ps
CPU time 731.4 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 01:03:11 PM PDT 24
Peak memory 210432 kb
Host smart-6e9afffa-c316-436f-948b-b53b60d48c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691554430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2691554430
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.156399193
Short name T275
Test name
Test status
Simulation time 496511468750 ps
CPU time 116.9 seconds
Started Mar 24 12:50:58 PM PDT 24
Finished Mar 24 12:52:55 PM PDT 24
Peak memory 210076 kb
Host smart-8637bb2d-6a36-4643-8309-a1eb77389857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156399193 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.156399193
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.173219340
Short name T614
Test name
Test status
Simulation time 402378451 ps
CPU time 1.51 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:51:02 PM PDT 24
Peak memory 201544 kb
Host smart-202d05c6-205a-457e-a5d0-031ad5ada465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173219340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.173219340
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3208308416
Short name T315
Test name
Test status
Simulation time 536180772623 ps
CPU time 968.07 seconds
Started Mar 24 12:50:59 PM PDT 24
Finished Mar 24 01:07:07 PM PDT 24
Peak memory 201764 kb
Host smart-a634d6da-5869-4a76-bad1-993e55e84cf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208308416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3208308416
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1892654126
Short name T240
Test name
Test status
Simulation time 333419229873 ps
CPU time 802.87 seconds
Started Mar 24 12:50:55 PM PDT 24
Finished Mar 24 01:04:18 PM PDT 24
Peak memory 201872 kb
Host smart-5ea322d0-40c5-4102-99e3-40f45b3a9891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892654126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1892654126
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3258252936
Short name T292
Test name
Test status
Simulation time 163021186189 ps
CPU time 378.59 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:57:21 PM PDT 24
Peak memory 201944 kb
Host smart-b081b1a0-ba86-4352-9321-c2f4f7b9ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258252936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3258252936
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1204969505
Short name T365
Test name
Test status
Simulation time 487085019565 ps
CPU time 300.25 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:56:01 PM PDT 24
Peak memory 201688 kb
Host smart-9c8dae84-3050-404b-8ae2-77ddf8c4014b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204969505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1204969505
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4157546826
Short name T566
Test name
Test status
Simulation time 160050937614 ps
CPU time 54.15 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:51:51 PM PDT 24
Peak memory 201820 kb
Host smart-af26adf4-af2b-4d08-956b-d5fd972ca944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157546826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4157546826
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2917261269
Short name T541
Test name
Test status
Simulation time 155838243931 ps
CPU time 167.6 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:53:50 PM PDT 24
Peak memory 201836 kb
Host smart-8cc2962a-436e-484d-a232-c9a08b84319b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917261269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2917261269
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3445889144
Short name T242
Test name
Test status
Simulation time 412870051091 ps
CPU time 1014.07 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 01:07:55 PM PDT 24
Peak memory 201844 kb
Host smart-dce9b164-7957-4f79-a83c-c57349a93b0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445889144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3445889144
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.328055653
Short name T556
Test name
Test status
Simulation time 401286877055 ps
CPU time 237.47 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:55:00 PM PDT 24
Peak memory 201924 kb
Host smart-96ac8bc3-9edf-4c00-a609-6c65de844a01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328055653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.328055653
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1010206382
Short name T227
Test name
Test status
Simulation time 123040755530 ps
CPU time 578.67 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 01:00:41 PM PDT 24
Peak memory 202032 kb
Host smart-d9de639d-40c6-4fd0-8e69-122db10302a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010206382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1010206382
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.130573822
Short name T625
Test name
Test status
Simulation time 40151569094 ps
CPU time 92.05 seconds
Started Mar 24 12:50:57 PM PDT 24
Finished Mar 24 12:52:29 PM PDT 24
Peak memory 201876 kb
Host smart-077a2ffa-e8b9-4288-9562-fb32a2e9d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130573822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.130573822
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.64178418
Short name T366
Test name
Test status
Simulation time 3743831639 ps
CPU time 10.22 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:51:10 PM PDT 24
Peak memory 201592 kb
Host smart-83a379f5-2ab3-4ce8-8a2b-e030ad97ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64178418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.64178418
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2465069711
Short name T475
Test name
Test status
Simulation time 5637171239 ps
CPU time 13.44 seconds
Started Mar 24 12:50:55 PM PDT 24
Finished Mar 24 12:51:08 PM PDT 24
Peak memory 201660 kb
Host smart-02bac05b-aaa3-4620-94c6-0e704435d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465069711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2465069711
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.197908754
Short name T21
Test name
Test status
Simulation time 258346247829 ps
CPU time 229.32 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 12:54:51 PM PDT 24
Peak memory 210412 kb
Host smart-4749b42c-136e-4741-8c1e-b8cae016bc63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197908754 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.197908754
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.274657352
Short name T23
Test name
Test status
Simulation time 339688946 ps
CPU time 1.37 seconds
Started Mar 24 12:51:04 PM PDT 24
Finished Mar 24 12:51:06 PM PDT 24
Peak memory 201476 kb
Host smart-9570743c-e326-4b1d-971b-d6c50f7953ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274657352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.274657352
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1480678856
Short name T119
Test name
Test status
Simulation time 512410604929 ps
CPU time 179.99 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 12:54:01 PM PDT 24
Peak memory 201788 kb
Host smart-5fd08c96-1311-43c1-aa57-f8add4d6a8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480678856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1480678856
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3887980381
Short name T542
Test name
Test status
Simulation time 489370452971 ps
CPU time 279 seconds
Started Mar 24 12:50:58 PM PDT 24
Finished Mar 24 12:55:37 PM PDT 24
Peak memory 202100 kb
Host smart-630b4daf-ade9-4c35-a216-1ac639492451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887980381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3887980381
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1246729516
Short name T662
Test name
Test status
Simulation time 501175970597 ps
CPU time 1195.76 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 01:10:56 PM PDT 24
Peak memory 201800 kb
Host smart-f49d4f2d-bef7-4bf3-9bbc-32673c2a97b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246729516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1246729516
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2596671262
Short name T764
Test name
Test status
Simulation time 485839909041 ps
CPU time 303.12 seconds
Started Mar 24 12:50:58 PM PDT 24
Finished Mar 24 12:56:01 PM PDT 24
Peak memory 201876 kb
Host smart-18e628b7-d8e2-4509-af15-4c5196bdca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596671262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2596671262
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3968511983
Short name T446
Test name
Test status
Simulation time 328369913679 ps
CPU time 514.74 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:59:31 PM PDT 24
Peak memory 201824 kb
Host smart-0e34524e-11e2-4469-88e2-69142612282e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968511983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3968511983
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2894242514
Short name T328
Test name
Test status
Simulation time 381115362635 ps
CPU time 862.59 seconds
Started Mar 24 12:50:55 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 201864 kb
Host smart-f9029870-3121-4f49-896d-aa3905059985
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894242514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2894242514
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3131206854
Short name T607
Test name
Test status
Simulation time 195695397933 ps
CPU time 444.8 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:58:25 PM PDT 24
Peak memory 201700 kb
Host smart-0f276922-0190-4255-9e17-b4e89b402c7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131206854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3131206854
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3542240925
Short name T363
Test name
Test status
Simulation time 138123616273 ps
CPU time 706.82 seconds
Started Mar 24 12:51:04 PM PDT 24
Finished Mar 24 01:02:51 PM PDT 24
Peak memory 202192 kb
Host smart-51ddf0e3-6175-4c54-87bc-03d11e9fa452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542240925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3542240925
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1325289361
Short name T622
Test name
Test status
Simulation time 29689130360 ps
CPU time 40.17 seconds
Started Mar 24 12:51:05 PM PDT 24
Finished Mar 24 12:51:46 PM PDT 24
Peak memory 201508 kb
Host smart-6de70a33-ee04-4f7a-8895-a096cac02c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325289361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1325289361
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.82120463
Short name T644
Test name
Test status
Simulation time 3914791703 ps
CPU time 5.27 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:51:05 PM PDT 24
Peak memory 201548 kb
Host smart-dff8dcd6-7628-41eb-9b03-4b3e4d929774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82120463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.82120463
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3248964324
Short name T202
Test name
Test status
Simulation time 6066452647 ps
CPU time 4.38 seconds
Started Mar 24 12:50:56 PM PDT 24
Finished Mar 24 12:51:01 PM PDT 24
Peak memory 201624 kb
Host smart-699fba05-ec17-407c-9f09-9b10f19979cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248964324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3248964324
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3928856009
Short name T780
Test name
Test status
Simulation time 308953623599 ps
CPU time 184.04 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 12:54:05 PM PDT 24
Peak memory 210456 kb
Host smart-9089e088-852f-42c1-8bf7-0243f4660fa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928856009 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3928856009
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2019698987
Short name T112
Test name
Test status
Simulation time 333937157 ps
CPU time 0.97 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:51:01 PM PDT 24
Peak memory 201568 kb
Host smart-9e242b4c-b6b4-4441-94ff-a200bed99d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019698987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2019698987
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.555782314
Short name T277
Test name
Test status
Simulation time 354466263644 ps
CPU time 198.32 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:54:22 PM PDT 24
Peak memory 201840 kb
Host smart-1f6f4eab-b088-44e1-a91c-5bffd0d3fd04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555782314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.555782314
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1782411759
Short name T199
Test name
Test status
Simulation time 332598119230 ps
CPU time 52.2 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 12:51:53 PM PDT 24
Peak memory 201752 kb
Host smart-bbc5c760-3160-413b-ae6b-94281baef890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782411759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1782411759
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1658998662
Short name T8
Test name
Test status
Simulation time 333290010439 ps
CPU time 360.62 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:57:04 PM PDT 24
Peak memory 201832 kb
Host smart-66569c31-6c85-4623-9116-23f31ffdc8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658998662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1658998662
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.719509460
Short name T450
Test name
Test status
Simulation time 326704299336 ps
CPU time 358.24 seconds
Started Mar 24 12:51:04 PM PDT 24
Finished Mar 24 12:57:03 PM PDT 24
Peak memory 201840 kb
Host smart-8719c81b-35be-4af6-9327-a5225b3caa08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=719509460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.719509460
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2571834473
Short name T161
Test name
Test status
Simulation time 499685194008 ps
CPU time 163.27 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:53:43 PM PDT 24
Peak memory 201848 kb
Host smart-e3e728dd-bdda-4afa-948e-e97c62a6e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571834473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2571834473
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.108989628
Short name T785
Test name
Test status
Simulation time 166324115043 ps
CPU time 86.77 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:52:29 PM PDT 24
Peak memory 201904 kb
Host smart-ca75e402-83fb-487a-ae38-bea669a6357a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=108989628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.108989628
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.528424344
Short name T63
Test name
Test status
Simulation time 174323028386 ps
CPU time 332.48 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:56:36 PM PDT 24
Peak memory 201868 kb
Host smart-16f65be6-279d-4110-8fff-e53e595c5826
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528424344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.528424344
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1281261879
Short name T496
Test name
Test status
Simulation time 601398199913 ps
CPU time 1336.87 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 01:13:21 PM PDT 24
Peak memory 201872 kb
Host smart-ab1a2f2f-70fa-49b2-ae2c-34ff169ae26c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281261879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1281261879
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1339473732
Short name T551
Test name
Test status
Simulation time 83412610882 ps
CPU time 352.46 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:56:55 PM PDT 24
Peak memory 202160 kb
Host smart-95533895-4526-4908-be90-1db0f80c96db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339473732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1339473732
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2113856470
Short name T414
Test name
Test status
Simulation time 22639492900 ps
CPU time 12.02 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:51:15 PM PDT 24
Peak memory 201632 kb
Host smart-e5cb31c0-bcac-4c58-9f27-ad7f8aa0676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113856470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2113856470
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2398451297
Short name T647
Test name
Test status
Simulation time 3535391740 ps
CPU time 4.45 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:51:07 PM PDT 24
Peak memory 201580 kb
Host smart-b9114582-292e-4e54-8e2e-ff6623fe097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398451297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2398451297
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2459699509
Short name T26
Test name
Test status
Simulation time 5872287180 ps
CPU time 4.16 seconds
Started Mar 24 12:51:04 PM PDT 24
Finished Mar 24 12:51:08 PM PDT 24
Peak memory 201636 kb
Host smart-5550a79e-04aa-4afe-9ccd-11a894e33049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459699509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2459699509
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2379368393
Short name T477
Test name
Test status
Simulation time 57328963527 ps
CPU time 35.67 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:51:38 PM PDT 24
Peak memory 202008 kb
Host smart-b5610aa9-0f2b-4efd-b01e-c6e1119ec002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379368393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2379368393
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2469316459
Short name T567
Test name
Test status
Simulation time 61417003526 ps
CPU time 255.22 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:55:16 PM PDT 24
Peak memory 210536 kb
Host smart-ebfc0020-6acc-4e9d-8e26-59e916fe9373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469316459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2469316459
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2849382493
Short name T387
Test name
Test status
Simulation time 352432981 ps
CPU time 1.38 seconds
Started Mar 24 12:51:08 PM PDT 24
Finished Mar 24 12:51:10 PM PDT 24
Peak memory 201540 kb
Host smart-4dd4a7e1-2ef1-4ec1-a566-58429e476e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849382493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2849382493
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.11633021
Short name T652
Test name
Test status
Simulation time 161229012923 ps
CPU time 30.07 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:51:30 PM PDT 24
Peak memory 201804 kb
Host smart-a062ac77-daa4-4261-b30d-e1f71d45421b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gatin
g.11633021
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1543684817
Short name T118
Test name
Test status
Simulation time 558517016470 ps
CPU time 312.21 seconds
Started Mar 24 12:51:04 PM PDT 24
Finished Mar 24 12:56:16 PM PDT 24
Peak memory 201836 kb
Host smart-92d9446f-e681-46d5-8105-1da8557e37ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543684817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1543684817
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2844339750
Short name T734
Test name
Test status
Simulation time 333346991802 ps
CPU time 203.9 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:54:27 PM PDT 24
Peak memory 201840 kb
Host smart-25e45462-9817-4121-9341-387e96159c31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844339750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2844339750
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.688124683
Short name T418
Test name
Test status
Simulation time 325437024571 ps
CPU time 703.75 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 201740 kb
Host smart-3a0551a5-5987-439d-9a97-ad4a28815731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688124683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.688124683
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1731906364
Short name T608
Test name
Test status
Simulation time 332532921953 ps
CPU time 174.73 seconds
Started Mar 24 12:51:00 PM PDT 24
Finished Mar 24 12:53:55 PM PDT 24
Peak memory 201692 kb
Host smart-6cb87fc7-eca5-4c55-8ab4-11935a6cf311
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731906364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1731906364
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1197478364
Short name T336
Test name
Test status
Simulation time 182655910794 ps
CPU time 420.86 seconds
Started Mar 24 12:51:02 PM PDT 24
Finished Mar 24 12:58:03 PM PDT 24
Peak memory 201936 kb
Host smart-8a12e87b-0472-42c1-b11a-9a889017bff5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197478364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1197478364
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2341541557
Short name T60
Test name
Test status
Simulation time 95228973152 ps
CPU time 395.98 seconds
Started Mar 24 12:51:01 PM PDT 24
Finished Mar 24 12:57:38 PM PDT 24
Peak memory 202216 kb
Host smart-86b6065a-3a76-420a-911a-b52ea194e949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341541557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2341541557
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2226643256
Short name T511
Test name
Test status
Simulation time 40265757660 ps
CPU time 24.18 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:51:28 PM PDT 24
Peak memory 201684 kb
Host smart-3b125f9f-3e54-4b25-804b-3de43002abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226643256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2226643256
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.244529342
Short name T692
Test name
Test status
Simulation time 3301703468 ps
CPU time 1.17 seconds
Started Mar 24 12:51:05 PM PDT 24
Finished Mar 24 12:51:07 PM PDT 24
Peak memory 201572 kb
Host smart-6b94098e-8988-4045-827d-24da385de847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244529342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.244529342
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2411482830
Short name T370
Test name
Test status
Simulation time 5612280141 ps
CPU time 3.91 seconds
Started Mar 24 12:51:03 PM PDT 24
Finished Mar 24 12:51:07 PM PDT 24
Peak memory 201680 kb
Host smart-7d012a10-1f39-4ae0-a110-725ffa0005cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411482830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2411482830
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.236091778
Short name T323
Test name
Test status
Simulation time 292443739683 ps
CPU time 711.02 seconds
Started Mar 24 12:51:08 PM PDT 24
Finished Mar 24 01:02:59 PM PDT 24
Peak memory 202112 kb
Host smart-4298291d-baf2-4a6a-a8ae-992ccb86c273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236091778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
236091778
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3868580557
Short name T13
Test name
Test status
Simulation time 78744007873 ps
CPU time 86.71 seconds
Started Mar 24 12:51:06 PM PDT 24
Finished Mar 24 12:52:33 PM PDT 24
Peak memory 218284 kb
Host smart-078320ef-b541-4b29-bdcd-4ad514b1d4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868580557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3868580557
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.455441919
Short name T548
Test name
Test status
Simulation time 300535924 ps
CPU time 1.14 seconds
Started Mar 24 12:51:06 PM PDT 24
Finished Mar 24 12:51:07 PM PDT 24
Peak memory 201520 kb
Host smart-8525443e-7f0e-4edd-8539-370e732c9cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455441919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.455441919
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1521401083
Short name T587
Test name
Test status
Simulation time 195420092583 ps
CPU time 74.28 seconds
Started Mar 24 12:51:08 PM PDT 24
Finished Mar 24 12:52:22 PM PDT 24
Peak memory 201844 kb
Host smart-9d68ed49-b5b7-485d-946b-05adc1bf87b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521401083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1521401083
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.482896526
Short name T10
Test name
Test status
Simulation time 321362089347 ps
CPU time 194.81 seconds
Started Mar 24 12:51:08 PM PDT 24
Finished Mar 24 12:54:23 PM PDT 24
Peak memory 201764 kb
Host smart-65b20519-612b-4782-8f6f-79aa2c3c22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482896526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.482896526
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.920636554
Short name T481
Test name
Test status
Simulation time 161314009979 ps
CPU time 101.39 seconds
Started Mar 24 12:51:12 PM PDT 24
Finished Mar 24 12:52:54 PM PDT 24
Peak memory 201828 kb
Host smart-5514a8a1-e9f3-46aa-aeb0-c35802f10846
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=920636554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.920636554
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3399783452
Short name T700
Test name
Test status
Simulation time 166246457499 ps
CPU time 385.33 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:57:38 PM PDT 24
Peak memory 201888 kb
Host smart-6fbf47dc-55b2-4780-8f6b-2f6d3d002799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399783452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3399783452
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3934621971
Short name T537
Test name
Test status
Simulation time 162529261012 ps
CPU time 103.09 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:52:57 PM PDT 24
Peak memory 201840 kb
Host smart-ab29bff5-b937-411d-adda-2840b52ff55e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934621971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3934621971
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.911112765
Short name T252
Test name
Test status
Simulation time 372070959193 ps
CPU time 239.38 seconds
Started Mar 24 12:51:06 PM PDT 24
Finished Mar 24 12:55:05 PM PDT 24
Peak memory 201932 kb
Host smart-f42a0897-970c-4c6a-9d73-18184d628daf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911112765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.911112765
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3031624571
Short name T642
Test name
Test status
Simulation time 197217506969 ps
CPU time 157.73 seconds
Started Mar 24 12:51:07 PM PDT 24
Finished Mar 24 12:53:45 PM PDT 24
Peak memory 201820 kb
Host smart-8c89fd09-a894-477c-971c-9306e1177f9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031624571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3031624571
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.494686610
Short name T220
Test name
Test status
Simulation time 133430506828 ps
CPU time 481.73 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:59:15 PM PDT 24
Peak memory 202140 kb
Host smart-2062ff43-dbb5-4adb-a8f5-63138c857d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494686610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.494686610
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1663727630
Short name T552
Test name
Test status
Simulation time 30682416151 ps
CPU time 45.54 seconds
Started Mar 24 12:51:06 PM PDT 24
Finished Mar 24 12:51:52 PM PDT 24
Peak memory 201636 kb
Host smart-f461ef0c-9a07-40fb-a2b8-7fa25f458c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663727630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1663727630
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3483984323
Short name T609
Test name
Test status
Simulation time 4193388347 ps
CPU time 3.2 seconds
Started Mar 24 12:51:06 PM PDT 24
Finished Mar 24 12:51:09 PM PDT 24
Peak memory 201592 kb
Host smart-f1908567-f15a-47f6-b659-488791e58eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483984323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3483984323
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.885902286
Short name T159
Test name
Test status
Simulation time 6013026091 ps
CPU time 9.33 seconds
Started Mar 24 12:51:08 PM PDT 24
Finished Mar 24 12:51:17 PM PDT 24
Peak memory 201680 kb
Host smart-75c00388-5484-4ea8-af24-2db456441293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885902286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.885902286
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.413984963
Short name T135
Test name
Test status
Simulation time 307768421968 ps
CPU time 282.36 seconds
Started Mar 24 12:51:12 PM PDT 24
Finished Mar 24 12:55:54 PM PDT 24
Peak memory 210484 kb
Host smart-5823451c-7c08-4a97-9229-dcd4b3fd6b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413984963 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.413984963
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1783675549
Short name T550
Test name
Test status
Simulation time 514673118 ps
CPU time 0.96 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:25 PM PDT 24
Peak memory 201540 kb
Host smart-462f0859-6f5b-416c-84cc-38a5064be08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783675549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1783675549
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3100876699
Short name T181
Test name
Test status
Simulation time 533256627470 ps
CPU time 126.8 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:52:30 PM PDT 24
Peak memory 201912 kb
Host smart-eedb972c-cc52-4c46-8489-d60c2a81e0f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100876699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3100876699
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.403911848
Short name T43
Test name
Test status
Simulation time 159896434658 ps
CPU time 60.9 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:51:23 PM PDT 24
Peak memory 201844 kb
Host smart-4be9420e-016e-4440-9624-36dfc7083520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403911848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.403911848
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1197849835
Short name T7
Test name
Test status
Simulation time 483528717462 ps
CPU time 1126.48 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 01:09:02 PM PDT 24
Peak memory 201840 kb
Host smart-f0b9025d-f0ed-44cc-890e-3da151b5480e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197849835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1197849835
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3976345557
Short name T533
Test name
Test status
Simulation time 168069597645 ps
CPU time 400.43 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:57:08 PM PDT 24
Peak memory 201816 kb
Host smart-5fc13598-c9ae-421a-98fc-b0e5909f654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976345557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3976345557
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.108435164
Short name T206
Test name
Test status
Simulation time 160787898720 ps
CPU time 96.44 seconds
Started Mar 24 12:50:15 PM PDT 24
Finished Mar 24 12:51:51 PM PDT 24
Peak memory 201820 kb
Host smart-6e557006-d437-440e-9b86-b4992e1c68e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=108435164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.108435164
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3817590113
Short name T211
Test name
Test status
Simulation time 167566405038 ps
CPU time 206.3 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:53:40 PM PDT 24
Peak memory 201880 kb
Host smart-178ae1f5-e09d-4bf2-8cb3-a01ff60b8880
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817590113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3817590113
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2745427463
Short name T579
Test name
Test status
Simulation time 601873583363 ps
CPU time 1557.53 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 01:16:11 PM PDT 24
Peak memory 201956 kb
Host smart-1c629d43-f7ad-4fad-bf22-6ac5037d3442
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745427463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2745427463
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1891851208
Short name T221
Test name
Test status
Simulation time 115521508568 ps
CPU time 447.53 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:57:52 PM PDT 24
Peak memory 202192 kb
Host smart-8d40e65f-502e-4001-977a-0c850ec41151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891851208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1891851208
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2790714972
Short name T44
Test name
Test status
Simulation time 33351049659 ps
CPU time 45.55 seconds
Started Mar 24 12:50:13 PM PDT 24
Finished Mar 24 12:50:58 PM PDT 24
Peak memory 201616 kb
Host smart-70fa4358-5af4-4ee5-8da7-af58796f3c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790714972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2790714972
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4206986161
Short name T675
Test name
Test status
Simulation time 2677512843 ps
CPU time 6.46 seconds
Started Mar 24 12:50:14 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 201600 kb
Host smart-efd0f9b4-2275-4df4-b736-a1b70c20dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206986161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4206986161
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.203728333
Short name T84
Test name
Test status
Simulation time 8124547376 ps
CPU time 18.14 seconds
Started Mar 24 12:50:37 PM PDT 24
Finished Mar 24 12:50:56 PM PDT 24
Peak memory 218488 kb
Host smart-0b8df240-b150-4e5d-9063-82b9957d1400
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203728333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.203728333
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3769293652
Short name T190
Test name
Test status
Simulation time 6039852074 ps
CPU time 3.13 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 201528 kb
Host smart-4898d516-994f-4d03-ba09-6c215e0f2260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769293652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3769293652
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1869754908
Short name T319
Test name
Test status
Simulation time 435064638912 ps
CPU time 1310.11 seconds
Started Mar 24 12:50:16 PM PDT 24
Finished Mar 24 01:12:07 PM PDT 24
Peak memory 210352 kb
Host smart-7479e67c-a311-4465-a87d-767df7ac4da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869754908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1869754908
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.540125992
Short name T646
Test name
Test status
Simulation time 532667187 ps
CPU time 1.75 seconds
Started Mar 24 12:51:14 PM PDT 24
Finished Mar 24 12:51:16 PM PDT 24
Peak memory 201524 kb
Host smart-9de420d4-7adf-484b-a524-7e0bf54f6bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540125992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.540125992
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1986264237
Short name T637
Test name
Test status
Simulation time 489286653716 ps
CPU time 287.72 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:56:01 PM PDT 24
Peak memory 201824 kb
Host smart-49d21c19-253e-483b-822a-e160823d5a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986264237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1986264237
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.4207086314
Short name T767
Test name
Test status
Simulation time 164297296936 ps
CPU time 208.58 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:54:41 PM PDT 24
Peak memory 201864 kb
Host smart-a2af4f93-d8ba-4472-acb8-5f965f7411b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207086314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4207086314
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1055931983
Short name T100
Test name
Test status
Simulation time 161400075064 ps
CPU time 45.91 seconds
Started Mar 24 12:51:15 PM PDT 24
Finished Mar 24 12:52:01 PM PDT 24
Peak memory 201892 kb
Host smart-05a76858-09a4-465e-be31-df71a9cc4245
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055931983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1055931983
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3472069825
Short name T350
Test name
Test status
Simulation time 178896974335 ps
CPU time 429.55 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:58:23 PM PDT 24
Peak memory 201912 kb
Host smart-23c753e5-51c2-4b46-9741-0016d37f7a7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472069825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3472069825
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3804568212
Short name T628
Test name
Test status
Simulation time 197754509730 ps
CPU time 57.21 seconds
Started Mar 24 12:51:12 PM PDT 24
Finished Mar 24 12:52:10 PM PDT 24
Peak memory 201920 kb
Host smart-8844b3ad-d211-4dd9-9100-69405c1d6918
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804568212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3804568212
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4119104327
Short name T222
Test name
Test status
Simulation time 88186515046 ps
CPU time 378.14 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 202216 kb
Host smart-38c7503b-345f-4ec8-ad95-9431f7fb5def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119104327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4119104327
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2417288044
Short name T711
Test name
Test status
Simulation time 36108675008 ps
CPU time 89.84 seconds
Started Mar 24 12:51:15 PM PDT 24
Finished Mar 24 12:52:45 PM PDT 24
Peak memory 201564 kb
Host smart-c45cede2-eea0-4304-bdc8-172c58dec08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417288044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2417288044
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1725781074
Short name T713
Test name
Test status
Simulation time 3652738227 ps
CPU time 8.89 seconds
Started Mar 24 12:51:12 PM PDT 24
Finished Mar 24 12:51:21 PM PDT 24
Peak memory 201552 kb
Host smart-c6d95b06-eb58-4c93-a10e-3cd9a7cf28ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725781074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1725781074
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.988482883
Short name T29
Test name
Test status
Simulation time 5982673342 ps
CPU time 14.69 seconds
Started Mar 24 12:51:15 PM PDT 24
Finished Mar 24 12:51:29 PM PDT 24
Peak memory 201632 kb
Host smart-74e48251-b050-43f0-8912-63f0aa98d0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988482883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.988482883
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1940422530
Short name T753
Test name
Test status
Simulation time 68405352596 ps
CPU time 29.23 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:51:42 PM PDT 24
Peak memory 210168 kb
Host smart-fe3d2a40-dec9-4a29-ac90-1886f48f77dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940422530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1940422530
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.255230888
Short name T698
Test name
Test status
Simulation time 505958319 ps
CPU time 1.43 seconds
Started Mar 24 12:51:18 PM PDT 24
Finished Mar 24 12:51:20 PM PDT 24
Peak memory 201548 kb
Host smart-372627ce-edcb-4246-9fe3-14829e922918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255230888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.255230888
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3937163189
Short name T342
Test name
Test status
Simulation time 330450470965 ps
CPU time 220.06 seconds
Started Mar 24 12:51:16 PM PDT 24
Finished Mar 24 12:54:56 PM PDT 24
Peak memory 201944 kb
Host smart-850ff968-cf64-4761-902f-5039f330746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937163189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3937163189
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4199395324
Short name T462
Test name
Test status
Simulation time 165456776803 ps
CPU time 88.29 seconds
Started Mar 24 12:51:17 PM PDT 24
Finished Mar 24 12:52:45 PM PDT 24
Peak memory 201840 kb
Host smart-b7d48eaa-ad8a-4b14-bfee-bc425c72ad64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199395324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4199395324
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2981795031
Short name T458
Test name
Test status
Simulation time 159456854827 ps
CPU time 51.77 seconds
Started Mar 24 12:51:13 PM PDT 24
Finished Mar 24 12:52:05 PM PDT 24
Peak memory 201824 kb
Host smart-0cea2c44-9a17-4fde-b200-ca0f91dff686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981795031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2981795031
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2260073966
Short name T185
Test name
Test status
Simulation time 488958092026 ps
CPU time 288.95 seconds
Started Mar 24 12:51:11 PM PDT 24
Finished Mar 24 12:56:00 PM PDT 24
Peak memory 201844 kb
Host smart-bb91beab-cf13-4d41-bea6-bcefabf3f8ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260073966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2260073966
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3798135760
Short name T170
Test name
Test status
Simulation time 542116937345 ps
CPU time 153.43 seconds
Started Mar 24 12:51:17 PM PDT 24
Finished Mar 24 12:53:50 PM PDT 24
Peak memory 201952 kb
Host smart-f92f9732-4be8-4ee4-801a-4c532081dad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798135760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3798135760
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2825475981
Short name T447
Test name
Test status
Simulation time 385055064267 ps
CPU time 838.86 seconds
Started Mar 24 12:51:20 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 202152 kb
Host smart-005a004e-146c-4371-b61e-27add9e39a03
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825475981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2825475981
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3169868083
Short name T223
Test name
Test status
Simulation time 108646169701 ps
CPU time 431.06 seconds
Started Mar 24 12:51:17 PM PDT 24
Finished Mar 24 12:58:29 PM PDT 24
Peak memory 202220 kb
Host smart-86d02eed-28f8-4f5b-8e20-e5b47906e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169868083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3169868083
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2998662179
Short name T476
Test name
Test status
Simulation time 27452251503 ps
CPU time 17.93 seconds
Started Mar 24 12:51:19 PM PDT 24
Finished Mar 24 12:51:37 PM PDT 24
Peak memory 201660 kb
Host smart-cd1363a8-98a0-4f14-9659-d1f83ce47bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998662179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2998662179
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4096434318
Short name T510
Test name
Test status
Simulation time 4049667113 ps
CPU time 10.67 seconds
Started Mar 24 12:51:19 PM PDT 24
Finished Mar 24 12:51:30 PM PDT 24
Peak memory 201552 kb
Host smart-ded16258-1e46-4c44-80ca-d9606ae1b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096434318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4096434318
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2061240295
Short name T762
Test name
Test status
Simulation time 5616776682 ps
CPU time 13.81 seconds
Started Mar 24 12:51:14 PM PDT 24
Finished Mar 24 12:51:28 PM PDT 24
Peak memory 201592 kb
Host smart-2ddbdc6d-2712-480a-a890-4939d008cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061240295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2061240295
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3451306931
Short name T667
Test name
Test status
Simulation time 194794163909 ps
CPU time 481.03 seconds
Started Mar 24 12:51:20 PM PDT 24
Finished Mar 24 12:59:21 PM PDT 24
Peak memory 202076 kb
Host smart-9de8d916-7fd0-4e17-8aa5-14b026f1f1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451306931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3451306931
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4262160675
Short name T393
Test name
Test status
Simulation time 404777705 ps
CPU time 1.57 seconds
Started Mar 24 12:51:26 PM PDT 24
Finished Mar 24 12:51:28 PM PDT 24
Peak memory 201564 kb
Host smart-50d77418-084f-4591-bb9a-df238cc46851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262160675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4262160675
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.761554367
Short name T689
Test name
Test status
Simulation time 156994587297 ps
CPU time 78.56 seconds
Started Mar 24 12:51:27 PM PDT 24
Finished Mar 24 12:52:46 PM PDT 24
Peak memory 201876 kb
Host smart-df5a6880-f9fa-4429-895b-e6ccc98d3fe5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761554367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.761554367
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2972864615
Short name T347
Test name
Test status
Simulation time 499007862598 ps
CPU time 597.64 seconds
Started Mar 24 12:51:25 PM PDT 24
Finished Mar 24 01:01:23 PM PDT 24
Peak memory 201308 kb
Host smart-ddd3201a-439b-4a46-9162-37593a58ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972864615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2972864615
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4023644714
Short name T681
Test name
Test status
Simulation time 496461254767 ps
CPU time 259.82 seconds
Started Mar 24 12:51:24 PM PDT 24
Finished Mar 24 12:55:45 PM PDT 24
Peak memory 201860 kb
Host smart-bdcc1706-8a3b-4bfb-b738-b08f8e1ba83b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023644714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4023644714
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2562983864
Short name T231
Test name
Test status
Simulation time 322331808389 ps
CPU time 749.36 seconds
Started Mar 24 12:51:22 PM PDT 24
Finished Mar 24 01:03:52 PM PDT 24
Peak memory 201808 kb
Host smart-5869cca3-2082-4aa6-9321-78db63dddc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562983864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2562983864
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.252116065
Short name T461
Test name
Test status
Simulation time 159266209320 ps
CPU time 109.78 seconds
Started Mar 24 12:51:25 PM PDT 24
Finished Mar 24 12:53:15 PM PDT 24
Peak memory 201304 kb
Host smart-1b035f24-dbde-44ee-a07a-45e80ac7cd90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=252116065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.252116065
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.922056131
Short name T588
Test name
Test status
Simulation time 550067128440 ps
CPU time 347.04 seconds
Started Mar 24 12:51:24 PM PDT 24
Finished Mar 24 12:57:12 PM PDT 24
Peak memory 201904 kb
Host smart-1b4f6588-6e31-438d-8bfc-88f4f3c0d3d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922056131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.922056131
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.803607326
Short name T793
Test name
Test status
Simulation time 594354044179 ps
CPU time 1395.67 seconds
Started Mar 24 12:51:26 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 201864 kb
Host smart-5c9d076a-e674-457c-a125-c244d7ed3d4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803607326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.803607326
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1237022597
Short name T563
Test name
Test status
Simulation time 142973689946 ps
CPU time 549.57 seconds
Started Mar 24 12:51:27 PM PDT 24
Finished Mar 24 01:00:37 PM PDT 24
Peak memory 202100 kb
Host smart-582c2163-1772-4ba7-9738-73e67ce93d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237022597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1237022597
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2440505153
Short name T464
Test name
Test status
Simulation time 32579223913 ps
CPU time 75.47 seconds
Started Mar 24 12:51:24 PM PDT 24
Finished Mar 24 12:52:40 PM PDT 24
Peak memory 201616 kb
Host smart-2d83a554-4781-4a13-9588-c7a0d8e1a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440505153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2440505153
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3362163334
Short name T701
Test name
Test status
Simulation time 3547854116 ps
CPU time 1.55 seconds
Started Mar 24 12:51:22 PM PDT 24
Finished Mar 24 12:51:24 PM PDT 24
Peak memory 201568 kb
Host smart-834c7a1e-e98b-4b9a-9869-c6313a735d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362163334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3362163334
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1361402274
Short name T555
Test name
Test status
Simulation time 5858697348 ps
CPU time 6.37 seconds
Started Mar 24 12:51:23 PM PDT 24
Finished Mar 24 12:51:30 PM PDT 24
Peak memory 201664 kb
Host smart-cb1d90cb-53ac-4fa9-b2cb-dac707b11f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361402274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1361402274
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3381302350
Short name T674
Test name
Test status
Simulation time 231864335289 ps
CPU time 252.13 seconds
Started Mar 24 12:51:26 PM PDT 24
Finished Mar 24 12:55:38 PM PDT 24
Peak memory 202156 kb
Host smart-9120ac9c-10bf-4d5e-a4c3-c8c7f403bf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381302350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3381302350
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.650363433
Short name T334
Test name
Test status
Simulation time 458633019237 ps
CPU time 352.42 seconds
Started Mar 24 12:51:26 PM PDT 24
Finished Mar 24 12:57:20 PM PDT 24
Peak memory 210848 kb
Host smart-676420b6-0756-4d6b-bb3b-0875f5f5c72d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650363433 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.650363433
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1277949323
Short name T651
Test name
Test status
Simulation time 385564620 ps
CPU time 1.45 seconds
Started Mar 24 12:51:36 PM PDT 24
Finished Mar 24 12:51:38 PM PDT 24
Peak memory 201428 kb
Host smart-b8296fc7-8826-4973-a3fb-072e75ab46f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277949323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1277949323
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2250272366
Short name T732
Test name
Test status
Simulation time 169042409844 ps
CPU time 95.06 seconds
Started Mar 24 12:51:29 PM PDT 24
Finished Mar 24 12:53:04 PM PDT 24
Peak memory 201920 kb
Host smart-9e87f8a1-f421-4522-b1d2-e9ac1f41a54c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250272366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2250272366
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.410588776
Short name T539
Test name
Test status
Simulation time 344857784539 ps
CPU time 776.22 seconds
Started Mar 24 12:51:30 PM PDT 24
Finished Mar 24 01:04:26 PM PDT 24
Peak memory 201868 kb
Host smart-537d9287-1509-4d95-8268-5f3da2e037df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410588776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.410588776
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.729711551
Short name T562
Test name
Test status
Simulation time 323531324752 ps
CPU time 386.38 seconds
Started Mar 24 12:51:28 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 201840 kb
Host smart-ea0b8be3-a063-40ef-adce-4fe704aa0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729711551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.729711551
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1220665532
Short name T409
Test name
Test status
Simulation time 331488614786 ps
CPU time 139.27 seconds
Started Mar 24 12:51:30 PM PDT 24
Finished Mar 24 12:53:49 PM PDT 24
Peak memory 201828 kb
Host smart-f390b5da-45a4-44c1-b97f-05d5db410d4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220665532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1220665532
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.168445306
Short name T6
Test name
Test status
Simulation time 337052902702 ps
CPU time 823.25 seconds
Started Mar 24 12:51:27 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 201924 kb
Host smart-f04059b8-4bed-449c-88f4-ffb174df4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168445306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.168445306
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3319730833
Short name T735
Test name
Test status
Simulation time 162443793676 ps
CPU time 141.56 seconds
Started Mar 24 12:51:28 PM PDT 24
Finished Mar 24 12:53:49 PM PDT 24
Peak memory 201904 kb
Host smart-1c21aada-65d8-4f22-a113-a4a63e6fe91d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319730833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3319730833
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1571922445
Short name T326
Test name
Test status
Simulation time 611228149486 ps
CPU time 1442.84 seconds
Started Mar 24 12:51:28 PM PDT 24
Finished Mar 24 01:15:32 PM PDT 24
Peak memory 201900 kb
Host smart-0c54b311-21a9-4095-a148-91a1348635ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571922445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1571922445
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.4122832598
Short name T574
Test name
Test status
Simulation time 399526592019 ps
CPU time 937.15 seconds
Started Mar 24 12:51:30 PM PDT 24
Finished Mar 24 01:07:08 PM PDT 24
Peak memory 201824 kb
Host smart-0cfa487f-d456-4517-b317-cba066acba71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122832598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.4122832598
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2626628253
Short name T127
Test name
Test status
Simulation time 79731961409 ps
CPU time 222.81 seconds
Started Mar 24 12:51:36 PM PDT 24
Finished Mar 24 12:55:19 PM PDT 24
Peak memory 202080 kb
Host smart-e88dd7ff-b78a-487d-9c0a-68f704ab0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626628253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2626628253
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1593077361
Short name T483
Test name
Test status
Simulation time 37178495586 ps
CPU time 85.13 seconds
Started Mar 24 12:51:35 PM PDT 24
Finished Mar 24 12:53:01 PM PDT 24
Peak memory 201676 kb
Host smart-a7b2b505-e62b-4b1f-8698-efa2a1bbc70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593077361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1593077361
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.717750818
Short name T390
Test name
Test status
Simulation time 4258018867 ps
CPU time 9.92 seconds
Started Mar 24 12:51:34 PM PDT 24
Finished Mar 24 12:51:44 PM PDT 24
Peak memory 201536 kb
Host smart-3a7bf534-2152-4e61-b59b-e47c858232a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717750818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.717750818
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4103019834
Short name T712
Test name
Test status
Simulation time 6069045445 ps
CPU time 15.56 seconds
Started Mar 24 12:51:24 PM PDT 24
Finished Mar 24 12:51:40 PM PDT 24
Peak memory 201632 kb
Host smart-32317aee-c9b3-4d07-aba3-80917aeb6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103019834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4103019834
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3135212341
Short name T364
Test name
Test status
Simulation time 29790958928 ps
CPU time 50.12 seconds
Started Mar 24 12:51:32 PM PDT 24
Finished Mar 24 12:52:23 PM PDT 24
Peak memory 210468 kb
Host smart-4be01398-3932-4e8b-98df-31d4ff56ccc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135212341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3135212341
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3407117491
Short name T776
Test name
Test status
Simulation time 527173044 ps
CPU time 1.92 seconds
Started Mar 24 12:51:41 PM PDT 24
Finished Mar 24 12:51:44 PM PDT 24
Peak memory 201568 kb
Host smart-a9c1bb6c-15dc-4841-a374-181366d5587f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407117491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3407117491
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4147818278
Short name T738
Test name
Test status
Simulation time 175605357850 ps
CPU time 406.38 seconds
Started Mar 24 12:51:33 PM PDT 24
Finished Mar 24 12:58:19 PM PDT 24
Peak memory 201848 kb
Host smart-6a1aaa1d-1ba4-4ef0-a28d-c12a0672f962
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147818278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4147818278
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4221640923
Short name T325
Test name
Test status
Simulation time 341482782258 ps
CPU time 779.04 seconds
Started Mar 24 12:51:39 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 201804 kb
Host smart-1452a4a2-7b99-4b2b-911c-bc56cae01879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221640923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4221640923
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3867331899
Short name T787
Test name
Test status
Simulation time 162520883353 ps
CPU time 403.9 seconds
Started Mar 24 12:51:32 PM PDT 24
Finished Mar 24 12:58:16 PM PDT 24
Peak memory 201804 kb
Host smart-1da06be7-dda7-434c-9cf5-79c978258845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867331899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3867331899
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2247257036
Short name T576
Test name
Test status
Simulation time 167679265912 ps
CPU time 101.66 seconds
Started Mar 24 12:51:32 PM PDT 24
Finished Mar 24 12:53:14 PM PDT 24
Peak memory 201860 kb
Host smart-7856c7a9-bf3d-4334-8949-cda03f12c2ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247257036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2247257036
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.191304445
Short name T4
Test name
Test status
Simulation time 322293782948 ps
CPU time 357.69 seconds
Started Mar 24 12:51:32 PM PDT 24
Finished Mar 24 12:57:30 PM PDT 24
Peak memory 201836 kb
Host smart-1fbbedf6-4010-47a6-9c22-787765164894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191304445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.191304445
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.149728056
Short name T394
Test name
Test status
Simulation time 330290633689 ps
CPU time 734.83 seconds
Started Mar 24 12:51:33 PM PDT 24
Finished Mar 24 01:03:48 PM PDT 24
Peak memory 201864 kb
Host smart-8a57d751-6d8f-4289-9310-82c26af9a400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149728056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.149728056
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3021033102
Short name T305
Test name
Test status
Simulation time 171680171071 ps
CPU time 433.91 seconds
Started Mar 24 12:51:34 PM PDT 24
Finished Mar 24 12:58:48 PM PDT 24
Peak memory 201832 kb
Host smart-5c8b94c1-9ba9-4e2a-9db6-0db4e4425ad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021033102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3021033102
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.640595877
Short name T507
Test name
Test status
Simulation time 617173694634 ps
CPU time 375.54 seconds
Started Mar 24 12:51:33 PM PDT 24
Finished Mar 24 12:57:48 PM PDT 24
Peak memory 201864 kb
Host smart-a8053239-2987-4319-8f98-14e1958ed7b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640595877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.640595877
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3545950718
Short name T624
Test name
Test status
Simulation time 93102903203 ps
CPU time 338.54 seconds
Started Mar 24 12:51:39 PM PDT 24
Finished Mar 24 12:57:18 PM PDT 24
Peak memory 202172 kb
Host smart-0e725ad0-daa8-4070-b087-b81c21cd40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545950718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3545950718
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3220571860
Short name T544
Test name
Test status
Simulation time 40299912202 ps
CPU time 23.72 seconds
Started Mar 24 12:51:39 PM PDT 24
Finished Mar 24 12:52:03 PM PDT 24
Peak memory 201652 kb
Host smart-9f69d8b7-2938-4254-bbdc-e54050ba7bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220571860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3220571860
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1305792918
Short name T472
Test name
Test status
Simulation time 3087989091 ps
CPU time 2.68 seconds
Started Mar 24 12:51:39 PM PDT 24
Finished Mar 24 12:51:42 PM PDT 24
Peak memory 201600 kb
Host smart-f0d9e23b-71fd-425b-a600-c16860770599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305792918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1305792918
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3396454683
Short name T492
Test name
Test status
Simulation time 5740112394 ps
CPU time 3.75 seconds
Started Mar 24 12:51:33 PM PDT 24
Finished Mar 24 12:51:37 PM PDT 24
Peak memory 201652 kb
Host smart-b251451b-f219-43aa-a1da-b46350dd4b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396454683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3396454683
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1416726807
Short name T14
Test name
Test status
Simulation time 71825538883 ps
CPU time 211.83 seconds
Started Mar 24 12:51:38 PM PDT 24
Finished Mar 24 12:55:11 PM PDT 24
Peak memory 210568 kb
Host smart-0079810e-56c9-4efa-97fa-2ab317c84a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416726807 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1416726807
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3506986797
Short name T765
Test name
Test status
Simulation time 327244143 ps
CPU time 1.04 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:51:45 PM PDT 24
Peak memory 201476 kb
Host smart-7abf2220-c03c-4fec-b79c-b33fc10827f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506986797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3506986797
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3445411686
Short name T249
Test name
Test status
Simulation time 162458693664 ps
CPU time 384.39 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:58:08 PM PDT 24
Peak memory 201920 kb
Host smart-b91cbe7b-fc09-4ba0-91d1-d470f64bef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445411686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3445411686
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.184856191
Short name T239
Test name
Test status
Simulation time 490581429941 ps
CPU time 588.16 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 01:01:31 PM PDT 24
Peak memory 201856 kb
Host smart-86c9eeb7-82f5-4823-8f56-5409832e379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184856191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.184856191
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1108959884
Short name T410
Test name
Test status
Simulation time 327247438951 ps
CPU time 183.3 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:54:46 PM PDT 24
Peak memory 201812 kb
Host smart-07880b34-f79c-4f8d-a39e-7c8c2a5721a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108959884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1108959884
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.342233388
Short name T747
Test name
Test status
Simulation time 328995710837 ps
CPU time 102.85 seconds
Started Mar 24 12:51:38 PM PDT 24
Finished Mar 24 12:53:22 PM PDT 24
Peak memory 201920 kb
Host smart-4b52933e-7e6f-45e5-ae33-9079d61dacdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342233388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.342233388
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4137953005
Short name T742
Test name
Test status
Simulation time 160991274717 ps
CPU time 99.63 seconds
Started Mar 24 12:51:37 PM PDT 24
Finished Mar 24 12:53:17 PM PDT 24
Peak memory 201696 kb
Host smart-59310ebf-49a4-42a9-8be5-543d5362d470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137953005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4137953005
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3479987041
Short name T672
Test name
Test status
Simulation time 358101189720 ps
CPU time 195 seconds
Started Mar 24 12:51:42 PM PDT 24
Finished Mar 24 12:54:57 PM PDT 24
Peak memory 201792 kb
Host smart-90a827ee-ceae-497c-811d-49fe8e2b5d6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479987041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3479987041
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1675525259
Short name T796
Test name
Test status
Simulation time 609701761440 ps
CPU time 698.68 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 201912 kb
Host smart-68ccf39c-876d-4778-be74-dd9687b7d029
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675525259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1675525259
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1220442970
Short name T750
Test name
Test status
Simulation time 128849520863 ps
CPU time 464.88 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:59:28 PM PDT 24
Peak memory 202132 kb
Host smart-c4b5402c-7220-456b-8a9f-f0d4dc0444ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220442970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1220442970
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.813968988
Short name T591
Test name
Test status
Simulation time 43253455659 ps
CPU time 27.48 seconds
Started Mar 24 12:51:41 PM PDT 24
Finished Mar 24 12:52:09 PM PDT 24
Peak memory 201656 kb
Host smart-17a04fed-eecf-418a-8370-dcbf009cd798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813968988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.813968988
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4094591860
Short name T715
Test name
Test status
Simulation time 3260105678 ps
CPU time 4.73 seconds
Started Mar 24 12:51:44 PM PDT 24
Finished Mar 24 12:51:49 PM PDT 24
Peak memory 201576 kb
Host smart-fe52a407-f3a7-4b44-8677-908cbe84a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094591860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4094591860
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2339600329
Short name T403
Test name
Test status
Simulation time 5693440180 ps
CPU time 8.84 seconds
Started Mar 24 12:51:37 PM PDT 24
Finished Mar 24 12:51:46 PM PDT 24
Peak memory 201628 kb
Host smart-91d67dd2-c376-4875-bbc8-890ba6eb2abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339600329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2339600329
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3490447008
Short name T351
Test name
Test status
Simulation time 499822989938 ps
CPU time 630.94 seconds
Started Mar 24 12:51:41 PM PDT 24
Finished Mar 24 01:02:13 PM PDT 24
Peak memory 202236 kb
Host smart-937bccdc-2da1-4c86-8fcf-224e22d6b251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490447008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3490447008
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2383181134
Short name T51
Test name
Test status
Simulation time 75039842298 ps
CPU time 43.01 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:52:26 PM PDT 24
Peak memory 211972 kb
Host smart-2dea98f2-6642-40d1-ad50-63c97b535c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383181134 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2383181134
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3125960842
Short name T506
Test name
Test status
Simulation time 477683974 ps
CPU time 0.89 seconds
Started Mar 24 12:51:54 PM PDT 24
Finished Mar 24 12:51:55 PM PDT 24
Peak memory 201540 kb
Host smart-62bbaedc-4df8-47c0-9cac-e681cc8649d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125960842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3125960842
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1595898281
Short name T663
Test name
Test status
Simulation time 352847158378 ps
CPU time 563.79 seconds
Started Mar 24 12:51:48 PM PDT 24
Finished Mar 24 01:01:12 PM PDT 24
Peak memory 201960 kb
Host smart-b672ed53-0685-4f84-95f4-08c658abc6ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595898281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1595898281
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3543557741
Short name T284
Test name
Test status
Simulation time 346185896928 ps
CPU time 213.8 seconds
Started Mar 24 12:51:50 PM PDT 24
Finished Mar 24 12:55:24 PM PDT 24
Peak memory 201828 kb
Host smart-218e40bc-36b0-4db2-885c-62e80a81881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543557741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3543557741
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2281916618
Short name T208
Test name
Test status
Simulation time 489590470095 ps
CPU time 614.16 seconds
Started Mar 24 12:51:49 PM PDT 24
Finished Mar 24 01:02:04 PM PDT 24
Peak memory 201864 kb
Host smart-87de21ee-30f3-428c-bee2-554ae3a4a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281916618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2281916618
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2147562797
Short name T759
Test name
Test status
Simulation time 166477682963 ps
CPU time 108.46 seconds
Started Mar 24 12:51:48 PM PDT 24
Finished Mar 24 12:53:37 PM PDT 24
Peak memory 201828 kb
Host smart-3c13ef8e-2bb8-468f-b621-c9c3d83ed635
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147562797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2147562797
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3867165416
Short name T656
Test name
Test status
Simulation time 327311531745 ps
CPU time 363.86 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:57:47 PM PDT 24
Peak memory 201824 kb
Host smart-4ac5aec8-62d7-4492-8460-aa0d825df51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867165416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3867165416
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3809555190
Short name T473
Test name
Test status
Simulation time 326839637271 ps
CPU time 181.28 seconds
Started Mar 24 12:51:49 PM PDT 24
Finished Mar 24 12:54:51 PM PDT 24
Peak memory 201788 kb
Host smart-99ea4f44-5bec-483f-818f-960164ffd0ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809555190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3809555190
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2652805036
Short name T62
Test name
Test status
Simulation time 393207525477 ps
CPU time 193.83 seconds
Started Mar 24 12:51:49 PM PDT 24
Finished Mar 24 12:55:04 PM PDT 24
Peak memory 201836 kb
Host smart-2cbbe7b3-1ad9-4814-88b8-652f1974f668
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652805036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2652805036
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4231083693
Short name T763
Test name
Test status
Simulation time 100359763833 ps
CPU time 275.05 seconds
Started Mar 24 12:51:53 PM PDT 24
Finished Mar 24 12:56:28 PM PDT 24
Peak memory 202252 kb
Host smart-bd4887f2-1311-4a71-ae3b-f85a99fb41cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231083693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4231083693
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.225045257
Short name T384
Test name
Test status
Simulation time 46602419916 ps
CPU time 31.51 seconds
Started Mar 24 12:51:49 PM PDT 24
Finished Mar 24 12:52:21 PM PDT 24
Peak memory 201680 kb
Host smart-491e0852-3410-4006-9934-d2f799ecbae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225045257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.225045257
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.986945815
Short name T485
Test name
Test status
Simulation time 3820496657 ps
CPU time 9.62 seconds
Started Mar 24 12:51:48 PM PDT 24
Finished Mar 24 12:51:59 PM PDT 24
Peak memory 201548 kb
Host smart-9ca3158e-cebf-474b-aa2b-8281c3433623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986945815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.986945815
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2717661397
Short name T725
Test name
Test status
Simulation time 6026340500 ps
CPU time 6.77 seconds
Started Mar 24 12:51:43 PM PDT 24
Finished Mar 24 12:51:50 PM PDT 24
Peak memory 201584 kb
Host smart-af1030b7-6739-4319-8502-3d3c1e800ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717661397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2717661397
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2343797025
Short name T32
Test name
Test status
Simulation time 174934692244 ps
CPU time 198.78 seconds
Started Mar 24 12:51:56 PM PDT 24
Finished Mar 24 12:55:14 PM PDT 24
Peak memory 201820 kb
Host smart-7a70f3c8-7add-47b8-8da0-754883ea1636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343797025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2343797025
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4248147609
Short name T280
Test name
Test status
Simulation time 337185297604 ps
CPU time 68.24 seconds
Started Mar 24 12:51:54 PM PDT 24
Finished Mar 24 12:53:02 PM PDT 24
Peak memory 210152 kb
Host smart-d71121a3-b465-44c0-a452-f44b3056c851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248147609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4248147609
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3373802788
Short name T777
Test name
Test status
Simulation time 519380374 ps
CPU time 1.06 seconds
Started Mar 24 12:52:05 PM PDT 24
Finished Mar 24 12:52:06 PM PDT 24
Peak memory 201532 kb
Host smart-18e5de03-3863-4cf7-84db-427f40a75de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373802788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3373802788
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1634618105
Short name T594
Test name
Test status
Simulation time 528502563468 ps
CPU time 726.1 seconds
Started Mar 24 12:52:03 PM PDT 24
Finished Mar 24 01:04:10 PM PDT 24
Peak memory 201944 kb
Host smart-7d4e905e-0243-4df7-9eb8-f95b9e9f2f13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634618105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1634618105
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2838254872
Short name T259
Test name
Test status
Simulation time 327791701253 ps
CPU time 371.93 seconds
Started Mar 24 12:51:59 PM PDT 24
Finished Mar 24 12:58:11 PM PDT 24
Peak memory 201884 kb
Host smart-f0e0fc7c-1cdd-48f9-adc3-c25f9574b870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838254872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2838254872
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2621892449
Short name T388
Test name
Test status
Simulation time 162418494375 ps
CPU time 402.68 seconds
Started Mar 24 12:52:01 PM PDT 24
Finished Mar 24 12:58:44 PM PDT 24
Peak memory 201816 kb
Host smart-58d561bf-5699-4408-bf28-51b3ab30f767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621892449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2621892449
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3461223789
Short name T212
Test name
Test status
Simulation time 331098297162 ps
CPU time 729.86 seconds
Started Mar 24 12:51:54 PM PDT 24
Finished Mar 24 01:04:05 PM PDT 24
Peak memory 201932 kb
Host smart-23c980ee-012a-4880-986c-b216e47a24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461223789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3461223789
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4114961037
Short name T373
Test name
Test status
Simulation time 166644988749 ps
CPU time 370.81 seconds
Started Mar 24 12:52:00 PM PDT 24
Finished Mar 24 12:58:11 PM PDT 24
Peak memory 201896 kb
Host smart-08072502-a84e-4fe8-8049-937e5f106fc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114961037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4114961037
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1808583380
Short name T316
Test name
Test status
Simulation time 167524065486 ps
CPU time 102.11 seconds
Started Mar 24 12:51:58 PM PDT 24
Finished Mar 24 12:53:41 PM PDT 24
Peak memory 201900 kb
Host smart-8c814729-be40-4325-b000-3de3706115da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808583380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1808583380
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4027517564
Short name T769
Test name
Test status
Simulation time 200567902586 ps
CPU time 115.86 seconds
Started Mar 24 12:51:58 PM PDT 24
Finished Mar 24 12:53:54 PM PDT 24
Peak memory 201848 kb
Host smart-1217a3ee-3f8a-46f4-8e1b-f1ff057ea631
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027517564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4027517564
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2366075407
Short name T690
Test name
Test status
Simulation time 77852964664 ps
CPU time 274.18 seconds
Started Mar 24 12:52:06 PM PDT 24
Finished Mar 24 12:56:40 PM PDT 24
Peak memory 202108 kb
Host smart-ac487530-43d2-423e-9f84-433d519a9367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366075407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2366075407
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4283456665
Short name T553
Test name
Test status
Simulation time 22099155732 ps
CPU time 48.69 seconds
Started Mar 24 12:52:05 PM PDT 24
Finished Mar 24 12:52:54 PM PDT 24
Peak memory 201612 kb
Host smart-1370acb4-f00c-499e-8071-a8721ca1a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283456665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4283456665
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3777821529
Short name T616
Test name
Test status
Simulation time 3670231057 ps
CPU time 9.17 seconds
Started Mar 24 12:52:05 PM PDT 24
Finished Mar 24 12:52:14 PM PDT 24
Peak memory 201572 kb
Host smart-a8aaa495-6b88-446e-83c1-bcecd9667a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777821529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3777821529
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.44762585
Short name T436
Test name
Test status
Simulation time 5863711912 ps
CPU time 7.48 seconds
Started Mar 24 12:51:53 PM PDT 24
Finished Mar 24 12:52:00 PM PDT 24
Peak memory 201644 kb
Host smart-66c4cf9f-51c9-430f-bceb-fd72745443dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44762585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.44762585
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2326352087
Short name T215
Test name
Test status
Simulation time 58941140005 ps
CPU time 58.7 seconds
Started Mar 24 12:52:04 PM PDT 24
Finished Mar 24 12:53:03 PM PDT 24
Peak memory 210476 kb
Host smart-fec4bf50-0a8c-4452-8391-7d1a5a9bc3e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326352087 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2326352087
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2911838377
Short name T427
Test name
Test status
Simulation time 319633801 ps
CPU time 0.79 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 12:52:18 PM PDT 24
Peak memory 201536 kb
Host smart-54518457-a160-417a-a727-74d4da76b595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911838377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2911838377
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1057761725
Short name T109
Test name
Test status
Simulation time 523680046487 ps
CPU time 286.76 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 12:57:03 PM PDT 24
Peak memory 201760 kb
Host smart-bb9a6526-46d5-4fbd-b4c8-85e0c825d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057761725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1057761725
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3538905136
Short name T166
Test name
Test status
Simulation time 493736138541 ps
CPU time 254.34 seconds
Started Mar 24 12:52:10 PM PDT 24
Finished Mar 24 12:56:25 PM PDT 24
Peak memory 201848 kb
Host smart-28b630e4-b2ef-4e9d-a271-dbd443c046bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538905136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3538905136
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3833053379
Short name T445
Test name
Test status
Simulation time 329566021432 ps
CPU time 774.78 seconds
Started Mar 24 12:52:10 PM PDT 24
Finished Mar 24 01:05:05 PM PDT 24
Peak memory 201808 kb
Host smart-a8e270d4-ee32-49d7-8e73-011a641c8fe5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833053379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3833053379
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2406319854
Short name T454
Test name
Test status
Simulation time 164797714806 ps
CPU time 100.5 seconds
Started Mar 24 12:52:11 PM PDT 24
Finished Mar 24 12:53:52 PM PDT 24
Peak memory 201820 kb
Host smart-5f87bd7b-43f0-45cb-8998-0be4124995dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406319854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2406319854
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.444126254
Short name T441
Test name
Test status
Simulation time 328092472337 ps
CPU time 222.51 seconds
Started Mar 24 12:52:11 PM PDT 24
Finished Mar 24 12:55:54 PM PDT 24
Peak memory 201796 kb
Host smart-95e136fc-8014-4e23-9ca3-5307cef8b6a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=444126254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.444126254
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1670079078
Short name T606
Test name
Test status
Simulation time 167901455868 ps
CPU time 86.19 seconds
Started Mar 24 12:52:20 PM PDT 24
Finished Mar 24 12:53:48 PM PDT 24
Peak memory 201804 kb
Host smart-30c93741-2d2a-497a-832d-ac72d8422a13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670079078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1670079078
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1926795792
Short name T406
Test name
Test status
Simulation time 611004736844 ps
CPU time 140.29 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:54:42 PM PDT 24
Peak memory 201792 kb
Host smart-880ae474-7d7c-4a3d-bf5f-68dd0301567a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926795792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1926795792
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2385631236
Short name T514
Test name
Test status
Simulation time 86730589108 ps
CPU time 430.93 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 12:59:28 PM PDT 24
Peak memory 202104 kb
Host smart-cda90945-f976-4c38-84e6-8ed9c2ff0c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385631236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2385631236
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.279276181
Short name T3
Test name
Test status
Simulation time 32368047136 ps
CPU time 20.9 seconds
Started Mar 24 12:52:17 PM PDT 24
Finished Mar 24 12:52:39 PM PDT 24
Peak memory 201644 kb
Host smart-7bb1fd1f-d7a9-4711-8092-c088da0d8f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279276181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.279276181
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2126412749
Short name T182
Test name
Test status
Simulation time 4655379960 ps
CPU time 11.69 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:52:34 PM PDT 24
Peak memory 201512 kb
Host smart-231e6507-9149-4ee1-acb4-431482102622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126412749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2126412749
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2860872141
Short name T703
Test name
Test status
Simulation time 5721535220 ps
CPU time 14.27 seconds
Started Mar 24 12:52:05 PM PDT 24
Finished Mar 24 12:52:19 PM PDT 24
Peak memory 201688 kb
Host smart-f5da052b-1c40-457b-a740-2863a41e1b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860872141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2860872141
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2601942297
Short name T272
Test name
Test status
Simulation time 211831967087 ps
CPU time 464.53 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 01:00:02 PM PDT 24
Peak memory 201872 kb
Host smart-495781d4-c36e-4ae5-bf43-7d9cb243d8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601942297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2601942297
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3062640370
Short name T411
Test name
Test status
Simulation time 435773746 ps
CPU time 0.79 seconds
Started Mar 24 12:52:20 PM PDT 24
Finished Mar 24 12:52:21 PM PDT 24
Peak memory 201512 kb
Host smart-2bddb3f6-0e9b-4906-baa4-e954d2d29916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062640370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3062640370
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1498996933
Short name T339
Test name
Test status
Simulation time 543719711214 ps
CPU time 877.1 seconds
Started Mar 24 12:52:19 PM PDT 24
Finished Mar 24 01:06:58 PM PDT 24
Peak memory 201832 kb
Host smart-08bf8ad6-9b79-4bee-9a36-068d8513c136
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498996933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1498996933
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3192313041
Short name T255
Test name
Test status
Simulation time 168859636544 ps
CPU time 105.06 seconds
Started Mar 24 12:52:22 PM PDT 24
Finished Mar 24 12:54:07 PM PDT 24
Peak memory 201828 kb
Host smart-06c92064-623e-46ce-a1df-c3adf72dc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192313041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3192313041
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1579126495
Short name T397
Test name
Test status
Simulation time 331320639547 ps
CPU time 383.2 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 12:58:40 PM PDT 24
Peak memory 201816 kb
Host smart-218a00a2-04ab-4e9e-ad62-a374a4052671
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579126495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1579126495
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1264816378
Short name T341
Test name
Test status
Simulation time 334273814452 ps
CPU time 811.69 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 01:05:48 PM PDT 24
Peak memory 201868 kb
Host smart-cb899212-bc72-4951-b2ab-666af395ffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264816378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1264816378
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3280812363
Short name T101
Test name
Test status
Simulation time 170060480922 ps
CPU time 100.45 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:54:02 PM PDT 24
Peak memory 201724 kb
Host smart-945be338-b50d-4da2-a76e-78bdff327872
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280812363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3280812363
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3976929733
Short name T799
Test name
Test status
Simulation time 170244270112 ps
CPU time 206.02 seconds
Started Mar 24 12:52:16 PM PDT 24
Finished Mar 24 12:55:43 PM PDT 24
Peak memory 201912 kb
Host smart-d40e4ad8-99fd-4c08-ac43-d822f3d42478
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976929733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3976929733
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4110412007
Short name T457
Test name
Test status
Simulation time 582644528687 ps
CPU time 323.39 seconds
Started Mar 24 12:52:23 PM PDT 24
Finished Mar 24 12:57:47 PM PDT 24
Peak memory 202100 kb
Host smart-520fb6f0-76f6-4eed-aa90-cd8be985e5bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110412007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4110412007
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.475020842
Short name T398
Test name
Test status
Simulation time 85809532177 ps
CPU time 357.34 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:58:19 PM PDT 24
Peak memory 202148 kb
Host smart-eba39ccf-6f2e-4646-b6fa-bc915ce041ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475020842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.475020842
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1383076484
Short name T790
Test name
Test status
Simulation time 32976075276 ps
CPU time 59.46 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:53:21 PM PDT 24
Peak memory 201640 kb
Host smart-72f66761-e635-4452-9a1a-13bf5a160913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383076484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1383076484
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1662405165
Short name T721
Test name
Test status
Simulation time 3553925910 ps
CPU time 4.98 seconds
Started Mar 24 12:52:23 PM PDT 24
Finished Mar 24 12:52:28 PM PDT 24
Peak memory 201840 kb
Host smart-80cc728c-4fc0-4655-a013-8fe321039325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662405165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1662405165
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.179468340
Short name T629
Test name
Test status
Simulation time 5606230434 ps
CPU time 4.39 seconds
Started Mar 24 12:52:15 PM PDT 24
Finished Mar 24 12:52:21 PM PDT 24
Peak memory 201668 kb
Host smart-52729d54-093d-4f3e-99ea-a837b67fce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179468340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.179468340
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2859699014
Short name T794
Test name
Test status
Simulation time 328328661021 ps
CPU time 1125.86 seconds
Started Mar 24 12:52:20 PM PDT 24
Finished Mar 24 01:11:07 PM PDT 24
Peak memory 202124 kb
Host smart-1775d020-52c6-4703-8832-08dc1938f83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859699014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2859699014
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2682792719
Short name T133
Test name
Test status
Simulation time 354429507 ps
CPU time 1.44 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:50:27 PM PDT 24
Peak memory 201552 kb
Host smart-bee2ddd7-130a-42c6-aaee-bb30e38c34a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682792719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2682792719
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.546279481
Short name T327
Test name
Test status
Simulation time 161275241213 ps
CPU time 392.85 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:56:59 PM PDT 24
Peak memory 201948 kb
Host smart-6c13ddbf-d985-4731-8e1b-456c10f5d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546279481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.546279481
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3755886386
Short name T575
Test name
Test status
Simulation time 335749232390 ps
CPU time 378.52 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:56:47 PM PDT 24
Peak memory 201860 kb
Host smart-5aa9c097-ef36-4905-babb-c7b9c7ec8832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755886386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3755886386
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2016649624
Short name T114
Test name
Test status
Simulation time 497655915179 ps
CPU time 1149.89 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 01:09:37 PM PDT 24
Peak memory 201736 kb
Host smart-18ba8e86-5de6-41dd-96f9-27774703885b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016649624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2016649624
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.282576056
Short name T257
Test name
Test status
Simulation time 164630856536 ps
CPU time 92.61 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:51:55 PM PDT 24
Peak memory 201752 kb
Host smart-4947b540-f429-40a8-8e72-4224edf5d2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282576056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.282576056
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1998793194
Short name T38
Test name
Test status
Simulation time 317323038078 ps
CPU time 205.85 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:53:43 PM PDT 24
Peak memory 201832 kb
Host smart-65001923-33b0-43c7-92d5-6ca4a865dc37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998793194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1998793194
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1791766290
Short name T309
Test name
Test status
Simulation time 528868295189 ps
CPU time 329.35 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:55:59 PM PDT 24
Peak memory 201936 kb
Host smart-88512cb8-a525-4de7-bd4e-43fc56369195
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791766290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1791766290
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2071075215
Short name T110
Test name
Test status
Simulation time 385149319555 ps
CPU time 224.53 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:54:09 PM PDT 24
Peak memory 201836 kb
Host smart-f237eb3d-d0e0-4d51-91d8-1ece7d15073c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071075215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2071075215
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1488727255
Short name T664
Test name
Test status
Simulation time 131409300208 ps
CPU time 722.17 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 01:02:27 PM PDT 24
Peak memory 202084 kb
Host smart-85b91f19-a878-4f3d-be43-f408067af43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488727255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1488727255
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1637867295
Short name T478
Test name
Test status
Simulation time 27669087822 ps
CPU time 56.6 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:51:20 PM PDT 24
Peak memory 201628 kb
Host smart-f48e325e-144c-4298-84fb-103d7ded7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637867295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1637867295
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1208154100
Short name T203
Test name
Test status
Simulation time 3439111259 ps
CPU time 4.37 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 201448 kb
Host smart-e4986f49-9a7d-4167-a0fa-4fd957ff0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208154100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1208154100
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2198946098
Short name T83
Test name
Test status
Simulation time 7705077084 ps
CPU time 8.76 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:50:32 PM PDT 24
Peak memory 218492 kb
Host smart-74760abe-c2dd-41db-83d7-e883a5019c99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198946098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2198946098
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1226334193
Short name T779
Test name
Test status
Simulation time 6026911993 ps
CPU time 3.26 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:50:22 PM PDT 24
Peak memory 201652 kb
Host smart-89cfb289-e5ed-4d02-8115-83cec5b8b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226334193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1226334193
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3664713525
Short name T67
Test name
Test status
Simulation time 341049389981 ps
CPU time 210.53 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:53:55 PM PDT 24
Peak memory 201840 kb
Host smart-2f1c9edb-8fd0-40c6-820d-d81169bbea0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664713525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3664713525
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1956498278
Short name T19
Test name
Test status
Simulation time 242187129245 ps
CPU time 267.92 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:54:48 PM PDT 24
Peak memory 217828 kb
Host smart-a9dd0bcf-a744-43f1-b3ba-b4712125e2c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956498278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1956498278
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3492579234
Short name T383
Test name
Test status
Simulation time 455069849 ps
CPU time 0.82 seconds
Started Mar 24 12:52:38 PM PDT 24
Finished Mar 24 12:52:39 PM PDT 24
Peak memory 201468 kb
Host smart-eb28bdd9-1abe-4bab-962d-46dbe3f13b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492579234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3492579234
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1533135703
Short name T115
Test name
Test status
Simulation time 184494275179 ps
CPU time 374.67 seconds
Started Mar 24 12:52:26 PM PDT 24
Finished Mar 24 12:58:41 PM PDT 24
Peak memory 201840 kb
Host smart-a11de13c-077d-4de9-800d-c10ec6c22205
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533135703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1533135703
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2910672143
Short name T157
Test name
Test status
Simulation time 373046315285 ps
CPU time 245.3 seconds
Started Mar 24 12:52:29 PM PDT 24
Finished Mar 24 12:56:35 PM PDT 24
Peak memory 201948 kb
Host smart-6e36960c-da0e-4680-bb64-894853d319ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910672143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2910672143
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2922563421
Short name T262
Test name
Test status
Simulation time 493268205515 ps
CPU time 1166.58 seconds
Started Mar 24 12:52:26 PM PDT 24
Finished Mar 24 01:11:53 PM PDT 24
Peak memory 201880 kb
Host smart-f53aaf7b-13c6-4cc8-bde1-fc45880007f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922563421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2922563421
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4105234899
Short name T619
Test name
Test status
Simulation time 323583156766 ps
CPU time 693.24 seconds
Started Mar 24 12:52:29 PM PDT 24
Finished Mar 24 01:04:03 PM PDT 24
Peak memory 201932 kb
Host smart-3df40089-9122-4ed5-acdf-643e8c6a0b4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105234899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4105234899
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1996601476
Short name T460
Test name
Test status
Simulation time 167209940238 ps
CPU time 373.58 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:58:35 PM PDT 24
Peak memory 201820 kb
Host smart-19aba949-c213-488a-9e5d-e4ba62a345ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996601476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1996601476
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2197789293
Short name T728
Test name
Test status
Simulation time 165056030429 ps
CPU time 54.36 seconds
Started Mar 24 12:52:21 PM PDT 24
Finished Mar 24 12:53:16 PM PDT 24
Peak memory 201832 kb
Host smart-530427eb-6740-47ae-a0a8-34e686c004e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197789293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2197789293
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1456909696
Short name T772
Test name
Test status
Simulation time 405735615240 ps
CPU time 964.05 seconds
Started Mar 24 12:52:27 PM PDT 24
Finished Mar 24 01:08:32 PM PDT 24
Peak memory 201932 kb
Host smart-24440025-3718-4c82-adc2-ac1d93248c02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456909696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1456909696
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2450408442
Short name T120
Test name
Test status
Simulation time 75334683583 ps
CPU time 374.02 seconds
Started Mar 24 12:52:27 PM PDT 24
Finished Mar 24 12:58:41 PM PDT 24
Peak memory 202076 kb
Host smart-3212e435-5e31-4f15-9859-523484098cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450408442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2450408442
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.723650725
Short name T676
Test name
Test status
Simulation time 39414087823 ps
CPU time 22.65 seconds
Started Mar 24 12:52:27 PM PDT 24
Finished Mar 24 12:52:50 PM PDT 24
Peak memory 201632 kb
Host smart-34aca2e6-9a9b-4d4a-8037-ec112cfdf644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723650725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.723650725
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1144812399
Short name T486
Test name
Test status
Simulation time 4187800383 ps
CPU time 2.74 seconds
Started Mar 24 12:52:30 PM PDT 24
Finished Mar 24 12:52:33 PM PDT 24
Peak memory 201496 kb
Host smart-805d280c-f436-4031-ae8a-5db21881caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144812399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1144812399
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1097715939
Short name T442
Test name
Test status
Simulation time 6203310858 ps
CPU time 1.55 seconds
Started Mar 24 12:52:20 PM PDT 24
Finished Mar 24 12:52:23 PM PDT 24
Peak memory 201656 kb
Host smart-dab207e3-62f4-45cb-8a52-11a496a81d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097715939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1097715939
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4103104252
Short name T71
Test name
Test status
Simulation time 102131398753 ps
CPU time 505.48 seconds
Started Mar 24 12:52:30 PM PDT 24
Finished Mar 24 01:00:56 PM PDT 24
Peak memory 202244 kb
Host smart-68181967-41b1-42c2-8493-15f998778ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103104252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4103104252
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.244479718
Short name T634
Test name
Test status
Simulation time 350540810 ps
CPU time 0.97 seconds
Started Mar 24 12:52:47 PM PDT 24
Finished Mar 24 12:52:48 PM PDT 24
Peak memory 201804 kb
Host smart-7f525a35-f8be-47dd-aeea-360cbb637058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244479718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.244479718
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.547955210
Short name T68
Test name
Test status
Simulation time 495781049408 ps
CPU time 329.19 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 12:58:05 PM PDT 24
Peak memory 201900 kb
Host smart-0d0c21d7-2aed-48fa-a5ea-43bc5b3fd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547955210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.547955210
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2716811432
Short name T784
Test name
Test status
Simulation time 163271083312 ps
CPU time 104.69 seconds
Started Mar 24 12:52:31 PM PDT 24
Finished Mar 24 12:54:16 PM PDT 24
Peak memory 201820 kb
Host smart-899e11fc-9744-4e5b-933e-cd302c360dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716811432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2716811432
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2336660127
Short name T545
Test name
Test status
Simulation time 324177042209 ps
CPU time 784.51 seconds
Started Mar 24 12:52:31 PM PDT 24
Finished Mar 24 01:05:36 PM PDT 24
Peak memory 201916 kb
Host smart-e7e393fc-3da3-47f2-8cb5-649de26b6ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336660127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2336660127
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.497831466
Short name T332
Test name
Test status
Simulation time 329164724022 ps
CPU time 175.07 seconds
Started Mar 24 12:52:33 PM PDT 24
Finished Mar 24 12:55:29 PM PDT 24
Peak memory 201856 kb
Host smart-d06a3b77-3f88-4501-86ef-5de0aa45f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497831466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.497831466
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3308694966
Short name T668
Test name
Test status
Simulation time 492535693297 ps
CPU time 560.16 seconds
Started Mar 24 12:52:34 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 201756 kb
Host smart-61230362-f160-4736-835e-6f549a0dc2c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308694966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3308694966
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2232516780
Short name T254
Test name
Test status
Simulation time 337760059126 ps
CPU time 226.98 seconds
Started Mar 24 12:52:34 PM PDT 24
Finished Mar 24 12:56:21 PM PDT 24
Peak memory 201780 kb
Host smart-7f220fae-cdcc-48de-ac59-418f281630ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232516780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2232516780
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1776033773
Short name T377
Test name
Test status
Simulation time 405561656697 ps
CPU time 927.36 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 01:08:03 PM PDT 24
Peak memory 201760 kb
Host smart-b15e27a3-940a-49d9-ac0c-2afa061ba94d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776033773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1776033773
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2279301998
Short name T412
Test name
Test status
Simulation time 82789120127 ps
CPU time 342.53 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 12:58:18 PM PDT 24
Peak memory 202208 kb
Host smart-c58b715f-bbc2-401c-86f5-9e0707e22553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279301998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2279301998
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1929840583
Short name T455
Test name
Test status
Simulation time 28744785370 ps
CPU time 66.63 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 12:53:42 PM PDT 24
Peak memory 201500 kb
Host smart-34f94848-14ee-404c-9ddc-55df0a45fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929840583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1929840583
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3918431280
Short name T42
Test name
Test status
Simulation time 3547367537 ps
CPU time 1.16 seconds
Started Mar 24 12:52:36 PM PDT 24
Finished Mar 24 12:52:38 PM PDT 24
Peak memory 201516 kb
Host smart-b23c751f-2957-40e9-8e22-fbeed011f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918431280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3918431280
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3173957778
Short name T456
Test name
Test status
Simulation time 5801794659 ps
CPU time 7.71 seconds
Started Mar 24 12:52:35 PM PDT 24
Finished Mar 24 12:52:43 PM PDT 24
Peak memory 201584 kb
Host smart-bd2f3b60-6b87-46e0-a3bc-6d1ce16dae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173957778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3173957778
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.786261443
Short name T760
Test name
Test status
Simulation time 7145029382 ps
CPU time 3.27 seconds
Started Mar 24 12:52:37 PM PDT 24
Finished Mar 24 12:52:40 PM PDT 24
Peak memory 201652 kb
Host smart-da7eecef-2a88-448e-a4a0-84abb802cf55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786261443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
786261443
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1719985331
Short name T611
Test name
Test status
Simulation time 330264769 ps
CPU time 1.51 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:52:55 PM PDT 24
Peak memory 201572 kb
Host smart-e8940465-111c-4a8c-936f-d9406116f9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719985331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1719985331
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2568766118
Short name T745
Test name
Test status
Simulation time 230030183098 ps
CPU time 48.82 seconds
Started Mar 24 12:52:49 PM PDT 24
Finished Mar 24 12:53:38 PM PDT 24
Peak memory 201936 kb
Host smart-a91ae21c-6b91-4d00-aaa4-e982d10568b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568766118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2568766118
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1878604033
Short name T278
Test name
Test status
Simulation time 328608399529 ps
CPU time 78.86 seconds
Started Mar 24 12:52:44 PM PDT 24
Finished Mar 24 12:54:04 PM PDT 24
Peak memory 201856 kb
Host smart-c86f2d58-626d-48bd-bc44-776f8e8560ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878604033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1878604033
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1401849142
Short name T415
Test name
Test status
Simulation time 334457434396 ps
CPU time 826.39 seconds
Started Mar 24 12:52:46 PM PDT 24
Finished Mar 24 01:06:32 PM PDT 24
Peak memory 201836 kb
Host smart-968de560-8e66-44c0-bba3-64ab53a21092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401849142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1401849142
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.146126422
Short name T169
Test name
Test status
Simulation time 497884932937 ps
CPU time 618.58 seconds
Started Mar 24 12:52:45 PM PDT 24
Finished Mar 24 01:03:04 PM PDT 24
Peak memory 201816 kb
Host smart-88bdd694-f719-4d6a-8a0a-9ccc1cee3d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146126422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.146126422
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1214408854
Short name T417
Test name
Test status
Simulation time 497063623842 ps
CPU time 336.53 seconds
Started Mar 24 12:52:47 PM PDT 24
Finished Mar 24 12:58:23 PM PDT 24
Peak memory 201864 kb
Host smart-204b67df-fbff-4acf-acea-9f9fc2cd654e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214408854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1214408854
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1093710084
Short name T532
Test name
Test status
Simulation time 600108377617 ps
CPU time 1320.99 seconds
Started Mar 24 12:52:46 PM PDT 24
Finished Mar 24 01:14:48 PM PDT 24
Peak memory 201812 kb
Host smart-287def90-3351-4736-92b3-23d1159903b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093710084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1093710084
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.635884612
Short name T724
Test name
Test status
Simulation time 135865019734 ps
CPU time 444.28 seconds
Started Mar 24 12:52:48 PM PDT 24
Finished Mar 24 01:00:12 PM PDT 24
Peak memory 202040 kb
Host smart-8513d033-5598-45f0-b5de-fc5c3e903a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635884612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.635884612
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2646331289
Short name T413
Test name
Test status
Simulation time 40593950882 ps
CPU time 23.53 seconds
Started Mar 24 12:52:50 PM PDT 24
Finished Mar 24 12:53:14 PM PDT 24
Peak memory 201560 kb
Host smart-d34e85f9-4f1d-4750-a2bf-55a371786d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646331289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2646331289
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.97614243
Short name T580
Test name
Test status
Simulation time 2703087824 ps
CPU time 2.96 seconds
Started Mar 24 12:52:48 PM PDT 24
Finished Mar 24 12:52:51 PM PDT 24
Peak memory 201576 kb
Host smart-4fa8993f-d00d-43d4-8259-ba620d5c26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97614243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.97614243
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.4250124736
Short name T729
Test name
Test status
Simulation time 5714089219 ps
CPU time 3.99 seconds
Started Mar 24 12:52:47 PM PDT 24
Finished Mar 24 12:52:51 PM PDT 24
Peak memory 201684 kb
Host smart-1ab386e2-1e1d-4d74-bf07-2b1536cd0b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250124736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4250124736
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3797083102
Short name T348
Test name
Test status
Simulation time 24384379689 ps
CPU time 61.38 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:53:55 PM PDT 24
Peak memory 210240 kb
Host smart-becacfcc-f306-4df4-a145-0c2f526dfee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797083102 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3797083102
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2208187787
Short name T131
Test name
Test status
Simulation time 523340149 ps
CPU time 0.7 seconds
Started Mar 24 12:53:07 PM PDT 24
Finished Mar 24 12:53:08 PM PDT 24
Peak memory 201516 kb
Host smart-db5f2a4e-a416-4bc5-9e3c-1e61b54f1bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208187787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2208187787
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2818291702
Short name T716
Test name
Test status
Simulation time 171976902600 ps
CPU time 425.42 seconds
Started Mar 24 12:52:59 PM PDT 24
Finished Mar 24 01:00:04 PM PDT 24
Peak memory 201704 kb
Host smart-1860275a-b94b-486e-b868-6a66972315c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818291702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2818291702
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3714719221
Short name T121
Test name
Test status
Simulation time 340763249425 ps
CPU time 93.05 seconds
Started Mar 24 12:52:59 PM PDT 24
Finished Mar 24 12:54:33 PM PDT 24
Peak memory 201844 kb
Host smart-65297024-3fee-4bd9-8274-df7da5ae0871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714719221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3714719221
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2081230010
Short name T241
Test name
Test status
Simulation time 334902048467 ps
CPU time 806.29 seconds
Started Mar 24 12:52:55 PM PDT 24
Finished Mar 24 01:06:22 PM PDT 24
Peak memory 201892 kb
Host smart-71132e18-9132-4f01-9b1a-59d75dd5fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081230010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2081230010
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3458990541
Short name T374
Test name
Test status
Simulation time 497594533341 ps
CPU time 301.8 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:57:55 PM PDT 24
Peak memory 201868 kb
Host smart-aae37408-2fc9-477c-b0ac-b448cdf10eee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458990541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3458990541
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.582279064
Short name T669
Test name
Test status
Simulation time 326327089008 ps
CPU time 735.52 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 201820 kb
Host smart-0fbd44a1-3663-4633-b611-5cdc44ef685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582279064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.582279064
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2831495578
Short name T11
Test name
Test status
Simulation time 161816703889 ps
CPU time 102.63 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:54:35 PM PDT 24
Peak memory 201948 kb
Host smart-5c7e57fb-ba55-454c-a27b-fcbd075f10c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831495578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2831495578
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3693926797
Short name T177
Test name
Test status
Simulation time 398615074364 ps
CPU time 188.72 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:56:02 PM PDT 24
Peak memory 201880 kb
Host smart-f3cf4acb-f090-428f-8463-dbacdb31f751
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693926797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3693926797
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1485341639
Short name T783
Test name
Test status
Simulation time 197185624219 ps
CPU time 236.56 seconds
Started Mar 24 12:52:53 PM PDT 24
Finished Mar 24 12:56:50 PM PDT 24
Peak memory 201888 kb
Host smart-5249e715-45bb-4354-a4a1-a2b9666edcba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485341639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1485341639
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3203081239
Short name T568
Test name
Test status
Simulation time 78408260809 ps
CPU time 390.44 seconds
Started Mar 24 12:53:03 PM PDT 24
Finished Mar 24 12:59:33 PM PDT 24
Peak memory 202148 kb
Host smart-4b0e1e94-ac14-4d3a-945e-51343fbefc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203081239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3203081239
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.658384589
Short name T685
Test name
Test status
Simulation time 29491007781 ps
CPU time 18.69 seconds
Started Mar 24 12:53:00 PM PDT 24
Finished Mar 24 12:53:19 PM PDT 24
Peak memory 201652 kb
Host smart-822a81a7-2115-4955-937f-2306c20a9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658384589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.658384589
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.868724127
Short name T433
Test name
Test status
Simulation time 5020671294 ps
CPU time 1.91 seconds
Started Mar 24 12:53:00 PM PDT 24
Finished Mar 24 12:53:02 PM PDT 24
Peak memory 201652 kb
Host smart-58bb8f4a-a15e-484e-b052-1f0a69bbb37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868724127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.868724127
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1372026084
Short name T694
Test name
Test status
Simulation time 5599283771 ps
CPU time 4.98 seconds
Started Mar 24 12:52:52 PM PDT 24
Finished Mar 24 12:52:57 PM PDT 24
Peak memory 201664 kb
Host smart-9ca993ab-1cf4-467b-bf05-19bbe51aaec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372026084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1372026084
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1533118707
Short name T337
Test name
Test status
Simulation time 197783125014 ps
CPU time 31.76 seconds
Started Mar 24 12:53:04 PM PDT 24
Finished Mar 24 12:53:36 PM PDT 24
Peak memory 201888 kb
Host smart-39da2cb2-7820-4acb-ab3d-63cf8791ef8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533118707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1533118707
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4164032459
Short name T439
Test name
Test status
Simulation time 451140775 ps
CPU time 1.13 seconds
Started Mar 24 12:53:10 PM PDT 24
Finished Mar 24 12:53:12 PM PDT 24
Peak memory 201512 kb
Host smart-c70a8bd3-d409-4490-a650-9f1c983196be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164032459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4164032459
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.490029316
Short name T250
Test name
Test status
Simulation time 523812106492 ps
CPU time 800.21 seconds
Started Mar 24 12:53:09 PM PDT 24
Finished Mar 24 01:06:30 PM PDT 24
Peak memory 201812 kb
Host smart-986eafad-cfbb-4e3b-ba56-4d01d1cf1f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490029316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.490029316
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3259791884
Short name T480
Test name
Test status
Simulation time 165145890966 ps
CPU time 109.64 seconds
Started Mar 24 12:53:07 PM PDT 24
Finished Mar 24 12:54:56 PM PDT 24
Peak memory 201924 kb
Host smart-ed7fe17d-e866-4e4a-8c68-b6c026b06547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259791884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3259791884
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1615618980
Short name T425
Test name
Test status
Simulation time 490737200884 ps
CPU time 350.73 seconds
Started Mar 24 12:53:09 PM PDT 24
Finished Mar 24 12:59:00 PM PDT 24
Peak memory 201692 kb
Host smart-59aaa2a7-79b6-489e-aeee-e8a35e435123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615618980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1615618980
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1736121800
Short name T697
Test name
Test status
Simulation time 329553107604 ps
CPU time 201.45 seconds
Started Mar 24 12:53:00 PM PDT 24
Finished Mar 24 12:56:22 PM PDT 24
Peak memory 201804 kb
Host smart-43398407-9b3c-49d2-b160-38820b96338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736121800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1736121800
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2287185669
Short name T408
Test name
Test status
Simulation time 497105461005 ps
CPU time 664.18 seconds
Started Mar 24 12:52:59 PM PDT 24
Finished Mar 24 01:04:03 PM PDT 24
Peak memory 201808 kb
Host smart-848fd0e4-d905-4d25-9da7-8fd34f038a70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287185669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2287185669
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2654952947
Short name T107
Test name
Test status
Simulation time 397987595327 ps
CPU time 933.99 seconds
Started Mar 24 12:53:07 PM PDT 24
Finished Mar 24 01:08:41 PM PDT 24
Peak memory 201836 kb
Host smart-b8199d6a-9048-4473-a4c8-a4aaf1d6dff2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654952947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2654952947
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.745932391
Short name T474
Test name
Test status
Simulation time 77764365022 ps
CPU time 280.28 seconds
Started Mar 24 12:53:09 PM PDT 24
Finished Mar 24 12:57:50 PM PDT 24
Peak memory 202112 kb
Host smart-dc09cd0d-cced-4ba8-8f89-52454e80cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745932391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.745932391
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2695313912
Short name T195
Test name
Test status
Simulation time 38683305177 ps
CPU time 84.24 seconds
Started Mar 24 12:53:07 PM PDT 24
Finished Mar 24 12:54:32 PM PDT 24
Peak memory 201624 kb
Host smart-5ca6a110-7580-4faf-ad06-1153e01a85b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695313912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2695313912
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.336524458
Short name T193
Test name
Test status
Simulation time 3633808715 ps
CPU time 3.48 seconds
Started Mar 24 12:53:05 PM PDT 24
Finished Mar 24 12:53:09 PM PDT 24
Peak memory 201536 kb
Host smart-1cbca2c7-9f22-47d8-bb1d-5f11fd8d9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336524458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.336524458
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3203220259
Short name T429
Test name
Test status
Simulation time 5975033124 ps
CPU time 15.52 seconds
Started Mar 24 12:53:04 PM PDT 24
Finished Mar 24 12:53:20 PM PDT 24
Peak memory 201648 kb
Host smart-0464dbf9-4304-4e23-bb70-6eddc479866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203220259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3203220259
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3863360399
Short name T786
Test name
Test status
Simulation time 113153463585 ps
CPU time 305.4 seconds
Started Mar 24 12:53:05 PM PDT 24
Finished Mar 24 12:58:11 PM PDT 24
Peak memory 218388 kb
Host smart-8d06c7df-1047-41fa-a59c-7858eb4e862f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863360399 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3863360399
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1728314634
Short name T400
Test name
Test status
Simulation time 334709109 ps
CPU time 0.97 seconds
Started Mar 24 12:53:23 PM PDT 24
Finished Mar 24 12:53:24 PM PDT 24
Peak memory 201532 kb
Host smart-44bd9596-be0f-477b-803d-c01d8e254057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728314634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1728314634
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3605235922
Short name T180
Test name
Test status
Simulation time 330431767010 ps
CPU time 766.94 seconds
Started Mar 24 12:53:19 PM PDT 24
Finished Mar 24 01:06:06 PM PDT 24
Peak memory 201840 kb
Host smart-a381a004-4845-4a1f-ad14-5001bd6d702b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605235922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3605235922
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2642445572
Short name T324
Test name
Test status
Simulation time 158447377398 ps
CPU time 105.05 seconds
Started Mar 24 12:53:10 PM PDT 24
Finished Mar 24 12:54:55 PM PDT 24
Peak memory 201896 kb
Host smart-ceaf57cd-5975-452a-ab34-61c721fabe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642445572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2642445572
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.643356949
Short name T751
Test name
Test status
Simulation time 328058879959 ps
CPU time 190.38 seconds
Started Mar 24 12:53:11 PM PDT 24
Finished Mar 24 12:56:22 PM PDT 24
Peak memory 201820 kb
Host smart-f6d84713-b0d9-46a8-ac22-13e898e683a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=643356949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.643356949
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3106826889
Short name T216
Test name
Test status
Simulation time 158444992892 ps
CPU time 92.79 seconds
Started Mar 24 12:53:10 PM PDT 24
Finished Mar 24 12:54:43 PM PDT 24
Peak memory 201800 kb
Host smart-a9de290a-5381-46f8-a754-f646bf1638ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106826889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3106826889
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1029083152
Short name T756
Test name
Test status
Simulation time 162034457126 ps
CPU time 94.51 seconds
Started Mar 24 12:53:11 PM PDT 24
Finished Mar 24 12:54:46 PM PDT 24
Peak memory 201852 kb
Host smart-ce175c12-8e96-40b4-b623-387f3ee17156
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029083152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1029083152
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.682963853
Short name T581
Test name
Test status
Simulation time 205653195390 ps
CPU time 246.92 seconds
Started Mar 24 12:53:09 PM PDT 24
Finished Mar 24 12:57:16 PM PDT 24
Peak memory 201804 kb
Host smart-8380a133-8c88-450c-9958-165e34b30571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682963853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.682963853
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3980878258
Short name T167
Test name
Test status
Simulation time 206076576282 ps
CPU time 100.15 seconds
Started Mar 24 12:53:14 PM PDT 24
Finished Mar 24 12:54:55 PM PDT 24
Peak memory 201892 kb
Host smart-38f3c378-2bf4-4fc9-9745-8f71f511ad83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980878258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3980878258
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2555999200
Short name T573
Test name
Test status
Simulation time 94405177771 ps
CPU time 525.87 seconds
Started Mar 24 12:53:16 PM PDT 24
Finished Mar 24 01:02:02 PM PDT 24
Peak memory 202148 kb
Host smart-add465f2-b9a0-4b6a-9db9-bc2a822638f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555999200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2555999200
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3833113647
Short name T515
Test name
Test status
Simulation time 24509644371 ps
CPU time 15 seconds
Started Mar 24 12:53:19 PM PDT 24
Finished Mar 24 12:53:34 PM PDT 24
Peak memory 201540 kb
Host smart-23248c98-a029-4f47-a48f-6f7b5e290b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833113647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3833113647
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1427706112
Short name T479
Test name
Test status
Simulation time 4407499409 ps
CPU time 3.52 seconds
Started Mar 24 12:53:19 PM PDT 24
Finished Mar 24 12:53:23 PM PDT 24
Peak memory 201520 kb
Host smart-9cbeaf1d-459d-472a-a4e9-e3521199bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427706112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1427706112
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2911141313
Short name T757
Test name
Test status
Simulation time 5865372314 ps
CPU time 2.24 seconds
Started Mar 24 12:53:09 PM PDT 24
Finished Mar 24 12:53:12 PM PDT 24
Peak memory 201532 kb
Host smart-5f224e24-542f-40c4-976f-d4b96142ffbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911141313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2911141313
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1928341778
Short name T234
Test name
Test status
Simulation time 228801799576 ps
CPU time 432.88 seconds
Started Mar 24 12:53:15 PM PDT 24
Finished Mar 24 01:00:29 PM PDT 24
Peak memory 202100 kb
Host smart-c32b843d-7c74-415f-99f9-f16d0d5285a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928341778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1928341778
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4150091719
Short name T17
Test name
Test status
Simulation time 297482111742 ps
CPU time 520.39 seconds
Started Mar 24 12:53:18 PM PDT 24
Finished Mar 24 01:01:59 PM PDT 24
Peak memory 210496 kb
Host smart-1fe484c2-08fc-4ee4-8fed-6aadb8c9062e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150091719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4150091719
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2898302124
Short name T536
Test name
Test status
Simulation time 317818720 ps
CPU time 0.8 seconds
Started Mar 24 12:53:29 PM PDT 24
Finished Mar 24 12:53:31 PM PDT 24
Peak memory 201152 kb
Host smart-b36d8d8d-44a1-473d-9b1e-7c695df0371e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898302124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2898302124
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2843905783
Short name T792
Test name
Test status
Simulation time 503629954967 ps
CPU time 556.46 seconds
Started Mar 24 12:53:27 PM PDT 24
Finished Mar 24 01:02:44 PM PDT 24
Peak memory 201832 kb
Host smart-290798fb-9525-4f20-a562-8b053f78c02a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843905783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2843905783
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3532006491
Short name T534
Test name
Test status
Simulation time 161082901642 ps
CPU time 396.79 seconds
Started Mar 24 12:53:26 PM PDT 24
Finished Mar 24 01:00:03 PM PDT 24
Peak memory 201764 kb
Host smart-51fb218f-72da-4f42-928b-f277481fb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532006491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3532006491
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2836320211
Short name T773
Test name
Test status
Simulation time 159725035037 ps
CPU time 366.59 seconds
Started Mar 24 12:53:21 PM PDT 24
Finished Mar 24 12:59:28 PM PDT 24
Peak memory 201912 kb
Host smart-ff7639ee-8643-491d-acf6-adacb732a6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836320211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2836320211
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1182720117
Short name T116
Test name
Test status
Simulation time 166869465205 ps
CPU time 413.06 seconds
Started Mar 24 12:53:21 PM PDT 24
Finished Mar 24 01:00:14 PM PDT 24
Peak memory 201820 kb
Host smart-d534043e-1bf6-4247-ba41-7b6bec5be622
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182720117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1182720117
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2732076604
Short name T421
Test name
Test status
Simulation time 162066404658 ps
CPU time 180.4 seconds
Started Mar 24 12:53:22 PM PDT 24
Finished Mar 24 12:56:22 PM PDT 24
Peak memory 201440 kb
Host smart-a56f5c86-c615-479c-ae9f-efe054aaadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732076604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2732076604
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.279101401
Short name T557
Test name
Test status
Simulation time 164709668996 ps
CPU time 364.53 seconds
Started Mar 24 12:53:22 PM PDT 24
Finished Mar 24 12:59:27 PM PDT 24
Peak memory 201428 kb
Host smart-c541521d-3b7f-4531-a266-e49776d6eb40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279101401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.279101401
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.694901348
Short name T691
Test name
Test status
Simulation time 576399103626 ps
CPU time 393.49 seconds
Started Mar 24 12:53:20 PM PDT 24
Finished Mar 24 12:59:53 PM PDT 24
Peak memory 201876 kb
Host smart-951579b3-d30b-4d42-a3ef-f46717e2e088
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694901348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.694901348
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.538338248
Short name T525
Test name
Test status
Simulation time 199256253912 ps
CPU time 517.73 seconds
Started Mar 24 12:53:20 PM PDT 24
Finished Mar 24 01:01:58 PM PDT 24
Peak memory 201844 kb
Host smart-6c42cf5e-11d2-4132-8b0a-ea3b55dbd51b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538338248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.538338248
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2114474522
Short name T770
Test name
Test status
Simulation time 65463072288 ps
CPU time 235.47 seconds
Started Mar 24 12:53:25 PM PDT 24
Finished Mar 24 12:57:20 PM PDT 24
Peak memory 202216 kb
Host smart-cfc30c42-5b7e-402d-808c-a0d96f0f9d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114474522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2114474522
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2209671227
Short name T431
Test name
Test status
Simulation time 42784670673 ps
CPU time 48.27 seconds
Started Mar 24 12:53:27 PM PDT 24
Finished Mar 24 12:54:15 PM PDT 24
Peak memory 201616 kb
Host smart-6a5a9d87-c753-4dae-8bcc-cd39ec588419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209671227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2209671227
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1179572175
Short name T500
Test name
Test status
Simulation time 3680639451 ps
CPU time 10.2 seconds
Started Mar 24 12:53:31 PM PDT 24
Finished Mar 24 12:53:41 PM PDT 24
Peak memory 201448 kb
Host smart-ff4572c5-07a2-4dcf-bc9a-e7484638d1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179572175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1179572175
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.503525172
Short name T437
Test name
Test status
Simulation time 5989729173 ps
CPU time 4.54 seconds
Started Mar 24 12:53:21 PM PDT 24
Finished Mar 24 12:53:26 PM PDT 24
Peak memory 201652 kb
Host smart-b83527ec-e435-44c4-8bb5-3c3101e9d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503525172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.503525172
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1760594908
Short name T274
Test name
Test status
Simulation time 454968280367 ps
CPU time 1034.61 seconds
Started Mar 24 12:53:24 PM PDT 24
Finished Mar 24 01:10:39 PM PDT 24
Peak memory 201920 kb
Host smart-fe0a9748-263e-4fd3-a9ef-8e45e44a6aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760594908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1760594908
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2189270288
Short name T81
Test name
Test status
Simulation time 182559398490 ps
CPU time 226.58 seconds
Started Mar 24 12:53:27 PM PDT 24
Finished Mar 24 12:57:14 PM PDT 24
Peak memory 210580 kb
Host smart-1f84e5db-5652-471b-8994-1106b8acd4a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189270288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2189270288
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3970762834
Short name T527
Test name
Test status
Simulation time 456241115 ps
CPU time 0.86 seconds
Started Mar 24 12:53:36 PM PDT 24
Finished Mar 24 12:53:37 PM PDT 24
Peak memory 201508 kb
Host smart-656c413b-eaef-4328-b55f-1786373a8077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970762834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3970762834
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4174918884
Short name T719
Test name
Test status
Simulation time 170831868260 ps
CPU time 411.92 seconds
Started Mar 24 12:53:32 PM PDT 24
Finished Mar 24 01:00:24 PM PDT 24
Peak memory 201920 kb
Host smart-4279b863-e45f-414b-a88b-71a2be1c0f1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174918884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4174918884
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.181371828
Short name T583
Test name
Test status
Simulation time 492944832033 ps
CPU time 312.19 seconds
Started Mar 24 12:53:35 PM PDT 24
Finished Mar 24 12:58:47 PM PDT 24
Peak memory 201788 kb
Host smart-27b8ef95-894a-467c-8d97-d76684ed4491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181371828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.181371828
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1361246680
Short name T513
Test name
Test status
Simulation time 168025467876 ps
CPU time 415.19 seconds
Started Mar 24 12:53:30 PM PDT 24
Finished Mar 24 01:00:25 PM PDT 24
Peak memory 201424 kb
Host smart-6c012d26-d24a-4a6b-a932-87b6ef4d14a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361246680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1361246680
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3922070978
Short name T61
Test name
Test status
Simulation time 491917495979 ps
CPU time 1102.48 seconds
Started Mar 24 12:53:25 PM PDT 24
Finished Mar 24 01:11:48 PM PDT 24
Peak memory 201728 kb
Host smart-ea547fe5-cac7-421e-bb5d-6ffebb607556
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922070978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3922070978
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1178175495
Short name T775
Test name
Test status
Simulation time 494604000502 ps
CPU time 151.77 seconds
Started Mar 24 12:53:30 PM PDT 24
Finished Mar 24 12:56:02 PM PDT 24
Peak memory 201708 kb
Host smart-9881a9c7-28de-4348-b026-7a6c0bd1638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178175495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1178175495
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2929837272
Short name T405
Test name
Test status
Simulation time 492585023886 ps
CPU time 544.03 seconds
Started Mar 24 12:53:26 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 201800 kb
Host smart-e1e86cec-91b5-494f-8a20-675ea41e4bc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929837272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2929837272
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1533410345
Short name T720
Test name
Test status
Simulation time 587383026538 ps
CPU time 1470.66 seconds
Started Mar 24 12:53:31 PM PDT 24
Finished Mar 24 01:18:02 PM PDT 24
Peak memory 201952 kb
Host smart-c5399e0f-c9cc-48eb-a437-634452a5b702
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533410345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1533410345
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2250461191
Short name T440
Test name
Test status
Simulation time 106372175441 ps
CPU time 407.78 seconds
Started Mar 24 12:53:32 PM PDT 24
Finished Mar 24 01:00:20 PM PDT 24
Peak memory 202208 kb
Host smart-91a1b859-8059-4065-a6a6-ea2b5e88061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250461191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2250461191
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1508528607
Short name T407
Test name
Test status
Simulation time 37789809606 ps
CPU time 12.5 seconds
Started Mar 24 12:53:30 PM PDT 24
Finished Mar 24 12:53:43 PM PDT 24
Peak memory 201500 kb
Host smart-9c296c71-e358-4a8f-b8e1-f8d413ab7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508528607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1508528607
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3357432404
Short name T599
Test name
Test status
Simulation time 4266838507 ps
CPU time 2 seconds
Started Mar 24 12:53:31 PM PDT 24
Finished Mar 24 12:53:33 PM PDT 24
Peak memory 201880 kb
Host smart-0f4ec480-801b-4e41-ab6a-3e8e51fcd7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357432404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3357432404
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2687071104
Short name T593
Test name
Test status
Simulation time 5585800325 ps
CPU time 13.12 seconds
Started Mar 24 12:53:24 PM PDT 24
Finished Mar 24 12:53:37 PM PDT 24
Peak memory 201636 kb
Host smart-5a771b6c-431b-4c44-8e05-c5fefd30f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687071104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2687071104
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4211128413
Short name T613
Test name
Test status
Simulation time 110036763020 ps
CPU time 182.84 seconds
Started Mar 24 12:53:36 PM PDT 24
Finished Mar 24 12:56:39 PM PDT 24
Peak memory 210244 kb
Host smart-b8d38156-73ab-49ae-8faf-b4f6ae7083e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211128413 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4211128413
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3724056651
Short name T448
Test name
Test status
Simulation time 520937255 ps
CPU time 0.95 seconds
Started Mar 24 12:53:43 PM PDT 24
Finished Mar 24 12:53:44 PM PDT 24
Peak memory 201568 kb
Host smart-eab44126-6ecd-4ac5-b216-fee8ef9c6127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724056651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3724056651
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1000312171
Short name T122
Test name
Test status
Simulation time 195721564562 ps
CPU time 109.63 seconds
Started Mar 24 12:53:35 PM PDT 24
Finished Mar 24 12:55:24 PM PDT 24
Peak memory 201856 kb
Host smart-1cf55db3-bac1-4c45-8554-78f79fe9ca91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000312171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1000312171
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1831099441
Short name T264
Test name
Test status
Simulation time 172818879041 ps
CPU time 431.07 seconds
Started Mar 24 12:53:36 PM PDT 24
Finished Mar 24 01:00:47 PM PDT 24
Peak memory 201896 kb
Host smart-5d57afbf-d22b-4282-b738-2d8475aa566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831099441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1831099441
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3042443265
Short name T509
Test name
Test status
Simulation time 164168891477 ps
CPU time 103.6 seconds
Started Mar 24 12:53:37 PM PDT 24
Finished Mar 24 12:55:20 PM PDT 24
Peak memory 201736 kb
Host smart-7f5cc7e0-485b-44f5-a251-ddc0c31efd8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042443265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3042443265
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2492946322
Short name T688
Test name
Test status
Simulation time 164581489426 ps
CPU time 353.96 seconds
Started Mar 24 12:53:37 PM PDT 24
Finished Mar 24 12:59:31 PM PDT 24
Peak memory 201928 kb
Host smart-51d6bfe7-8276-4da9-900b-709f41513fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492946322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2492946322
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.4135068192
Short name T495
Test name
Test status
Simulation time 492060691185 ps
CPU time 218.03 seconds
Started Mar 24 12:53:37 PM PDT 24
Finished Mar 24 12:57:15 PM PDT 24
Peak memory 201764 kb
Host smart-16c053cc-f520-415d-97f2-beb590047aeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135068192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.4135068192
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1783495814
Short name T424
Test name
Test status
Simulation time 207014876124 ps
CPU time 460.91 seconds
Started Mar 24 12:53:35 PM PDT 24
Finished Mar 24 01:01:16 PM PDT 24
Peak memory 201836 kb
Host smart-e5e664fd-577f-4069-9086-84c8acdff888
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783495814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1783495814
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2631459146
Short name T362
Test name
Test status
Simulation time 136705919719 ps
CPU time 477.8 seconds
Started Mar 24 12:53:42 PM PDT 24
Finished Mar 24 01:01:41 PM PDT 24
Peak memory 202160 kb
Host smart-e8e62e15-1a53-416c-9fb3-4ea1fcb20bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631459146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2631459146
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2866289628
Short name T696
Test name
Test status
Simulation time 43994462397 ps
CPU time 32.5 seconds
Started Mar 24 12:53:42 PM PDT 24
Finished Mar 24 12:54:16 PM PDT 24
Peak memory 201632 kb
Host smart-cf6b22cd-4d01-4815-b2cc-3d67070f104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866289628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2866289628
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1958524518
Short name T621
Test name
Test status
Simulation time 3673381434 ps
CPU time 4.52 seconds
Started Mar 24 12:53:42 PM PDT 24
Finished Mar 24 12:53:47 PM PDT 24
Peak memory 201528 kb
Host smart-b962ecda-3845-46b7-94e3-2e28103beb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958524518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1958524518
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3521643022
Short name T561
Test name
Test status
Simulation time 5816278860 ps
CPU time 8.54 seconds
Started Mar 24 12:53:34 PM PDT 24
Finished Mar 24 12:53:42 PM PDT 24
Peak memory 201684 kb
Host smart-602a539c-7237-4ed2-9b48-6af7d0809065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521643022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3521643022
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.749311770
Short name T768
Test name
Test status
Simulation time 208676570830 ps
CPU time 183.35 seconds
Started Mar 24 12:53:44 PM PDT 24
Finished Mar 24 12:56:48 PM PDT 24
Peak memory 201704 kb
Host smart-9f80372d-6347-4a87-9368-2d17b7dbe64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749311770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
749311770
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3584675396
Short name T47
Test name
Test status
Simulation time 311945244591 ps
CPU time 246.58 seconds
Started Mar 24 12:53:42 PM PDT 24
Finished Mar 24 12:57:49 PM PDT 24
Peak memory 218968 kb
Host smart-6393f591-535e-413d-b032-b7797e99d20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584675396 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3584675396
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2345282331
Short name T385
Test name
Test status
Simulation time 344534314 ps
CPU time 0.81 seconds
Started Mar 24 12:53:51 PM PDT 24
Finished Mar 24 12:53:52 PM PDT 24
Peak memory 201516 kb
Host smart-30f63423-20fd-4d62-9533-ba9624cf86e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345282331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2345282331
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3356515750
Short name T595
Test name
Test status
Simulation time 165390118909 ps
CPU time 358.9 seconds
Started Mar 24 12:53:50 PM PDT 24
Finished Mar 24 12:59:49 PM PDT 24
Peak memory 201940 kb
Host smart-772fcfa6-1a4a-42a1-a604-029dc87b2344
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356515750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3356515750
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1195260402
Short name T312
Test name
Test status
Simulation time 483972494912 ps
CPU time 576.5 seconds
Started Mar 24 12:53:52 PM PDT 24
Finished Mar 24 01:03:28 PM PDT 24
Peak memory 201912 kb
Host smart-488d965d-ce27-41b4-bde3-29eb1bf238ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195260402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1195260402
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2093973412
Short name T189
Test name
Test status
Simulation time 327957682227 ps
CPU time 192.55 seconds
Started Mar 24 12:53:46 PM PDT 24
Finished Mar 24 12:56:59 PM PDT 24
Peak memory 201896 kb
Host smart-9781fc6a-f774-4ab3-86a6-f31281b73bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093973412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2093973412
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.206287434
Short name T463
Test name
Test status
Simulation time 162979106623 ps
CPU time 387.79 seconds
Started Mar 24 12:53:46 PM PDT 24
Finished Mar 24 01:00:14 PM PDT 24
Peak memory 201820 kb
Host smart-1a34ce3a-fd17-46c5-9679-2358ddd216bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=206287434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.206287434
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1944167530
Short name T687
Test name
Test status
Simulation time 490584408258 ps
CPU time 265.87 seconds
Started Mar 24 12:53:47 PM PDT 24
Finished Mar 24 12:58:13 PM PDT 24
Peak memory 201820 kb
Host smart-1dc71dd7-4b18-4593-aae6-ea093ff54d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944167530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1944167530
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2747794195
Short name T582
Test name
Test status
Simulation time 497221986563 ps
CPU time 553.84 seconds
Started Mar 24 12:53:49 PM PDT 24
Finished Mar 24 01:03:03 PM PDT 24
Peak memory 201912 kb
Host smart-8f808c2c-a61d-4a9e-9f6c-d6e4dd08bd58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747794195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2747794195
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1785364168
Short name T741
Test name
Test status
Simulation time 673262518632 ps
CPU time 393.89 seconds
Started Mar 24 12:53:47 PM PDT 24
Finished Mar 24 01:00:22 PM PDT 24
Peak memory 201900 kb
Host smart-f38ef272-d84c-4544-a63d-543a3b4d9e0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785364168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1785364168
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.447259353
Short name T132
Test name
Test status
Simulation time 598364285871 ps
CPU time 1523.53 seconds
Started Mar 24 12:53:51 PM PDT 24
Finished Mar 24 01:19:15 PM PDT 24
Peak memory 202080 kb
Host smart-a37983a7-d923-4d9e-b19f-a39e287f9c96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447259353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.447259353
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3852407129
Short name T192
Test name
Test status
Simulation time 120227228362 ps
CPU time 447.57 seconds
Started Mar 24 12:53:50 PM PDT 24
Finished Mar 24 01:01:18 PM PDT 24
Peak memory 202252 kb
Host smart-cd27ed83-e45d-46c1-a072-4fc779cc1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852407129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3852407129
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4264336303
Short name T603
Test name
Test status
Simulation time 29821266792 ps
CPU time 19.64 seconds
Started Mar 24 12:53:51 PM PDT 24
Finished Mar 24 12:54:10 PM PDT 24
Peak memory 201656 kb
Host smart-b5ca5b95-f804-4dd6-9ef9-7d02d299813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264336303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4264336303
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1229033632
Short name T626
Test name
Test status
Simulation time 4245856035 ps
CPU time 10.82 seconds
Started Mar 24 12:53:50 PM PDT 24
Finished Mar 24 12:54:01 PM PDT 24
Peak memory 201612 kb
Host smart-142b7534-d8f9-44cd-af7b-7ee1bdaba81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229033632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1229033632
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3672694683
Short name T467
Test name
Test status
Simulation time 5904300651 ps
CPU time 7.73 seconds
Started Mar 24 12:53:46 PM PDT 24
Finished Mar 24 12:53:54 PM PDT 24
Peak memory 201632 kb
Host smart-4c221b59-5e29-40f0-ba2c-c56768cb250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672694683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3672694683
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.624518117
Short name T80
Test name
Test status
Simulation time 126443752649 ps
CPU time 104.26 seconds
Started Mar 24 12:53:51 PM PDT 24
Finished Mar 24 12:55:36 PM PDT 24
Peak memory 217912 kb
Host smart-be244bc5-2cfa-47fb-97c3-04d2f2f11bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624518117 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.624518117
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2816775360
Short name T743
Test name
Test status
Simulation time 531442240 ps
CPU time 1.82 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:20 PM PDT 24
Peak memory 201492 kb
Host smart-9eee4170-dc29-4bb8-af9f-358860c3cf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816775360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2816775360
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1035657444
Short name T678
Test name
Test status
Simulation time 502469093087 ps
CPU time 372.13 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:56:42 PM PDT 24
Peak memory 201796 kb
Host smart-730a2abc-f651-488e-a9b4-6382294079fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035657444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1035657444
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.423067708
Short name T630
Test name
Test status
Simulation time 370589370008 ps
CPU time 448.72 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:57:53 PM PDT 24
Peak memory 201792 kb
Host smart-14d8b2fb-19d3-40d6-a961-aa8af83e5ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423067708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.423067708
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3770562419
Short name T295
Test name
Test status
Simulation time 489533503099 ps
CPU time 311.02 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:55:35 PM PDT 24
Peak memory 201800 kb
Host smart-e06eeb30-733f-4c3f-87e1-b9062874be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770562419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3770562419
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2063118566
Short name T610
Test name
Test status
Simulation time 483861972183 ps
CPU time 191.37 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:53:40 PM PDT 24
Peak memory 201856 kb
Host smart-f877d811-4e21-4e61-a991-bc546be013ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063118566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2063118566
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.10937598
Short name T684
Test name
Test status
Simulation time 328805023408 ps
CPU time 773.83 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 01:03:23 PM PDT 24
Peak memory 201740 kb
Host smart-c2e68731-a000-4844-b9f2-796fc9e4ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10937598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.10937598
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1801807603
Short name T22
Test name
Test status
Simulation time 496834188020 ps
CPU time 291.57 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:55:16 PM PDT 24
Peak memory 201800 kb
Host smart-a4fa9320-4eda-48a7-8dba-b84c2f4e4907
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801807603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1801807603
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3942410752
Short name T518
Test name
Test status
Simulation time 346099882893 ps
CPU time 127.61 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:52:32 PM PDT 24
Peak memory 201892 kb
Host smart-a435cc88-5bfd-45a3-adde-ac2c0356b838
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942410752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3942410752
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4163479014
Short name T379
Test name
Test status
Simulation time 213048314188 ps
CPU time 500.13 seconds
Started Mar 24 12:50:16 PM PDT 24
Finished Mar 24 12:58:37 PM PDT 24
Peak memory 201912 kb
Host smart-f2458101-f233-47ba-bb7f-706f2171b97c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163479014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4163479014
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1122276852
Short name T660
Test name
Test status
Simulation time 67821957637 ps
CPU time 336.53 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:56:01 PM PDT 24
Peak memory 202068 kb
Host smart-3812dca6-bc05-4113-8753-a6e1e2e44b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122276852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1122276852
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4243469812
Short name T761
Test name
Test status
Simulation time 21867687534 ps
CPU time 24.27 seconds
Started Mar 24 12:50:17 PM PDT 24
Finished Mar 24 12:50:43 PM PDT 24
Peak memory 201676 kb
Host smart-4ab55c09-a442-4c51-bd2b-d8f4696a284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243469812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4243469812
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3533757025
Short name T438
Test name
Test status
Simulation time 3581796662 ps
CPU time 3.11 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 201540 kb
Host smart-9c698fa6-44b9-4b97-9f66-da59594233b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533757025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3533757025
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3080942609
Short name T82
Test name
Test status
Simulation time 8595220898 ps
CPU time 6.02 seconds
Started Mar 24 12:50:29 PM PDT 24
Finished Mar 24 12:50:35 PM PDT 24
Peak memory 217488 kb
Host smart-2ce69e31-96c8-4ecd-a9cc-6d417335469d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080942609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3080942609
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.949357108
Short name T430
Test name
Test status
Simulation time 5783337633 ps
CPU time 14 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:35 PM PDT 24
Peak memory 201680 kb
Host smart-bca613a9-f111-41b8-b198-dce88ad802c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949357108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.949357108
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2876797049
Short name T279
Test name
Test status
Simulation time 175819280080 ps
CPU time 226.62 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:54:13 PM PDT 24
Peak memory 201804 kb
Host smart-c7998203-416b-4dfb-81e4-b2f8f3f027bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876797049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2876797049
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2181071253
Short name T641
Test name
Test status
Simulation time 214270948266 ps
CPU time 117.79 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:52:28 PM PDT 24
Peak memory 202268 kb
Host smart-0478ee76-459e-4b44-b3c1-0b2ef59a935a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181071253 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2181071253
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3822694186
Short name T680
Test name
Test status
Simulation time 480079525 ps
CPU time 1.72 seconds
Started Mar 24 12:54:04 PM PDT 24
Finished Mar 24 12:54:05 PM PDT 24
Peak memory 201532 kb
Host smart-aa324a8d-5386-4367-a91e-9d46c3dc1cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822694186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3822694186
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.380868062
Short name T270
Test name
Test status
Simulation time 180776703133 ps
CPU time 381.72 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 01:00:19 PM PDT 24
Peak memory 201928 kb
Host smart-e9d26c27-266a-4c16-816b-6e066021a092
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380868062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.380868062
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3883792837
Short name T650
Test name
Test status
Simulation time 378571245744 ps
CPU time 227.01 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 12:57:44 PM PDT 24
Peak memory 201844 kb
Host smart-49d0dc77-7a35-4b66-ae6b-7843a67cb01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883792837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3883792837
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.249263762
Short name T353
Test name
Test status
Simulation time 493212429969 ps
CPU time 1171.93 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 01:13:29 PM PDT 24
Peak memory 201928 kb
Host smart-3c6ef0b2-47c2-4f1a-b681-e98e13f2c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249263762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.249263762
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.553426882
Short name T367
Test name
Test status
Simulation time 336372200373 ps
CPU time 795.18 seconds
Started Mar 24 12:53:58 PM PDT 24
Finished Mar 24 01:07:13 PM PDT 24
Peak memory 201764 kb
Host smart-6ae53400-e09e-4175-9fb6-e82b069f37ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=553426882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.553426882
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3421473650
Short name T183
Test name
Test status
Simulation time 332541208792 ps
CPU time 44.14 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 12:54:42 PM PDT 24
Peak memory 201852 kb
Host smart-c4636ad1-fd8a-44b8-969f-5f02f0032597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421473650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3421473650
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.489314754
Short name T677
Test name
Test status
Simulation time 484753490349 ps
CPU time 1085.52 seconds
Started Mar 24 12:53:58 PM PDT 24
Finished Mar 24 01:12:03 PM PDT 24
Peak memory 201716 kb
Host smart-2889b133-b1f6-49f9-b932-6dfa9f2c3644
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489314754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.489314754
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.779475636
Short name T338
Test name
Test status
Simulation time 169500853399 ps
CPU time 29.08 seconds
Started Mar 24 12:53:58 PM PDT 24
Finished Mar 24 12:54:27 PM PDT 24
Peak memory 201828 kb
Host smart-e987728d-f910-4a8d-ab1e-e03c0c47d62b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779475636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.779475636
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1720412700
Short name T487
Test name
Test status
Simulation time 591506486296 ps
CPU time 1463.35 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 01:18:20 PM PDT 24
Peak memory 201824 kb
Host smart-f3ac27e7-0c6d-462e-85f7-5bb8e70adeed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720412700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1720412700
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2261652871
Short name T41
Test name
Test status
Simulation time 89280313050 ps
CPU time 310.65 seconds
Started Mar 24 12:54:04 PM PDT 24
Finished Mar 24 12:59:15 PM PDT 24
Peak memory 202124 kb
Host smart-3d7fb6eb-0879-4375-9bb1-0758a0ce85e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261652871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2261652871
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3195077616
Short name T670
Test name
Test status
Simulation time 25666611029 ps
CPU time 35.58 seconds
Started Mar 24 12:53:57 PM PDT 24
Finished Mar 24 12:54:33 PM PDT 24
Peak memory 201640 kb
Host smart-1739ce8f-4b02-4141-bb91-e3ae2297078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195077616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3195077616
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1984309953
Short name T618
Test name
Test status
Simulation time 5384046585 ps
CPU time 3.67 seconds
Started Mar 24 12:53:56 PM PDT 24
Finished Mar 24 12:54:00 PM PDT 24
Peak memory 201680 kb
Host smart-878a2bc0-fc02-42ca-ad6c-b0492a96c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984309953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1984309953
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1218286099
Short name T402
Test name
Test status
Simulation time 5781127670 ps
CPU time 13.73 seconds
Started Mar 24 12:53:52 PM PDT 24
Finished Mar 24 12:54:05 PM PDT 24
Peak memory 201540 kb
Host smart-276982e2-cd0c-4958-83ea-c0f7cc9cfb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218286099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1218286099
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.640937241
Short name T321
Test name
Test status
Simulation time 181153892521 ps
CPU time 106.21 seconds
Started Mar 24 12:54:04 PM PDT 24
Finished Mar 24 12:55:51 PM PDT 24
Peak memory 201832 kb
Host smart-603da13c-27a8-45e0-9341-615c7c1d307d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640937241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
640937241
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.32752122
Short name T217
Test name
Test status
Simulation time 278499320109 ps
CPU time 109.71 seconds
Started Mar 24 12:54:03 PM PDT 24
Finished Mar 24 12:55:53 PM PDT 24
Peak memory 218648 kb
Host smart-e024fe2e-8cc4-4d61-8350-216b2dde4493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32752122 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.32752122
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4046791419
Short name T422
Test name
Test status
Simulation time 476333753 ps
CPU time 0.9 seconds
Started Mar 24 12:54:16 PM PDT 24
Finished Mar 24 12:54:18 PM PDT 24
Peak memory 201532 kb
Host smart-33b60be8-c483-4717-8137-2e733b184c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046791419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4046791419
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2892218454
Short name T296
Test name
Test status
Simulation time 273651062874 ps
CPU time 428.33 seconds
Started Mar 24 12:54:15 PM PDT 24
Finished Mar 24 01:01:23 PM PDT 24
Peak memory 201872 kb
Host smart-fa63b4e5-d040-4351-a2de-24c34eb24269
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892218454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2892218454
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2246487656
Short name T782
Test name
Test status
Simulation time 491731620161 ps
CPU time 320.45 seconds
Started Mar 24 12:54:09 PM PDT 24
Finished Mar 24 12:59:29 PM PDT 24
Peak memory 201916 kb
Host smart-e03f6934-6781-4958-ac95-2e5e1d056d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246487656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2246487656
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2165676876
Short name T27
Test name
Test status
Simulation time 164384904611 ps
CPU time 372.78 seconds
Started Mar 24 12:54:14 PM PDT 24
Finished Mar 24 01:00:27 PM PDT 24
Peak memory 201808 kb
Host smart-eddd8ac6-9206-4945-8411-715164dc3d37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165676876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2165676876
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3188473741
Short name T470
Test name
Test status
Simulation time 170393774381 ps
CPU time 367.48 seconds
Started Mar 24 12:54:10 PM PDT 24
Finished Mar 24 01:00:18 PM PDT 24
Peak memory 201808 kb
Host smart-374e66d4-4079-43cc-a48c-7e91d9568edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188473741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3188473741
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2796935160
Short name T791
Test name
Test status
Simulation time 330586828284 ps
CPU time 368.13 seconds
Started Mar 24 12:54:09 PM PDT 24
Finished Mar 24 01:00:17 PM PDT 24
Peak memory 201708 kb
Host smart-dd07e84b-42ca-40eb-abed-eabf5d1e6300
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796935160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2796935160
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4057998338
Short name T125
Test name
Test status
Simulation time 402091736090 ps
CPU time 781.83 seconds
Started Mar 24 12:54:17 PM PDT 24
Finished Mar 24 01:07:19 PM PDT 24
Peak memory 201844 kb
Host smart-ba584972-9133-4546-b44f-e417e1da61f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057998338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4057998338
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1867561097
Short name T106
Test name
Test status
Simulation time 82957144281 ps
CPU time 393 seconds
Started Mar 24 12:54:14 PM PDT 24
Finished Mar 24 01:00:48 PM PDT 24
Peak memory 202228 kb
Host smart-4770eae1-94f7-4d3a-9cc4-91b86003dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867561097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1867561097
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1949567553
Short name T795
Test name
Test status
Simulation time 37798933098 ps
CPU time 87.94 seconds
Started Mar 24 12:54:12 PM PDT 24
Finished Mar 24 12:55:40 PM PDT 24
Peak memory 201628 kb
Host smart-547bb7ad-92a2-4d38-8f10-0085bde1cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949567553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1949567553
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1673656127
Short name T523
Test name
Test status
Simulation time 3203086998 ps
CPU time 7.94 seconds
Started Mar 24 12:54:15 PM PDT 24
Finished Mar 24 12:54:23 PM PDT 24
Peak memory 201568 kb
Host smart-66ddc711-1e7a-4cfa-b480-fa3c7a71aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673656127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1673656127
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1818800831
Short name T627
Test name
Test status
Simulation time 5980397106 ps
CPU time 15.18 seconds
Started Mar 24 12:54:11 PM PDT 24
Finished Mar 24 12:54:26 PM PDT 24
Peak memory 201636 kb
Host smart-1103f851-5bb5-4198-9513-41940cdbf345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818800831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1818800831
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.168958040
Short name T643
Test name
Test status
Simulation time 280448187563 ps
CPU time 301.85 seconds
Started Mar 24 12:54:17 PM PDT 24
Finished Mar 24 12:59:19 PM PDT 24
Peak memory 210376 kb
Host smart-27918b9e-6f77-4842-94b5-3d58e1270e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168958040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
168958040
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2155704101
Short name T781
Test name
Test status
Simulation time 72091823812 ps
CPU time 159.27 seconds
Started Mar 24 12:54:15 PM PDT 24
Finished Mar 24 12:56:55 PM PDT 24
Peak memory 210124 kb
Host smart-666f20bb-bf1d-46e0-9241-c3d6a292e05c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155704101 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2155704101
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2002589724
Short name T488
Test name
Test status
Simulation time 533077790 ps
CPU time 1.91 seconds
Started Mar 24 12:54:23 PM PDT 24
Finished Mar 24 12:54:25 PM PDT 24
Peak memory 201548 kb
Host smart-65f7ce1f-a34e-49e2-9e85-0cc51a07740f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002589724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2002589724
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1804218907
Short name T538
Test name
Test status
Simulation time 192136276210 ps
CPU time 232.68 seconds
Started Mar 24 12:54:22 PM PDT 24
Finished Mar 24 12:58:15 PM PDT 24
Peak memory 201704 kb
Host smart-9d85d9aa-e0e9-401e-9b19-0dd4a28362e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804218907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1804218907
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3576452629
Short name T707
Test name
Test status
Simulation time 162931606156 ps
CPU time 385.82 seconds
Started Mar 24 12:54:13 PM PDT 24
Finished Mar 24 01:00:39 PM PDT 24
Peak memory 201868 kb
Host smart-db9c1e09-55c3-48b3-b14a-2094b30ac2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576452629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3576452629
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1195975659
Short name T717
Test name
Test status
Simulation time 163751178883 ps
CPU time 400.13 seconds
Started Mar 24 12:54:14 PM PDT 24
Finished Mar 24 01:00:54 PM PDT 24
Peak memory 201796 kb
Host smart-d1d024b2-db3f-415e-a8e5-f93e89fa35ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195975659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1195975659
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1238812299
Short name T435
Test name
Test status
Simulation time 480608718298 ps
CPU time 286.3 seconds
Started Mar 24 12:54:17 PM PDT 24
Finished Mar 24 12:59:04 PM PDT 24
Peak memory 201800 kb
Host smart-aaf0f8a2-ab90-4212-8f28-a4b04eaac662
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238812299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1238812299
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4116814370
Short name T256
Test name
Test status
Simulation time 565217584906 ps
CPU time 1397.29 seconds
Started Mar 24 12:54:22 PM PDT 24
Finished Mar 24 01:17:39 PM PDT 24
Peak memory 201944 kb
Host smart-fe5ffc61-149e-4ea4-9308-7bd5d7417654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116814370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4116814370
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2331992114
Short name T471
Test name
Test status
Simulation time 604096627819 ps
CPU time 202.22 seconds
Started Mar 24 12:54:23 PM PDT 24
Finished Mar 24 12:57:45 PM PDT 24
Peak memory 201772 kb
Host smart-0056c090-7e9d-442e-bbb5-08f153700d29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331992114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2331992114
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1434534572
Short name T695
Test name
Test status
Simulation time 92657478617 ps
CPU time 497.42 seconds
Started Mar 24 12:54:21 PM PDT 24
Finished Mar 24 01:02:39 PM PDT 24
Peak memory 202140 kb
Host smart-02ed1867-fc8a-4949-a6e7-baff3f3786fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434534572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1434534572
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1959631487
Short name T498
Test name
Test status
Simulation time 45654490222 ps
CPU time 49.56 seconds
Started Mar 24 12:54:23 PM PDT 24
Finished Mar 24 12:55:13 PM PDT 24
Peak memory 201648 kb
Host smart-9e7f4bbb-f1d6-41b9-a4c1-60eb222cfdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959631487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1959631487
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4040779947
Short name T529
Test name
Test status
Simulation time 3440509525 ps
CPU time 2.75 seconds
Started Mar 24 12:54:22 PM PDT 24
Finished Mar 24 12:54:25 PM PDT 24
Peak memory 201612 kb
Host smart-88af1016-a22e-4b7a-8422-cc17500fc6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040779947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4040779947
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2668659048
Short name T693
Test name
Test status
Simulation time 6047617139 ps
CPU time 13.28 seconds
Started Mar 24 12:54:14 PM PDT 24
Finished Mar 24 12:54:28 PM PDT 24
Peak memory 201636 kb
Host smart-1f7d57b8-54cc-427d-ad50-0a4b9f16a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668659048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2668659048
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1765103997
Short name T512
Test name
Test status
Simulation time 208391351402 ps
CPU time 53.78 seconds
Started Mar 24 12:54:22 PM PDT 24
Finished Mar 24 12:55:16 PM PDT 24
Peak memory 201712 kb
Host smart-a2c33020-29bf-44a0-bb86-8bce6fc3a487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765103997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1765103997
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2296141314
Short name T401
Test name
Test status
Simulation time 379563714 ps
CPU time 1.38 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:54:29 PM PDT 24
Peak memory 201472 kb
Host smart-bd75b4c5-650c-458e-8d81-c9923d4e3bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296141314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2296141314
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.97547829
Short name T704
Test name
Test status
Simulation time 343942550902 ps
CPU time 366.11 seconds
Started Mar 24 12:54:25 PM PDT 24
Finished Mar 24 01:00:32 PM PDT 24
Peak memory 201896 kb
Host smart-eef54822-d80e-49cb-a801-4bff336ec99e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97547829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gatin
g.97547829
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3808952827
Short name T329
Test name
Test status
Simulation time 434011792087 ps
CPU time 74.29 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:55:42 PM PDT 24
Peak memory 201804 kb
Host smart-c88d8371-bfaa-4637-bc56-2af25f7887c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808952827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3808952827
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.371499169
Short name T126
Test name
Test status
Simulation time 335949547222 ps
CPU time 767.58 seconds
Started Mar 24 12:54:24 PM PDT 24
Finished Mar 24 01:07:12 PM PDT 24
Peak memory 201824 kb
Host smart-585786bf-25e2-4d99-926c-709808c1fdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371499169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.371499169
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1010535684
Short name T502
Test name
Test status
Simulation time 492225244014 ps
CPU time 576.92 seconds
Started Mar 24 12:54:29 PM PDT 24
Finished Mar 24 01:04:06 PM PDT 24
Peak memory 201832 kb
Host smart-80727ed6-5fe3-4bba-a0dc-78f4e23add8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010535684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1010535684
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.841833462
Short name T521
Test name
Test status
Simulation time 498450665923 ps
CPU time 1250.51 seconds
Started Mar 24 12:54:21 PM PDT 24
Finished Mar 24 01:15:12 PM PDT 24
Peak memory 201820 kb
Host smart-ce9cd89d-1e8e-465f-a044-3b3fc59f98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841833462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.841833462
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.703008312
Short name T531
Test name
Test status
Simulation time 318601842200 ps
CPU time 364 seconds
Started Mar 24 12:54:24 PM PDT 24
Finished Mar 24 01:00:28 PM PDT 24
Peak memory 201796 kb
Host smart-84cd0de9-89a7-4bd1-9e03-668dab7b8f71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=703008312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.703008312
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1940861192
Short name T382
Test name
Test status
Simulation time 597481305745 ps
CPU time 1481.98 seconds
Started Mar 24 12:54:32 PM PDT 24
Finished Mar 24 01:19:14 PM PDT 24
Peak memory 201796 kb
Host smart-92eeb5a0-df48-403c-891e-c6d3d1a34177
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940861192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1940861192
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.671152575
Short name T639
Test name
Test status
Simulation time 81557915101 ps
CPU time 417.78 seconds
Started Mar 24 12:54:26 PM PDT 24
Finished Mar 24 01:01:25 PM PDT 24
Peak memory 202216 kb
Host smart-a524d1e8-5656-4dae-9a1f-b08e7e9669b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671152575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.671152575
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1381102111
Short name T508
Test name
Test status
Simulation time 44381943655 ps
CPU time 28.25 seconds
Started Mar 24 12:54:29 PM PDT 24
Finished Mar 24 12:54:57 PM PDT 24
Peak memory 201648 kb
Host smart-2a2b5570-bf61-43b7-9410-0f810040ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381102111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1381102111
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.106190067
Short name T683
Test name
Test status
Simulation time 4309226127 ps
CPU time 3.58 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:54:31 PM PDT 24
Peak memory 201656 kb
Host smart-bc2bce17-63f8-4b7b-8781-8aba7c2d1cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106190067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.106190067
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.4135774229
Short name T134
Test name
Test status
Simulation time 6058463066 ps
CPU time 15.58 seconds
Started Mar 24 12:54:20 PM PDT 24
Finished Mar 24 12:54:36 PM PDT 24
Peak memory 201656 kb
Host smart-df33d50e-9c95-4058-8cee-169bf2538019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135774229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4135774229
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.547128127
Short name T420
Test name
Test status
Simulation time 114239557597 ps
CPU time 475.2 seconds
Started Mar 24 12:54:28 PM PDT 24
Finished Mar 24 01:02:23 PM PDT 24
Peak memory 202176 kb
Host smart-8ec29ccd-73ac-4e64-b4db-a4e0a955d930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547128127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
547128127
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1914012692
Short name T758
Test name
Test status
Simulation time 523767237 ps
CPU time 1.6 seconds
Started Mar 24 12:54:30 PM PDT 24
Finished Mar 24 12:54:32 PM PDT 24
Peak memory 201408 kb
Host smart-7321c6b6-0991-4929-b724-6ddd989e6104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914012692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1914012692
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.295093138
Short name T310
Test name
Test status
Simulation time 165455009529 ps
CPU time 60.93 seconds
Started Mar 24 12:54:33 PM PDT 24
Finished Mar 24 12:55:34 PM PDT 24
Peak memory 201808 kb
Host smart-bd40e74e-16ed-4e76-8f24-d9af3bb95d21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295093138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.295093138
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.356261129
Short name T104
Test name
Test status
Simulation time 322596744944 ps
CPU time 752.76 seconds
Started Mar 24 12:54:34 PM PDT 24
Finished Mar 24 01:07:06 PM PDT 24
Peak memory 201728 kb
Host smart-eaf99cc0-f795-4dd7-b1fa-6d9ab99cfb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356261129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.356261129
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.14584591
Short name T755
Test name
Test status
Simulation time 162762599274 ps
CPU time 156.81 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:57:04 PM PDT 24
Peak memory 201860 kb
Host smart-1c50247b-fd30-43c9-84e1-83ff0e94acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14584591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.14584591
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2584531615
Short name T37
Test name
Test status
Simulation time 331888586174 ps
CPU time 157.97 seconds
Started Mar 24 12:54:26 PM PDT 24
Finished Mar 24 12:57:05 PM PDT 24
Peak memory 201836 kb
Host smart-474cf5b7-f786-4361-9259-55a26cb7375e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584531615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2584531615
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2691058868
Short name T340
Test name
Test status
Simulation time 493590846391 ps
CPU time 811.16 seconds
Started Mar 24 12:54:28 PM PDT 24
Finished Mar 24 01:07:59 PM PDT 24
Peak memory 201860 kb
Host smart-25f085a4-f041-443c-b842-4bf148e34639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691058868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2691058868
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1573972857
Short name T136
Test name
Test status
Simulation time 487945129156 ps
CPU time 674.2 seconds
Started Mar 24 12:54:28 PM PDT 24
Finished Mar 24 01:05:42 PM PDT 24
Peak memory 201836 kb
Host smart-ffaf5ed6-5029-40b5-a7e6-28f8d0d5441b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573972857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1573972857
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4150377167
Short name T66
Test name
Test status
Simulation time 547846747390 ps
CPU time 334.6 seconds
Started Mar 24 12:54:33 PM PDT 24
Finished Mar 24 01:00:08 PM PDT 24
Peak memory 201820 kb
Host smart-f32c3297-d868-4e60-838f-2bd48f453fb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150377167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4150377167
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.728123786
Short name T128
Test name
Test status
Simulation time 608331848572 ps
CPU time 1468.63 seconds
Started Mar 24 12:54:34 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 201716 kb
Host smart-36a7cde1-8588-4741-b8d9-5a5038686e1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728123786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.728123786
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4124173798
Short name T497
Test name
Test status
Simulation time 94846107851 ps
CPU time 348.29 seconds
Started Mar 24 12:54:42 PM PDT 24
Finished Mar 24 01:00:30 PM PDT 24
Peak memory 202168 kb
Host smart-49392f01-154c-4a32-a5e1-93353ffcf884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124173798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4124173798
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3228265675
Short name T519
Test name
Test status
Simulation time 25272005736 ps
CPU time 58.87 seconds
Started Mar 24 12:54:31 PM PDT 24
Finished Mar 24 12:55:30 PM PDT 24
Peak memory 201648 kb
Host smart-2b98a573-f1ff-447a-9ddb-9acbed6a12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228265675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3228265675
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4094491453
Short name T653
Test name
Test status
Simulation time 3058333646 ps
CPU time 2.7 seconds
Started Mar 24 12:54:31 PM PDT 24
Finished Mar 24 12:54:34 PM PDT 24
Peak memory 201560 kb
Host smart-58e4219d-7a27-4604-a5eb-4af4459ad91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094491453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4094491453
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.302914327
Short name T520
Test name
Test status
Simulation time 5858149447 ps
CPU time 15.09 seconds
Started Mar 24 12:54:27 PM PDT 24
Finished Mar 24 12:54:42 PM PDT 24
Peak memory 201648 kb
Host smart-2242e737-6585-402d-90d5-4131e3c6f7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302914327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.302914327
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2600297738
Short name T172
Test name
Test status
Simulation time 216696857292 ps
CPU time 108.69 seconds
Started Mar 24 12:54:30 PM PDT 24
Finished Mar 24 12:56:19 PM PDT 24
Peak memory 201880 kb
Host smart-da7cc5bd-0aea-44c4-a8bb-3697019adff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600297738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2600297738
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.7478943
Short name T560
Test name
Test status
Simulation time 117737634567 ps
CPU time 132.34 seconds
Started Mar 24 12:54:34 PM PDT 24
Finished Mar 24 12:56:46 PM PDT 24
Peak memory 210644 kb
Host smart-bf5a1ddd-2ec1-41d1-befd-81fb36ab551c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7478943 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.7478943
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.672570145
Short name T392
Test name
Test status
Simulation time 406583003 ps
CPU time 1.59 seconds
Started Mar 24 12:54:43 PM PDT 24
Finished Mar 24 12:54:45 PM PDT 24
Peak memory 201484 kb
Host smart-7b43e852-79cb-4275-b592-eb7fd1688f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672570145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.672570145
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.716205183
Short name T165
Test name
Test status
Simulation time 362272363367 ps
CPU time 220.58 seconds
Started Mar 24 12:54:36 PM PDT 24
Finished Mar 24 12:58:17 PM PDT 24
Peak memory 201932 kb
Host smart-8bd38172-d74a-48a6-a43d-d656c1f8b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716205183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.716205183
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.465233597
Short name T171
Test name
Test status
Simulation time 164564262201 ps
CPU time 402.27 seconds
Started Mar 24 12:54:39 PM PDT 24
Finished Mar 24 01:01:22 PM PDT 24
Peak memory 201864 kb
Host smart-e6549847-36ec-4f04-a88d-7bf5bc1ba8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465233597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.465233597
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1594742980
Short name T469
Test name
Test status
Simulation time 489052480879 ps
CPU time 614.09 seconds
Started Mar 24 12:54:37 PM PDT 24
Finished Mar 24 01:04:51 PM PDT 24
Peak memory 201900 kb
Host smart-124fdb84-a85a-44c4-af65-d983aa531206
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594742980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1594742980
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3273230438
Short name T213
Test name
Test status
Simulation time 489211030650 ps
CPU time 231.68 seconds
Started Mar 24 12:54:45 PM PDT 24
Finished Mar 24 12:58:37 PM PDT 24
Peak memory 201872 kb
Host smart-33aff679-2b55-4d2d-9845-6375b6627029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273230438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3273230438
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3129105376
Short name T584
Test name
Test status
Simulation time 162202769997 ps
CPU time 90.07 seconds
Started Mar 24 12:54:45 PM PDT 24
Finished Mar 24 12:56:15 PM PDT 24
Peak memory 201816 kb
Host smart-da8dbcf7-0e27-4c4c-bce4-6f44a2437deb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129105376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3129105376
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2690198258
Short name T283
Test name
Test status
Simulation time 547164174454 ps
CPU time 689.77 seconds
Started Mar 24 12:54:44 PM PDT 24
Finished Mar 24 01:06:15 PM PDT 24
Peak memory 201796 kb
Host smart-8b2f8a9b-0cfc-4063-b6c1-2a261380a0a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690198258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2690198258
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2770447282
Short name T453
Test name
Test status
Simulation time 385641310344 ps
CPU time 185.1 seconds
Started Mar 24 12:54:44 PM PDT 24
Finished Mar 24 12:57:50 PM PDT 24
Peak memory 201804 kb
Host smart-624fffc2-ecc7-45f3-9a65-6e74e0854a7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770447282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2770447282
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.959492546
Short name T404
Test name
Test status
Simulation time 23638325520 ps
CPU time 53.83 seconds
Started Mar 24 12:54:42 PM PDT 24
Finished Mar 24 12:55:36 PM PDT 24
Peak memory 201640 kb
Host smart-7e99685a-c22e-430c-90b6-03a287955176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959492546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.959492546
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.77192538
Short name T665
Test name
Test status
Simulation time 3080097544 ps
CPU time 2.75 seconds
Started Mar 24 12:54:44 PM PDT 24
Finished Mar 24 12:54:47 PM PDT 24
Peak memory 201540 kb
Host smart-ed782cb3-6a7f-4108-a56c-a4b1669450a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77192538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.77192538
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.323844149
Short name T604
Test name
Test status
Simulation time 6119725054 ps
CPU time 16.06 seconds
Started Mar 24 12:54:38 PM PDT 24
Finished Mar 24 12:54:54 PM PDT 24
Peak memory 201688 kb
Host smart-03e3e50f-2a93-4103-94c8-3710da8c1b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323844149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.323844149
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2841694059
Short name T726
Test name
Test status
Simulation time 516209493713 ps
CPU time 1268.11 seconds
Started Mar 24 12:54:42 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 201740 kb
Host smart-2da6d0ed-fe77-4bc1-a971-194d949a7b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841694059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2841694059
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2018749611
Short name T706
Test name
Test status
Simulation time 69845977044 ps
CPU time 56.75 seconds
Started Mar 24 12:54:43 PM PDT 24
Finished Mar 24 12:55:40 PM PDT 24
Peak memory 210504 kb
Host smart-9008c32b-4aae-4f3c-a5ad-43c775eef820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018749611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2018749611
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2193499409
Short name T57
Test name
Test status
Simulation time 537042979 ps
CPU time 0.73 seconds
Started Mar 24 12:54:58 PM PDT 24
Finished Mar 24 12:54:59 PM PDT 24
Peak memory 201532 kb
Host smart-f18012ad-99bc-473c-aba9-787ebec191e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193499409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2193499409
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3065659399
Short name T730
Test name
Test status
Simulation time 197453670226 ps
CPU time 206.45 seconds
Started Mar 24 12:54:50 PM PDT 24
Finished Mar 24 12:58:16 PM PDT 24
Peak memory 201904 kb
Host smart-77b1af75-e86e-4bea-a393-98d7d0f57b08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065659399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3065659399
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2356826772
Short name T666
Test name
Test status
Simulation time 160117164502 ps
CPU time 83.26 seconds
Started Mar 24 12:54:47 PM PDT 24
Finished Mar 24 12:56:11 PM PDT 24
Peak memory 201812 kb
Host smart-97bbc8cc-5ccc-4dde-8932-de56cc638540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356826772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2356826772
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2402502912
Short name T263
Test name
Test status
Simulation time 485005464210 ps
CPU time 1193.95 seconds
Started Mar 24 12:54:48 PM PDT 24
Finished Mar 24 01:14:42 PM PDT 24
Peak memory 201816 kb
Host smart-3b18277b-4b74-4373-ae44-d01bded2ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402502912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2402502912
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1289674680
Short name T56
Test name
Test status
Simulation time 330426509187 ps
CPU time 160.75 seconds
Started Mar 24 12:54:48 PM PDT 24
Finished Mar 24 12:57:29 PM PDT 24
Peak memory 201788 kb
Host smart-e85a7594-4ced-41d9-9be8-a9984b4c8ded
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289674680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1289674680
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3729699833
Short name T28
Test name
Test status
Simulation time 496222466126 ps
CPU time 1163.08 seconds
Started Mar 24 12:54:46 PM PDT 24
Finished Mar 24 01:14:09 PM PDT 24
Peak memory 201864 kb
Host smart-d866ea68-7530-47e0-9532-cf0de6c1508d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729699833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3729699833
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2615917431
Short name T590
Test name
Test status
Simulation time 499226147827 ps
CPU time 565.72 seconds
Started Mar 24 12:54:47 PM PDT 24
Finished Mar 24 01:04:13 PM PDT 24
Peak memory 201792 kb
Host smart-20cb1b5a-4e34-40d6-bfbb-23ddb9a0b45b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615917431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2615917431
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.893129976
Short name T251
Test name
Test status
Simulation time 568151231550 ps
CPU time 1124.16 seconds
Started Mar 24 12:54:46 PM PDT 24
Finished Mar 24 01:13:31 PM PDT 24
Peak memory 201856 kb
Host smart-5ad67b14-2c59-4123-8891-59c137da79de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893129976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.893129976
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1486544062
Short name T636
Test name
Test status
Simulation time 384268963379 ps
CPU time 479.05 seconds
Started Mar 24 12:54:48 PM PDT 24
Finished Mar 24 01:02:47 PM PDT 24
Peak memory 201864 kb
Host smart-099a2238-419c-4b5b-b8e3-48bf91949314
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486544062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1486544062
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2547615819
Short name T70
Test name
Test status
Simulation time 76843928499 ps
CPU time 388.63 seconds
Started Mar 24 12:54:51 PM PDT 24
Finished Mar 24 01:01:20 PM PDT 24
Peak memory 202200 kb
Host smart-add7537a-19bd-4fd6-99d9-31efe4380e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547615819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2547615819
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3045133137
Short name T673
Test name
Test status
Simulation time 47530786853 ps
CPU time 52.83 seconds
Started Mar 24 12:55:01 PM PDT 24
Finished Mar 24 12:55:54 PM PDT 24
Peak memory 201652 kb
Host smart-9e1b7dcb-a083-4ef1-95b0-9773ecfb0b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045133137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3045133137
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4245763584
Short name T381
Test name
Test status
Simulation time 5438017513 ps
CPU time 7.42 seconds
Started Mar 24 12:54:48 PM PDT 24
Finished Mar 24 12:54:56 PM PDT 24
Peak memory 201636 kb
Host smart-0d9e6651-5b0e-4418-9ea2-f42a249a9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245763584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4245763584
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2026492808
Short name T739
Test name
Test status
Simulation time 5621219876 ps
CPU time 14.39 seconds
Started Mar 24 12:54:49 PM PDT 24
Finished Mar 24 12:55:04 PM PDT 24
Peak memory 201648 kb
Host smart-61b26bbd-15ad-4c85-8c27-37c381d00442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026492808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2026492808
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2981496688
Short name T304
Test name
Test status
Simulation time 328322760725 ps
CPU time 420.33 seconds
Started Mar 24 12:54:53 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 201792 kb
Host smart-c60aa2a6-50fa-4fc4-a57c-791571917594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981496688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2981496688
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.320190081
Short name T287
Test name
Test status
Simulation time 164024737461 ps
CPU time 149.63 seconds
Started Mar 24 12:55:01 PM PDT 24
Finished Mar 24 12:57:31 PM PDT 24
Peak memory 210540 kb
Host smart-79356106-d325-487c-b23f-f3ada71fb7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320190081 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.320190081
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3839541738
Short name T88
Test name
Test status
Simulation time 438845270 ps
CPU time 1.61 seconds
Started Mar 24 12:55:03 PM PDT 24
Finished Mar 24 12:55:04 PM PDT 24
Peak memory 201552 kb
Host smart-0caaff8a-f49d-4895-b60f-3435d9ae0d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839541738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3839541738
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.814336950
Short name T699
Test name
Test status
Simulation time 528420972877 ps
CPU time 443.15 seconds
Started Mar 24 12:55:07 PM PDT 24
Finished Mar 24 01:02:30 PM PDT 24
Peak memory 201832 kb
Host smart-b26f7de1-468a-4f9b-b60d-45ea6ab62906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814336950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.814336950
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1337687457
Short name T306
Test name
Test status
Simulation time 498573883394 ps
CPU time 1266.32 seconds
Started Mar 24 12:55:02 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 201892 kb
Host smart-443a80e9-12b4-4fbf-a3bd-fe5e7e68ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337687457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1337687457
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1440688731
Short name T744
Test name
Test status
Simulation time 326456509892 ps
CPU time 195.69 seconds
Started Mar 24 12:54:58 PM PDT 24
Finished Mar 24 12:58:14 PM PDT 24
Peak memory 201740 kb
Host smart-ead81fee-f8a8-45a8-9005-73f8456924ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440688731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1440688731
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2740004982
Short name T572
Test name
Test status
Simulation time 486144550825 ps
CPU time 1093.59 seconds
Started Mar 24 12:54:57 PM PDT 24
Finished Mar 24 01:13:11 PM PDT 24
Peak memory 201900 kb
Host smart-47a57224-58ad-486f-9532-8f4554aefdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740004982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2740004982
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2319718944
Short name T535
Test name
Test status
Simulation time 167175567898 ps
CPU time 98.05 seconds
Started Mar 24 12:55:02 PM PDT 24
Finished Mar 24 12:56:40 PM PDT 24
Peak memory 201832 kb
Host smart-da3c4400-8a8c-44ec-9baa-a3102afd55c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319718944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2319718944
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1350362239
Short name T570
Test name
Test status
Simulation time 400906417821 ps
CPU time 478.2 seconds
Started Mar 24 12:54:58 PM PDT 24
Finished Mar 24 01:02:56 PM PDT 24
Peak memory 201852 kb
Host smart-027f5899-448e-4842-931c-a9ecca09b124
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350362239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1350362239
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1981808657
Short name T205
Test name
Test status
Simulation time 198437417365 ps
CPU time 492.08 seconds
Started Mar 24 12:54:56 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 201864 kb
Host smart-86793f3a-705d-4370-a1db-c1f9668a0ed8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981808657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1981808657
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3372185796
Short name T571
Test name
Test status
Simulation time 113379341416 ps
CPU time 387.15 seconds
Started Mar 24 12:55:02 PM PDT 24
Finished Mar 24 01:01:29 PM PDT 24
Peak memory 202076 kb
Host smart-0e4e2737-32aa-4a4d-a13f-ddc392cbbc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372185796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3372185796
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3737161504
Short name T493
Test name
Test status
Simulation time 33390437547 ps
CPU time 5.47 seconds
Started Mar 24 12:55:04 PM PDT 24
Finished Mar 24 12:55:10 PM PDT 24
Peak memory 201644 kb
Host smart-359d1cbd-5b22-4dea-a88c-8f3081256663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737161504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3737161504
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3406812105
Short name T443
Test name
Test status
Simulation time 2987920095 ps
CPU time 7.45 seconds
Started Mar 24 12:55:08 PM PDT 24
Finished Mar 24 12:55:15 PM PDT 24
Peak memory 201572 kb
Host smart-9142629d-3f11-4ab2-a735-ca61b986df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406812105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3406812105
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.39155362
Short name T633
Test name
Test status
Simulation time 5693692194 ps
CPU time 3.35 seconds
Started Mar 24 12:54:59 PM PDT 24
Finished Mar 24 12:55:02 PM PDT 24
Peak memory 201648 kb
Host smart-b7474fb9-24db-4c80-bc2c-0105a077ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39155362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.39155362
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3368167446
Short name T267
Test name
Test status
Simulation time 358352465306 ps
CPU time 166.26 seconds
Started Mar 24 12:55:08 PM PDT 24
Finished Mar 24 12:57:54 PM PDT 24
Peak memory 201832 kb
Host smart-e80162f5-4906-43e7-8a30-2bca2272f620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368167446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3368167446
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2229951399
Short name T659
Test name
Test status
Simulation time 432309192 ps
CPU time 0.82 seconds
Started Mar 24 12:55:12 PM PDT 24
Finished Mar 24 12:55:13 PM PDT 24
Peak memory 201496 kb
Host smart-426ea11c-e49d-4b0f-8c06-a50f108a27ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229951399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2229951399
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3942979093
Short name T686
Test name
Test status
Simulation time 181892505549 ps
CPU time 219.49 seconds
Started Mar 24 12:55:09 PM PDT 24
Finished Mar 24 12:58:49 PM PDT 24
Peak memory 201828 kb
Host smart-0df4f0db-5405-43a9-b374-ac8eb560238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942979093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3942979093
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3822668026
Short name T352
Test name
Test status
Simulation time 326710216917 ps
CPU time 820.14 seconds
Started Mar 24 12:55:03 PM PDT 24
Finished Mar 24 01:08:43 PM PDT 24
Peak memory 201820 kb
Host smart-8ed92b23-91fd-489c-9f79-e15bd77a1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822668026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3822668026
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4219072411
Short name T416
Test name
Test status
Simulation time 493866512129 ps
CPU time 625.61 seconds
Started Mar 24 12:55:05 PM PDT 24
Finished Mar 24 01:05:32 PM PDT 24
Peak memory 201852 kb
Host smart-e727197f-fb13-40ef-9b99-b19d65ffef6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219072411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4219072411
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3398572669
Short name T330
Test name
Test status
Simulation time 489268855387 ps
CPU time 535.69 seconds
Started Mar 24 12:55:04 PM PDT 24
Finished Mar 24 01:04:00 PM PDT 24
Peak memory 201836 kb
Host smart-4eebc8df-9ad1-4da7-8121-e669a2940d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398572669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3398572669
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.714012626
Short name T635
Test name
Test status
Simulation time 487142682702 ps
CPU time 294.28 seconds
Started Mar 24 12:55:03 PM PDT 24
Finished Mar 24 12:59:57 PM PDT 24
Peak memory 201792 kb
Host smart-930976a6-45a2-4dd2-bdf5-8810eeafd2bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=714012626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.714012626
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.282373436
Short name T307
Test name
Test status
Simulation time 193462985666 ps
CPU time 454.81 seconds
Started Mar 24 12:55:09 PM PDT 24
Finished Mar 24 01:02:44 PM PDT 24
Peak memory 201960 kb
Host smart-f7e57b64-6d51-4a35-b7f1-247f72b2165a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282373436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.282373436
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1113890195
Short name T524
Test name
Test status
Simulation time 597558882350 ps
CPU time 1526.89 seconds
Started Mar 24 12:55:07 PM PDT 24
Finished Mar 24 01:20:34 PM PDT 24
Peak memory 201872 kb
Host smart-f473976d-9605-42ce-bb90-115f4b6955b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113890195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1113890195
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3789097604
Short name T771
Test name
Test status
Simulation time 68256020948 ps
CPU time 298.64 seconds
Started Mar 24 12:55:09 PM PDT 24
Finished Mar 24 01:00:08 PM PDT 24
Peak memory 202424 kb
Host smart-1ee7b084-4cb6-4777-8360-ae26c663fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789097604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3789097604
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.779467175
Short name T499
Test name
Test status
Simulation time 32464791993 ps
CPU time 41.35 seconds
Started Mar 24 12:55:07 PM PDT 24
Finished Mar 24 12:55:48 PM PDT 24
Peak memory 201628 kb
Host smart-17a1dd12-2b90-4677-a463-621fc2c4c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779467175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.779467175
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2003369843
Short name T449
Test name
Test status
Simulation time 3249481973 ps
CPU time 7.99 seconds
Started Mar 24 12:55:10 PM PDT 24
Finished Mar 24 12:55:18 PM PDT 24
Peak memory 201576 kb
Host smart-22979468-e332-4f17-9e8a-ee8f20516203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003369843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2003369843
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1343890608
Short name T522
Test name
Test status
Simulation time 5726288965 ps
CPU time 14.08 seconds
Started Mar 24 12:55:03 PM PDT 24
Finished Mar 24 12:55:17 PM PDT 24
Peak memory 201632 kb
Host smart-b760863f-db96-4e00-9f4e-736a51af18c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343890608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1343890608
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2826390496
Short name T766
Test name
Test status
Simulation time 193363615924 ps
CPU time 420.15 seconds
Started Mar 24 12:55:14 PM PDT 24
Finished Mar 24 01:02:14 PM PDT 24
Peak memory 201816 kb
Host smart-00b80ec7-f04e-441c-88d4-eb4259b0b22c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826390496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2826390496
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2250418348
Short name T53
Test name
Test status
Simulation time 78811934889 ps
CPU time 61.21 seconds
Started Mar 24 12:55:13 PM PDT 24
Finished Mar 24 12:56:14 PM PDT 24
Peak memory 210216 kb
Host smart-0d8374bc-fb1b-4162-aad7-e5a19f847cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250418348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2250418348
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1148625503
Short name T655
Test name
Test status
Simulation time 391303891 ps
CPU time 1.06 seconds
Started Mar 24 12:55:24 PM PDT 24
Finished Mar 24 12:55:25 PM PDT 24
Peak memory 201568 kb
Host smart-424f26e7-995e-4d84-a75b-354e705d0da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148625503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1148625503
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.77562300
Short name T288
Test name
Test status
Simulation time 500368497158 ps
CPU time 503.06 seconds
Started Mar 24 12:55:18 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 201792 kb
Host smart-fa8ab8eb-8e14-4c7b-afd1-cb5ca5c0c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77562300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.77562300
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1283593479
Short name T331
Test name
Test status
Simulation time 169624933502 ps
CPU time 420.44 seconds
Started Mar 24 12:55:15 PM PDT 24
Finished Mar 24 01:02:15 PM PDT 24
Peak memory 201892 kb
Host smart-7f208579-89cf-42e0-9b19-b6c17822402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283593479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1283593479
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.7120057
Short name T617
Test name
Test status
Simulation time 168146879488 ps
CPU time 97.37 seconds
Started Mar 24 12:55:18 PM PDT 24
Finished Mar 24 12:56:56 PM PDT 24
Peak memory 201796 kb
Host smart-c32f7e26-a6e5-430c-a613-81330a797c04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=7120057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_
fixed.7120057
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.529704276
Short name T596
Test name
Test status
Simulation time 166932872775 ps
CPU time 374.83 seconds
Started Mar 24 12:55:14 PM PDT 24
Finished Mar 24 01:01:29 PM PDT 24
Peak memory 201896 kb
Host smart-3d60a29a-01b3-4ae9-9115-b91ce113d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529704276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.529704276
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4128197060
Short name T708
Test name
Test status
Simulation time 167966684329 ps
CPU time 364.69 seconds
Started Mar 24 12:55:13 PM PDT 24
Finished Mar 24 01:01:18 PM PDT 24
Peak memory 201864 kb
Host smart-9b07bb21-4b67-4c2a-a0e6-b9e4b8faa98f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128197060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4128197060
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.249274055
Short name T490
Test name
Test status
Simulation time 401939615283 ps
CPU time 491.66 seconds
Started Mar 24 12:55:17 PM PDT 24
Finished Mar 24 01:03:29 PM PDT 24
Peak memory 201820 kb
Host smart-718477a7-715d-473f-a550-1e23e6c45475
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249274055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.249274055
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.232510015
Short name T226
Test name
Test status
Simulation time 108603853423 ps
CPU time 418.68 seconds
Started Mar 24 12:55:17 PM PDT 24
Finished Mar 24 01:02:15 PM PDT 24
Peak memory 202148 kb
Host smart-c34280d2-b990-49a7-8bff-155af8264331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232510015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.232510015
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2368110953
Short name T468
Test name
Test status
Simulation time 25732732457 ps
CPU time 65.31 seconds
Started Mar 24 12:55:19 PM PDT 24
Finished Mar 24 12:56:24 PM PDT 24
Peak memory 201536 kb
Host smart-c878b7f4-7f5e-4e69-a036-32283b257fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368110953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2368110953
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2356235075
Short name T631
Test name
Test status
Simulation time 3373710808 ps
CPU time 4.26 seconds
Started Mar 24 12:55:19 PM PDT 24
Finished Mar 24 12:55:23 PM PDT 24
Peak memory 201596 kb
Host smart-965143a5-7d09-40dd-9b55-505baef2fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356235075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2356235075
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2593278107
Short name T649
Test name
Test status
Simulation time 5756173959 ps
CPU time 3.87 seconds
Started Mar 24 12:55:13 PM PDT 24
Finished Mar 24 12:55:17 PM PDT 24
Peak memory 201584 kb
Host smart-33bd434f-9e3e-4f30-9254-6da78619984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593278107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2593278107
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1520440304
Short name T18
Test name
Test status
Simulation time 58157672245 ps
CPU time 65.3 seconds
Started Mar 24 12:55:18 PM PDT 24
Finished Mar 24 12:56:23 PM PDT 24
Peak memory 210216 kb
Host smart-2b06cba8-9785-463d-b238-6d18d15bf2ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520440304 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1520440304
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.205443696
Short name T30
Test name
Test status
Simulation time 491320181 ps
CPU time 0.97 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:21 PM PDT 24
Peak memory 201432 kb
Host smart-18d251e0-a829-4f3f-8e9c-02511a1c5e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205443696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.205443696
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2374800511
Short name T549
Test name
Test status
Simulation time 156837723758 ps
CPU time 338.63 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:56:03 PM PDT 24
Peak memory 201928 kb
Host smart-44791f0e-897b-4fa0-b4b2-ddf364ff0d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374800511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2374800511
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4273413474
Short name T661
Test name
Test status
Simulation time 489579093699 ps
CPU time 594.47 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 01:00:20 PM PDT 24
Peak memory 201916 kb
Host smart-d49bbed7-b72c-4cfe-92d0-34d7b88e1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273413474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4273413474
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4243150674
Short name T682
Test name
Test status
Simulation time 490710012930 ps
CPU time 1241.74 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 01:11:03 PM PDT 24
Peak memory 201912 kb
Host smart-cdefadce-9434-4895-a176-4b4d696c6ed3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243150674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4243150674
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1075324734
Short name T186
Test name
Test status
Simulation time 484104416347 ps
CPU time 567 seconds
Started Mar 24 12:50:29 PM PDT 24
Finished Mar 24 12:59:56 PM PDT 24
Peak memory 201720 kb
Host smart-ccfd52d8-d731-486b-b431-3d0b40a62071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075324734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1075324734
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.624586035
Short name T623
Test name
Test status
Simulation time 495310449202 ps
CPU time 279.72 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:55:04 PM PDT 24
Peak memory 201804 kb
Host smart-0dcbf863-a554-4d62-979c-08e9ea2d0bbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=624586035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.624586035
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3179627477
Short name T577
Test name
Test status
Simulation time 169547893775 ps
CPU time 102.25 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:52:11 PM PDT 24
Peak memory 201820 kb
Host smart-a7da7a43-94c1-4e04-b21c-55e9b12960c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179627477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3179627477
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.846730600
Short name T1
Test name
Test status
Simulation time 600620629238 ps
CPU time 1323.28 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 01:12:28 PM PDT 24
Peak memory 201812 kb
Host smart-c125dfe8-8c1d-4c2c-bb80-0676f05a43e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846730600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.846730600
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.704324103
Short name T491
Test name
Test status
Simulation time 86795217980 ps
CPU time 448.87 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:57:49 PM PDT 24
Peak memory 202164 kb
Host smart-b39b51ba-25f2-46e1-b3b0-4f4e6a3c750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704324103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.704324103
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3673518143
Short name T797
Test name
Test status
Simulation time 29376427227 ps
CPU time 32.98 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:55 PM PDT 24
Peak memory 201628 kb
Host smart-a6c7ce79-6dd9-4cfb-bb7b-a138521ddfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673518143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3673518143
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4177195554
Short name T714
Test name
Test status
Simulation time 4988047307 ps
CPU time 3.35 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 12:50:22 PM PDT 24
Peak memory 201644 kb
Host smart-3b630d28-2c8a-4add-a76a-91b94698c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177195554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4177195554
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2414581634
Short name T158
Test name
Test status
Simulation time 5973070191 ps
CPU time 4.41 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:50:31 PM PDT 24
Peak memory 201660 kb
Host smart-e45438de-ea7d-4020-a51c-bdeb012b7eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414581634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2414581634
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2354145429
Short name T737
Test name
Test status
Simulation time 158885121097 ps
CPU time 481.15 seconds
Started Mar 24 12:50:31 PM PDT 24
Finished Mar 24 12:58:33 PM PDT 24
Peak memory 210432 kb
Host smart-c1c55f03-1502-42b0-b1a5-dbfd2bb4c268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354145429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2354145429
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4288793076
Short name T49
Test name
Test status
Simulation time 136727431020 ps
CPU time 200.93 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 12:53:44 PM PDT 24
Peak memory 210496 kb
Host smart-602ffd6f-0f27-4066-ad97-48f04cc1f288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288793076 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4288793076
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3986788673
Short name T632
Test name
Test status
Simulation time 405958793 ps
CPU time 1.64 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:23 PM PDT 24
Peak memory 201544 kb
Host smart-7fc991c2-8b26-41d3-bdf0-6a07fbb6e722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986788673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3986788673
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3791540457
Short name T117
Test name
Test status
Simulation time 167868209048 ps
CPU time 398.09 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:57:05 PM PDT 24
Peak memory 201876 kb
Host smart-befd29f2-680f-46f2-86fb-fd88ed731e0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791540457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3791540457
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2708748354
Short name T658
Test name
Test status
Simulation time 489538844812 ps
CPU time 1168.57 seconds
Started Mar 24 12:50:18 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 201848 kb
Host smart-448d0710-bf9f-4065-bae0-74ff93541022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708748354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2708748354
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1291988784
Short name T722
Test name
Test status
Simulation time 332407888742 ps
CPU time 232.74 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:54:19 PM PDT 24
Peak memory 201868 kb
Host smart-2f9c5ac4-1181-4f58-bf1a-3c20b584380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291988784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1291988784
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.450826821
Short name T375
Test name
Test status
Simulation time 323949913287 ps
CPU time 535.39 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:59:20 PM PDT 24
Peak memory 201800 kb
Host smart-a20c42a4-3c9b-4b19-aff2-6c9b11ffa3ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=450826821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.450826821
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3226515723
Short name T173
Test name
Test status
Simulation time 497199074437 ps
CPU time 295.59 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:55:24 PM PDT 24
Peak memory 201860 kb
Host smart-ec37e351-39a3-492a-adfb-3c16b50bf1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226515723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3226515723
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1182447117
Short name T645
Test name
Test status
Simulation time 497953588890 ps
CPU time 255.82 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:54:43 PM PDT 24
Peak memory 201804 kb
Host smart-4beb68c2-70d9-4b9d-9594-ff290a77b38e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182447117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1182447117
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2015719686
Short name T489
Test name
Test status
Simulation time 594417676720 ps
CPU time 199.84 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:53:46 PM PDT 24
Peak memory 201868 kb
Host smart-78655e0b-ce30-4493-855c-8ced89c83913
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015719686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2015719686
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1266141186
Short name T69
Test name
Test status
Simulation time 99212541280 ps
CPU time 543.38 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:59:29 PM PDT 24
Peak memory 202176 kb
Host smart-39be03ee-14b7-464e-938d-43fae93d64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266141186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1266141186
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1523522939
Short name T372
Test name
Test status
Simulation time 40890674756 ps
CPU time 17.62 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:50:39 PM PDT 24
Peak memory 201688 kb
Host smart-26b9ce46-d428-43a2-bf96-9d58ffc24564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523522939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1523522939
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1963416219
Short name T444
Test name
Test status
Simulation time 3475533235 ps
CPU time 8.71 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:29 PM PDT 24
Peak memory 201564 kb
Host smart-fcbec5b2-4261-4234-9855-22f7975e0e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963416219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1963416219
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1855015468
Short name T709
Test name
Test status
Simulation time 6071517609 ps
CPU time 15.18 seconds
Started Mar 24 12:50:20 PM PDT 24
Finished Mar 24 12:50:35 PM PDT 24
Peak memory 201692 kb
Host smart-7ae8c2f6-7083-4072-8d0e-c0f736c594e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855015468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1855015468
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.155856538
Short name T501
Test name
Test status
Simulation time 517910354294 ps
CPU time 657.6 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 01:01:21 PM PDT 24
Peak memory 201860 kb
Host smart-9e162f9d-1858-406c-9a47-5edc206c40e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155856538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.155856538
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1919878278
Short name T12
Test name
Test status
Simulation time 34653709819 ps
CPU time 101.6 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:52:08 PM PDT 24
Peak memory 210492 kb
Host smart-c94f3485-6626-46ba-9ce7-68ece7494f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919878278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1919878278
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1906846796
Short name T586
Test name
Test status
Simulation time 390230170 ps
CPU time 1.51 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 12:50:26 PM PDT 24
Peak memory 201472 kb
Host smart-b1864654-f703-4b5d-af62-8718c039918e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906846796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1906846796
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2480342756
Short name T200
Test name
Test status
Simulation time 497970788184 ps
CPU time 308.54 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:55:37 PM PDT 24
Peak memory 201888 kb
Host smart-94e13772-0930-4216-b88a-83d63728dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480342756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2480342756
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.25596137
Short name T778
Test name
Test status
Simulation time 169877812135 ps
CPU time 216.68 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:54:07 PM PDT 24
Peak memory 201824 kb
Host smart-9294078d-6cac-4c96-92e0-84d231db5987
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.25596137
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1567361898
Short name T244
Test name
Test status
Simulation time 329394717640 ps
CPU time 706.72 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 01:02:11 PM PDT 24
Peak memory 201920 kb
Host smart-68191a37-d3b2-4118-aff4-67cdf8ab6f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567361898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1567361898
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4012107229
Short name T547
Test name
Test status
Simulation time 171582016504 ps
CPU time 418.32 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:57:26 PM PDT 24
Peak memory 201944 kb
Host smart-30f5eaca-b098-42aa-8b11-ff82752fb572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012107229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4012107229
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2400994904
Short name T300
Test name
Test status
Simulation time 538666818839 ps
CPU time 1183.09 seconds
Started Mar 24 12:50:23 PM PDT 24
Finished Mar 24 01:10:06 PM PDT 24
Peak memory 201940 kb
Host smart-525a5427-4874-43e9-be95-2d2fff5b47a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400994904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2400994904
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.623368456
Short name T528
Test name
Test status
Simulation time 198371008534 ps
CPU time 114.92 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:52:17 PM PDT 24
Peak memory 201956 kb
Host smart-38f2d65d-59e9-4cfc-b7e8-75488b66a41f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623368456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.623368456
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.554816257
Short name T108
Test name
Test status
Simulation time 109606289989 ps
CPU time 536.77 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:59:21 PM PDT 24
Peak memory 202140 kb
Host smart-38bda2a4-8e1d-41d1-9dbc-f7ba05263e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554816257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.554816257
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3928818059
Short name T396
Test name
Test status
Simulation time 30174111696 ps
CPU time 71.45 seconds
Started Mar 24 12:50:26 PM PDT 24
Finished Mar 24 12:51:38 PM PDT 24
Peak memory 201636 kb
Host smart-84d18ad8-fd2a-4146-ac09-06f0af8f4c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928818059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3928818059
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3646407744
Short name T505
Test name
Test status
Simulation time 5545314243 ps
CPU time 3.63 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:28 PM PDT 24
Peak memory 201540 kb
Host smart-aa65f723-964e-4f18-a96b-3d4f2b86b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646407744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3646407744
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3137227113
Short name T371
Test name
Test status
Simulation time 5825726075 ps
CPU time 15.66 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:50:40 PM PDT 24
Peak memory 201648 kb
Host smart-835e815c-02f1-4f24-9544-e95b93b55837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137227113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3137227113
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3166328545
Short name T36
Test name
Test status
Simulation time 76497108563 ps
CPU time 43.8 seconds
Started Mar 24 12:50:33 PM PDT 24
Finished Mar 24 12:51:17 PM PDT 24
Peak memory 201660 kb
Host smart-7e5cd833-d241-4d91-b99d-5bab519f5229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166328545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3166328545
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1998282086
Short name T55
Test name
Test status
Simulation time 90519976871 ps
CPU time 118.72 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:52:27 PM PDT 24
Peak memory 202068 kb
Host smart-481b4fa2-7e33-444a-afc6-cfc4aeb230e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998282086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1998282086
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2328352400
Short name T389
Test name
Test status
Simulation time 423879814 ps
CPU time 1.58 seconds
Started Mar 24 12:50:36 PM PDT 24
Finished Mar 24 12:50:38 PM PDT 24
Peak memory 201556 kb
Host smart-96c19fc7-db5c-490a-97f8-b2bfa588d0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328352400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2328352400
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3768268341
Short name T789
Test name
Test status
Simulation time 165169786960 ps
CPU time 103.13 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:52:14 PM PDT 24
Peak memory 201812 kb
Host smart-3a48dd03-7236-4b5d-aa3f-2494a1349e2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768268341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3768268341
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.76069937
Short name T516
Test name
Test status
Simulation time 580932285644 ps
CPU time 1344.02 seconds
Started Mar 24 12:50:37 PM PDT 24
Finished Mar 24 01:13:02 PM PDT 24
Peak memory 201836 kb
Host smart-15e079d9-9c15-411d-b4c0-314f6ec109aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76069937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.76069937
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3180465751
Short name T727
Test name
Test status
Simulation time 492068501653 ps
CPU time 483.61 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:58:32 PM PDT 24
Peak memory 201856 kb
Host smart-a73332ff-0d0e-4c7a-87e8-a9446fe037ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180465751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3180465751
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.308585988
Short name T395
Test name
Test status
Simulation time 499727249085 ps
CPU time 277.67 seconds
Started Mar 24 12:50:29 PM PDT 24
Finished Mar 24 12:55:06 PM PDT 24
Peak memory 202088 kb
Host smart-8a60d531-44f0-443a-b547-32151c9a2fb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=308585988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.308585988
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3838087621
Short name T774
Test name
Test status
Simulation time 336084668138 ps
CPU time 211.1 seconds
Started Mar 24 12:50:24 PM PDT 24
Finished Mar 24 12:53:56 PM PDT 24
Peak memory 201760 kb
Host smart-e6e3057e-1982-4158-8466-ce51daefe96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838087621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3838087621
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.166143439
Short name T598
Test name
Test status
Simulation time 489340763737 ps
CPU time 622.97 seconds
Started Mar 24 12:50:25 PM PDT 24
Finished Mar 24 01:00:48 PM PDT 24
Peak memory 201852 kb
Host smart-26de5d1f-68bd-4866-8288-7b3d03bd01be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=166143439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.166143439
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1700535316
Short name T731
Test name
Test status
Simulation time 188912488742 ps
CPU time 232.67 seconds
Started Mar 24 12:50:31 PM PDT 24
Finished Mar 24 12:54:23 PM PDT 24
Peak memory 201916 kb
Host smart-b1bd000e-c961-4d66-865a-2bfc3590e5a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700535316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1700535316
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1111109249
Short name T380
Test name
Test status
Simulation time 191978943175 ps
CPU time 174.54 seconds
Started Mar 24 12:50:21 PM PDT 24
Finished Mar 24 12:53:16 PM PDT 24
Peak memory 201860 kb
Host smart-41b577d3-822c-4fe7-ba50-ffc4231fc2a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111109249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1111109249
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.956518412
Short name T45
Test name
Test status
Simulation time 127951916263 ps
CPU time 433.22 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 12:57:40 PM PDT 24
Peak memory 202052 kb
Host smart-d82121df-9f1a-42a4-8de0-5de93c04489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956518412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.956518412
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1660378905
Short name T740
Test name
Test status
Simulation time 46769915621 ps
CPU time 20.65 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 201672 kb
Host smart-17b42522-bd1f-43ee-a3a0-c9b4c3052c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660378905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1660378905
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1321632942
Short name T540
Test name
Test status
Simulation time 4807198584 ps
CPU time 3.75 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:50:32 PM PDT 24
Peak memory 201624 kb
Host smart-6d348bbb-fca1-4abd-9161-58390dea2703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321632942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1321632942
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.359982914
Short name T378
Test name
Test status
Simulation time 5978683949 ps
CPU time 14.72 seconds
Started Mar 24 12:50:22 PM PDT 24
Finished Mar 24 12:50:37 PM PDT 24
Peak memory 201624 kb
Host smart-b466f644-8724-4235-99dd-49f7106cd981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359982914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.359982914
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2959291923
Short name T601
Test name
Test status
Simulation time 36232698560 ps
CPU time 88.43 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:51:57 PM PDT 24
Peak memory 218280 kb
Host smart-0e482ce7-7a1a-42e2-a7b7-21cee6c34f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959291923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2959291923
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1432357652
Short name T368
Test name
Test status
Simulation time 389587659 ps
CPU time 0.86 seconds
Started Mar 24 12:50:44 PM PDT 24
Finished Mar 24 12:50:46 PM PDT 24
Peak memory 201500 kb
Host smart-2dac1716-48f8-403f-bec2-9cfaf9dc9278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432357652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1432357652
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3081156608
Short name T282
Test name
Test status
Simulation time 329657055210 ps
CPU time 192.49 seconds
Started Mar 24 12:50:34 PM PDT 24
Finished Mar 24 12:53:46 PM PDT 24
Peak memory 201896 kb
Host smart-9460adac-eb31-4865-8445-920bdfc8d728
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081156608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3081156608
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.691846791
Short name T9
Test name
Test status
Simulation time 488009250921 ps
CPU time 1144.36 seconds
Started Mar 24 12:50:27 PM PDT 24
Finished Mar 24 01:09:32 PM PDT 24
Peak memory 201936 kb
Host smart-2724cb69-f5f5-4c73-8c91-f7cc8e9a4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691846791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.691846791
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4176528891
Short name T434
Test name
Test status
Simulation time 493426660509 ps
CPU time 222.94 seconds
Started Mar 24 12:50:28 PM PDT 24
Finished Mar 24 12:54:11 PM PDT 24
Peak memory 201848 kb
Host smart-e62525a8-7682-4e1a-83b9-87c1d6238086
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176528891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4176528891
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4209613426
Short name T314
Test name
Test status
Simulation time 494438406999 ps
CPU time 1213.61 seconds
Started Mar 24 12:50:30 PM PDT 24
Finished Mar 24 01:10:44 PM PDT 24
Peak memory 201748 kb
Host smart-9e77cc14-80b0-4259-b39d-0ddde7efa9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209613426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4209613426
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3122183746
Short name T102
Test name
Test status
Simulation time 485218295111 ps
CPU time 1191.75 seconds
Started Mar 24 12:50:31 PM PDT 24
Finished Mar 24 01:10:23 PM PDT 24
Peak memory 201816 kb
Host smart-cc2d82b5-dc48-40cf-a0f7-04ba5cd4ddaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122183746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3122183746
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1335379728
Short name T210
Test name
Test status
Simulation time 182034007696 ps
CPU time 140.54 seconds
Started Mar 24 12:50:31 PM PDT 24
Finished Mar 24 12:52:51 PM PDT 24
Peak memory 201796 kb
Host smart-05677475-cda5-40d5-be42-11ceea8fc91e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335379728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1335379728
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2021626394
Short name T24
Test name
Test status
Simulation time 195755325320 ps
CPU time 455.11 seconds
Started Mar 24 12:50:33 PM PDT 24
Finished Mar 24 12:58:08 PM PDT 24
Peak memory 201816 kb
Host smart-2ec2f65c-88bc-4100-b7bf-0124f93a7e7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021626394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2021626394
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.505176824
Short name T72
Test name
Test status
Simulation time 134302426142 ps
CPU time 713.13 seconds
Started Mar 24 12:50:34 PM PDT 24
Finished Mar 24 01:02:28 PM PDT 24
Peak memory 202220 kb
Host smart-aeb8a952-64e7-4a8d-b1d1-bd121fd2c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505176824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.505176824
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.554990822
Short name T585
Test name
Test status
Simulation time 32911821702 ps
CPU time 82.15 seconds
Started Mar 24 12:50:32 PM PDT 24
Finished Mar 24 12:51:54 PM PDT 24
Peak memory 201920 kb
Host smart-adad738a-232b-4a5b-8b17-f11261ab63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554990822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.554990822
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1351385635
Short name T369
Test name
Test status
Simulation time 4295134306 ps
CPU time 3.31 seconds
Started Mar 24 12:50:32 PM PDT 24
Finished Mar 24 12:50:36 PM PDT 24
Peak memory 201644 kb
Host smart-aa8d5b51-4034-4954-8894-bbc647bfe2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351385635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1351385635
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1048182263
Short name T466
Test name
Test status
Simulation time 5987945845 ps
CPU time 14.46 seconds
Started Mar 24 12:50:36 PM PDT 24
Finished Mar 24 12:50:51 PM PDT 24
Peak memory 201676 kb
Host smart-24c2cc2e-c0b9-49ed-abdf-8dc4e07697fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048182263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1048182263
Directory /workspace/9.adc_ctrl_smoke/latest
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