Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7368	1			T3	45		T9	20		T10	45
testmodes[AdcCtrlTestmodeNormal]	5871	1			T1	3		T2	1		T3	54
testmodes[AdcCtrlTestmodeLowpower]	5943	1			T3	49		T4	2		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3860	1			T3	12		T9	19		T10	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1933	1			T3	13		T10	13		T11	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1477	1			T3	20		T10	18		T12	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1916	1			T3	15		T10	15		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2158	1			T1	2		T3	23		T8	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1447	1			T3	15		T10	12		T12	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1476	1			T3	18		T10	16		T12	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1446	1			T3	18		T7	1		T10	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2770	1			T3	13		T4	1		T6	2