Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23640

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3564

1

T1

2

T4

11

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21344

1

T1

3

T3

148

T7

1

auto[1]

5860

1

T2

1

T4

30

T5

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T240	1		T241	1		T182	2
values[0]	139	1			T144	33		T145	30		T242	16
values[1]	640	1			T1	2		T45	8		T36	15
values[2]	570	1			T6	10		T12	10		T32	23
values[3]	540	1			T7	37		T8	13		T45	11
values[4]	2822	1			T2	1		T5	16		T6	4
values[5]	667	1			T39	4		T139	1		T59	28
values[6]	515	1			T73	1		T96	14		T138	5
values[7]	736	1			T4	19		T6	19		T7	1
values[8]	768	1			T1	1		T37	1		T96	8
values[9]	1547	1			T4	11		T11	1		T45	17
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	953	1			T1	2		T6	10		T45	8
values[1]	456	1			T12	10		T32	23		T38	1
values[2]	570	1			T7	37		T8	13		T45	11
values[3]	2916	1			T2	1		T5	16		T6	4
values[4]	682	1			T96	14		T59	28		T243	6
values[5]	581	1			T6	19		T73	1		T138	5
values[6]	717	1			T1	1		T4	19		T7	1
values[7]	809	1			T4	11		T45	17		T49	9
values[8]	1105	1			T11	1		T50	32		T138	31
values[9]	161	1			T38	2		T244	11		T245	1
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T6	10		T50	12		T137	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	2		T45	5		T36	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T32	10		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T219	1		T246	8		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T213	1		T59	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	26		T8	1		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T2	1		T5	16		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	1		T144	12		T91	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T96	2		T59	14		T246	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T243	6		T157	1		T160	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T138	3		T40	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	19		T73	1		T145	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	1		T4	19		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T37	1		T49	17		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	9		T26	1		T247	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	11		T45	13		T243	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T138	16		T90	1		T248	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	1		T50	16		T91	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T38	1		T244	5		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T249	11		T216	9		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T50	16		T137	3		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T45	3		T36	6		T144	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	9		T32	13		T91	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T246	2		T158	4		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T59	10		T100	7		T202	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	11		T8	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T43	12		T44	23		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	13		T144	14		T91	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T96	12		T59	14		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T160	10		T252	2		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	2		T141	18		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T145	11		T164	3		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T96	7		T139	10		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	9		T48	4		T254	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	2		T247	1		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	4		T158	2		T255	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T138	15		T248	14		T256	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T50	16		T91	6		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T38	1		T244	6		T257	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T258	4		T259	17		T260	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T240	1		T241	1		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T242	7		T261	8		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T144	17		T145	18		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T50	12		T137	7		T138	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	2		T45	5		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	10		T12	1		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T219	1		T146	1		T158	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	1		T59	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	26		T8	1		T45	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T2	1		T5	16		T6	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T144	12		T91	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T59	14		T246	3		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	3		T139	1		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T96	2		T138	3		T248	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T73	1		T263	9		T264	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	19		T7	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	19		T49	17		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T96	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T37	1		T243	9		T158	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	478	1			T49	9		T138	16		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T4	11		T11	1		T45	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T182	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T242	9		T261	5		T265	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T144	16		T145	12		T24	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	16		T137	3		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T45	3		T36	6		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	9		T32	13		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T158	4		T189	9		T220	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T59	10		T147	8		T100	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T7	11		T8	12		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T43	12		T44	23		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	13		T144	14		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	14		T251	12		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T39	1		T160	11		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T96	12		T138	2		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T147	1		T253	11		T266	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T141	18		T18	2		T267	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	9		T145	11		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T96	7		T26	2		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T158	2		T48	4		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T138	15		T38	1		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T45	4		T50	16		T91	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	1		T50	17		T137	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	2		T45	4		T36	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	10		T32	14		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T219	1		T246	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T213	1		T59	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	13		T8	13		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T2	1		T5	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	14		T144	15		T91	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T96	14		T59	15		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T243	1		T157	1		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	3		T40	1		T141	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T73	1		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T4	1		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T37	1		T49	1		T50	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T49	1		T26	3		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T45	5		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T138	16		T90	1		T248	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T11	1		T50	17		T91	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T38	2		T244	7		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T249	1		T216	1		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	9		T50	11		T137	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	4		T36	4		T144	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	9		T91	10		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T246	7		T158	5		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T59	10		T269	3		T270	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	24		T45	10		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T5	15		T6	3		T46	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	11		T91	8		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T59	13		T246	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T243	5		T160	8		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T138	2		T40	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	18		T145	9		T263	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T4	18		T248	10		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	16		T50	13		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	8		T247	3		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	10		T45	12		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T138	15		T248	14		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	15		T91	8		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T244	4		T271	11		T185	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T249	10		T216	8		T272	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T240	1		T241	1		T182	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T242	10		T261	6		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T144	17		T145	13		T24	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T50	17		T137	4		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	2		T45	4		T36	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T12	10		T32	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T219	1		T146	1		T158	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	1		T59	11		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	13		T8	13		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	1		T5	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	14		T144	15		T91	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T59	15		T246	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T39	3		T139	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T96	14		T138	3		T248	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T73	1		T263	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T7	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T49	1		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T96	8		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T37	1		T243	1		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T49	1		T138	16		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T4	1		T11	1		T45	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T242	6		T261	7		T273	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T144	16		T145	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	11		T137	6		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T45	4		T36	4		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	9		T32	9		T91	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T158	5		T142	1		T189	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T59	10		T17	1		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	24		T45	10		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T5	15		T6	3		T46	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	11		T91	8		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T59	13		T246	2		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	1		T243	5		T160	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T138	2		T248	10		T48	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T263	8		T264	1		T253	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T4	18		T40	1		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	18		T49	16		T50	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T247	3		T17	2		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T243	8		T158	3		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T49	8		T138	15		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T4	10		T45	12		T50	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23613

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T1

1

T6

33

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21323

1

T1

1

T3

148

T6

14

auto[1]

5881

1

T1

2

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T274	1		T275	10		T276	17
values[0]	27	1			T254	1		T277	12		T185	11
values[1]	611	1			T8	13		T45	19		T37	3
values[2]	576	1			T138	31		T85	11		T247	5
values[3]	765	1			T4	11		T38	2		T91	13
values[4]	690	1			T4	19		T7	18		T50	28
values[5]	2871	1			T2	1		T5	16		T7	1
values[6]	696	1			T1	1		T6	29		T7	19
values[7]	831	1			T49	9		T144	33		T138	5
values[8]	668	1			T11	1		T37	1		T49	17
values[9]	1187	1			T1	2		T6	4		T8	14
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	727	1			T8	13		T45	11		T37	3
values[1]	699	1			T45	8		T138	31		T278	1
values[2]	694	1			T4	30		T85	11		T38	2
values[3]	2908	1			T2	1		T5	16		T13	2
values[4]	641	1			T7	38		T12	10		T45	17
values[5]	768	1			T1	1		T6	29		T90	1
values[6]	837	1			T11	1		T37	1		T49	9
values[7]	645	1			T8	14		T49	17		T139	1
values[8]	822	1			T1	1		T6	4		T50	32
values[9]	191	1			T1	1		T142	9		T264	2
minimum	18272	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	2		T144	3		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	1		T45	11		T50	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T142	13		T143	25		T166	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	5		T138	16		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	30		T91	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T85	1		T38	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T2	1		T5	16		T13	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	12		T138	5		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	16		T45	13		T73	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	11		T12	1		T36	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T90	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	29		T91	9		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	1		T37	1		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T96	2		T144	17		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	1		T48	6		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	17		T139	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T50	16		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	4		T26	1		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T142	9		T279	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T1	1		T264	2		T280	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18131	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	1		T144	12		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	12		T50	9		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T166	6		T168	14		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T45	3		T138	15		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T91	2		T141	2		T281	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T85	10		T38	1		T59	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T43	12		T44	23		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	16		T138	2		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	3		T45	4		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	8		T12	9		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T164	3		T147	10		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T91	6		T159	11		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T91	4		T160	8		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T96	17		T144	16		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	13		T48	4		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T158	4		T147	1		T282	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	16		T144	14		T137	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	2		T145	12		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T279	1		T170	12		T283	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T280	1		T284	5		T24	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T36	7		T73	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	1		T275	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T276	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T254	1		T277	1		T185	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T37	2		T144	3		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T45	16		T50	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T247	4		T17	4		T142	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	16		T85	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	11		T91	11		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	1		T59	14		T248	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	19		T263	13		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	10		T50	12		T138	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T2	1		T5	16		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T12	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T7	16		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	29		T36	9		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T49	9		T87	12		T91	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T144	17		T138	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	1		T37	1		T209	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T49	17		T96	1		T243	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T1	1		T8	1		T50	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	1		T6	4		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T275	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T276	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T277	11		T285	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T37	1		T144	12		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	12		T45	3		T50	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T247	1		T17	3		T166	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T138	15		T85	10		T286	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T91	2		T141	2		T287	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	1		T59	14		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T281	6		T288	26		T202	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	8		T50	16		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T43	12		T44	23		T45	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	9		T96	2		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	3		T147	8		T289	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	6		T96	7		T91	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	4		T164	3		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T144	16		T138	2		T256	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T209	7		T158	14		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T96	10		T147	1		T290	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	13		T50	16		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T26	2		T145	12		T139	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1