Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23597

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3607

1

T1

1

T4

19

T6

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21371

1

T1

2

T3

148

T6

4

auto[1]

5833

1

T1

1

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T334	1		T347	23		T348	20
values[0]	60	1			T59	21		T170	1		T261	13
values[1]	557	1			T7	18		T73	1		T138	5
values[2]	720	1			T11	1		T45	28		T49	9
values[3]	756	1			T50	28		T39	4		T213	1
values[4]	775	1			T1	1		T4	11		T8	14
values[5]	2818	1			T2	1		T4	19		T5	16
values[6]	534	1			T85	11		T91	26		T145	21
values[7]	833	1			T1	1		T6	4		T138	7
values[8]	763	1			T7	19		T8	13		T144	26
values[9]	1090	1			T1	1		T6	10		T12	10
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T7	18		T11	1		T45	17
values[1]	779	1			T45	11		T137	10		T26	3
values[2]	562	1			T50	28		T96	3		T144	15
values[3]	3039	1			T1	1		T2	1		T4	30
values[4]	656	1			T6	19		T50	23		T96	19
values[5]	557	1			T7	1		T138	7		T91	26
values[6]	866	1			T1	1		T6	4		T7	19
values[7]	771	1			T6	10		T8	13		T37	1
values[8]	782	1			T12	10		T50	32		T91	15
values[9]	141	1			T1	1		T45	8		T145	30
minimum	18283	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	10		T11	1		T45	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	17		T90	1		T59	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T137	7		T26	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	11		T213	1		T146	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T96	1		T213	1		T243	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	12		T144	3		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T1	1		T2	1		T4	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T4	19		T32	10		T87	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T96	1		T138	16		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	19		T50	14		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	1		T141	1		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	5		T91	20		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	1		T7	16		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	4		T144	12		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	10		T89	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	1		T37	1		T49	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T91	9		T209	3		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T50	16		T246	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T45	5		T147	5		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T1	1		T145	18		T349	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18124	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T242	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	8		T45	4		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T144	16		T59	10		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T137	3		T26	2		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T146	9		T164	1		T291	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T96	2		T160	1		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	16		T144	12		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T8	13		T43	12		T44	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T32	13		T247	1		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T96	7		T138	15		T85	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T50	9		T96	10		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T141	13		T282	11		T266	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	2		T91	6		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	3		T158	14		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T144	14		T145	11		T59	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	10		T158	2		T289	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	12		T281	6		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T91	6		T209	7		T255	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	9		T50	16		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T45	3		T147	2		T100	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T145	12		T350	1		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T242	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T347	9		T348	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T170	1		T261	8		T283	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T59	11		T351	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	10		T73	1		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T90	1		T164	1		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T45	13		T49	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	11		T144	17		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T213	1		T246	3		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T50	12		T39	3		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T4	11		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T144	3		T32	10		T87	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T2	1		T5	16		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	19		T6	19		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T85	1		T141	1		T282	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T91	20		T145	10		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	1		T243	6		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	4		T138	5		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	16		T89	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T144	12		T281	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T6	10		T45	5		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T1	1		T12	1		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T347	14		T348	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T261	5		T283	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T59	10		T351	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	8		T138	2		T248	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T164	1		T159	11		T287	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	4		T137	3		T26	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T144	16		T146	9		T291	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T160	1		T147	8		T289	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	16		T39	1		T286	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	13		T37	1		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T144	12		T32	13		T247	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T43	12		T44	23		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	9		T96	10		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T85	10		T141	13		T282	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T91	6		T145	11		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	14		T289	6		T220	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T138	2		T59	14		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T158	2		T147	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	12		T144	14		T281	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	3		T91	6		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	9		T50	16		T145	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	9		T11	1		T45	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	17		T90	1		T59	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T137	4		T26	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	1		T213	1		T146	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T96	3		T213	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T50	17		T144	13		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T1	1		T2	1		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T4	1		T32	14		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T96	8		T138	16		T85	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T50	10		T96	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T141	14		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	3		T91	8		T164	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T7	4		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T144	15		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T89	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	13		T37	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T91	7		T209	8		T278	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	10		T50	17		T246	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T45	4		T147	3		T100	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T1	1		T145	13		T349	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18260	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T242	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	9		T45	12		T49	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	16		T59	10		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	6		T263	3		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	10		T146	2		T264	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T243	8		T246	2		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	11		T144	2		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T4	10		T5	15		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T4	18		T32	9		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	15		T160	8		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	18		T50	13		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T293	17		T282	2		T294	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	4		T91	18		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	15		T243	5		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	3		T144	11		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	9		T263	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	16		T140	17		T281	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T91	8		T209	2		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	15		T246	7		T160	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T45	4		T147	4		T352	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T145	17		T353	8		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T261	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T242	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T347	15		T348	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T170	1		T261	6		T283	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T59	11		T351	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	9		T73	1		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T90	1		T164	2		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	1		T45	5		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	1		T144	17		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T213	1		T246	1		T160	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T50	17		T39	3		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	1		T4	1		T8	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T144	13		T32	14		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T2	1		T5	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	1		T6	1		T50	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T85	11		T141	14		T282	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T91	8		T145	12		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	1		T243	1		T158	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T138	3		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	4		T89	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	13		T144	15		T281	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T6	1		T45	4		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T1	1		T12	10		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T347	8		T348	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T261	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T59	10		T351	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	9		T138	2		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T159	11		T242	6		T169	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	12		T49	8		T137	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	10		T144	16		T146	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T246	2		T160	12		T264	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T50	11		T39	1		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	10		T37	1		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T144	2		T32	9		T87	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T5	15		T36	4		T46	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	18		T6	18		T50	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T282	2		T217	2		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T91	18		T145	9		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T243	5		T158	10		T293	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	3		T138	4		T59	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	15		T263	8		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T144	11		T281	2		T293	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	9		T45	4		T91	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T49	16		T50	15		T145	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30