Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23671

1

T1

3

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3533

1

T6

29

T7

19

T8

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21254

1

T1

1

T3

143

T4

11

auto[1]

5950

1

T1

2

T2

1

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	612	1			T3	5		T7	19		T10	6
values[0]	72	1			T310	11		T317	1		T203	18
values[1]	643	1			T1	1		T45	17		T38	1
values[2]	2745	1			T2	1		T5	16		T13	2
values[3]	747	1			T7	1		T45	11		T49	17
values[4]	608	1			T1	1		T4	11		T6	10
values[5]	674	1			T6	4		T36	15		T37	3
values[6]	827	1			T4	19		T6	19		T73	1
values[7]	749	1			T50	32		T32	23		T89	1
values[8]	754	1			T8	13		T11	1		T138	5
values[9]	1021	1			T1	1		T12	10		T138	31
minimum	17752	1			T3	143		T9	20		T10	122

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T1	1		T45	17		T96	14
values[1]	2668	1			T2	1		T5	16		T13	2
values[2]	633	1			T7	1		T45	19		T49	17
values[3]	750	1			T1	1		T4	11		T6	10
values[4]	677	1			T6	4		T36	15		T144	33
values[5]	857	1			T4	19		T6	19		T37	3
values[6]	788	1			T8	13		T11	1		T50	32
values[7]	649	1			T12	10		T138	36		T87	12
values[8]	931	1			T1	1		T7	19		T37	1
values[9]	55	1			T279	2		T92	12		T183	5
minimum	18417	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T45	13		T96	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T59	11		T146	3		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T2	1		T5	16		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T96	1		T243	9		T247	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	1		T49	17		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	16		T144	12		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T4	11		T7	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	10		T8	1		T50	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	4		T144	17		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	9		T26	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T4	19		T37	2		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	19		T73	1		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T50	16		T32	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T160	28		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T138	16		T91	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T138	3		T87	12		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	1		T37	1		T91	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T7	16		T158	11		T140	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T92	6		T354	1		T231	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T279	1		T183	1		T355	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18119	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T157	1		T267	1		T292	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	4		T96	12		T257	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T59	10		T146	9		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T43	12		T44	23		T137	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T96	7		T247	1		T220	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T145	11		T59	14		T18	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	3		T144	14		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	8		T85	10		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	13		T50	25		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	16		T248	2		T147	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T36	6		T26	2		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	1		T144	12		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	3		T147	2		T244	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T50	16		T32	13		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	12		T160	9		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	9		T138	15		T91	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T138	2		T158	4		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T91	4		T147	8		T289	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	3		T158	14		T48	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T92	6		T231	8		T320	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T279	1		T183	4		T355	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T267	3		T309	11		T356	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	523	1			T3	5		T10	6		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T7	16		T104	16		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T310	11		T203	9		T324	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T317	1		T323	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T1	1		T45	13		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T59	11		T146	3		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T2	1		T5	16		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T96	1		T243	9		T247	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	1		T49	17		T145	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	11		T144	12		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T4	11		T7	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	10		T8	1		T45	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	4		T37	2		T144	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	9		T26	1		T91	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	19		T144	3		T138	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	19		T73	1		T49	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T50	16		T32	10		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T160	28		T143	28		T269	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T91	11		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T138	3		T87	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T1	1		T12	1		T138	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T158	11		T140	18		T142	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17614	1			T3	143		T9	20		T10	122
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T91	4		T357	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T7	3		T104	2		T202	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T203	9		T324	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T323	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	4		T288	26		T100	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T59	10		T146	9		T267	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T43	12		T44	23		T96	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T96	7		T247	1		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T145	11		T59	14		T167	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T144	14		T164	11		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	8		T18	8		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T8	13		T45	3		T50	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	1		T144	16		T85	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	6		T26	2		T91	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T144	12		T138	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	3		T147	2		T244	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	16		T32	13		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T160	9		T253	11		T287	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	2		T164	3		T166	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	12		T138	2		T158	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	9		T138	15		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T158	14		T48	4		T254	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T45	5		T96	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T59	11		T146	10		T141	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T2	1		T5	1		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T96	8		T243	1		T247	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T49	1		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	5		T144	15		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T4	1		T7	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	1		T8	14		T50	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T144	17		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T36	11		T26	3		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	1		T37	2		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T73	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	1		T50	17		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	13		T160	11		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	10		T138	16		T91	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	3		T87	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T37	1		T91	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	4		T158	15		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T92	9		T354	1		T231	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T279	2		T183	5		T355	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18278	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T157	1		T267	4		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	12		T263	8		T190	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T59	10		T146	2		T142	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T5	15		T46	33		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T243	8		T247	3		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T49	16		T145	9		T59	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	14		T144	11		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	10		T7	9		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	9		T50	24		T91	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	3		T144	16		T243	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T36	4		T209	2		T263	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	18		T37	1		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	18		T49	8		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T50	15		T32	9		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T160	26		T143	13		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	15		T91	10		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	2		T87	11		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T91	8		T147	8		T293	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	15		T158	10		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T92	3		T231	8		T320	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T328	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T292	15		T309	18		T316	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	521	1			T3	5		T10	6		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T7	4		T104	3		T202	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T310	1		T203	10		T324	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T317	1		T323	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T45	5		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T59	11		T146	10		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T2	1		T5	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T96	8		T243	1		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T49	1		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T45	1		T144	15		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T4	1		T7	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	1		T8	14		T45	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T37	2		T144	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T36	11		T26	3		T91	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	1		T144	13		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	1		T73	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	17		T32	14		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T160	11		T143	2		T269	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	1		T91	3		T164	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	13		T138	3		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T12	10		T138	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T158	15		T140	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17752	1			T3	143		T9	20		T10	122
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T91	8		T357	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T7	15		T104	15		T358	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T310	10		T203	8		T324	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T323	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T45	12		T311	9		T294	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T59	10		T146	2		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T5	15		T46	33		T137	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T243	8		T247	3		T264	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T49	16		T145	9		T59	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T45	10		T144	11		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	10		T7	9		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	9		T45	4		T50	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	3		T37	1		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	4		T91	8		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	18		T144	2		T138	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	18		T49	8		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T50	15		T32	9		T145	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T160	26		T143	26		T269	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T91	10		T164	9		T269	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	2		T87	11		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T138	15		T147	8		T293	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T158	10		T140	17		T142	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30