Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23783

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T1

1

T4

19

T6

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21313

1

T1

2

T3

148

T6

4

auto[1]

5891

1

T1

1

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T12	10		T45	8		T168	19
values[0]	38	1			T59	21		T215	1		T261	13
values[1]	595	1			T7	18		T73	1		T138	5
values[2]	721	1			T11	1		T45	28		T49	9
values[3]	730	1			T50	28		T144	15		T26	3
values[4]	741	1			T1	1		T4	11		T8	14
values[5]	2830	1			T2	1		T4	19		T5	16
values[6]	551	1			T50	23		T85	11		T91	26
values[7]	891	1			T1	1		T6	4		T138	7
values[8]	705	1			T7	19		T8	13		T144	26
values[9]	840	1			T1	1		T6	10		T37	1
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T7	18		T11	1		T45	28
values[1]	736	1			T137	10		T26	3		T38	2
values[2]	627	1			T50	28		T144	15		T39	4
values[3]	2988	1			T1	1		T2	1		T4	30
values[4]	677	1			T6	19		T7	1		T50	23
values[5]	517	1			T138	7		T91	13		T164	13
values[6]	937	1			T1	1		T6	4		T7	19
values[7]	688	1			T6	10		T8	13		T49	17
values[8]	854	1			T12	10		T37	1		T50	32
values[9]	103	1			T1	1		T45	8		T292	16
minimum	18440	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	10		T45	13		T73	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T45	11		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T137	7		T26	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T213	1		T146	3		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T213	1		T243	9		T246	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	12		T144	3		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T1	1		T2	1		T4	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T4	19		T32	10		T87	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T50	14		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	19		T96	1		T91	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T138	5		T141	1		T293	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T91	9		T164	10		T166	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T7	16		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T6	4		T16	3		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	10		T89	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	1		T49	17		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	1		T91	9		T209	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	1		T50	16		T145	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T45	5		T292	16		T352	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T1	1		T199	1		T342	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18154	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T90	1		T159	12		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	8		T45	4		T48	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	16		T287	10		T169	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T137	3		T26	2		T38	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	9		T164	1		T291	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T158	4		T160	1		T141	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	16		T144	12		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T8	13		T43	12		T44	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T32	13		T247	1		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	9		T96	7		T138	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T96	10		T91	2		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T138	2		T141	13		T282	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T91	4		T164	3		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	3		T289	6		T257	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T145	11		T59	14		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T139	10		T158	2		T281	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	12		T144	14		T244	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	9		T91	6		T209	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	16		T145	12		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T45	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T199	4		T342	9		T350	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T159	11		T248	2		T242	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	1		T45	5		T168	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T325	1		T359	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T59	11		T261	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T215	1		T283	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	10		T73	1		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T90	1		T219	1		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	13		T49	9		T137	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T45	11		T144	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	1		T213	1		T246	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T50	12		T144	3		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T4	11		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T32	10		T87	12		T247	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T2	1		T5	16		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	19		T6	19		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T50	14		T85	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T91	20		T164	10		T166	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	1		T138	5		T243	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	4		T16	3		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	16		T89	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	1		T144	12		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	10		T38	1		T91	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	1		T37	1		T49	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	9		T45	3		T168	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T325	1		T359	13		T199	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T59	10		T261	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T283	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	8		T138	2		T48	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T159	11		T248	2		T287	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	4		T137	3		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	16		T146	9		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	2		T158	4		T160	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	16		T144	12		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	13		T37	1		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	13		T247	1		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T43	12		T44	23		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T96	10		T17	3		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T50	9		T85	10		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T91	6		T164	3		T166	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T138	2		T289	6		T220	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T145	11		T59	14		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	3		T158	2		T281	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T8	12		T144	14		T147	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T91	6		T139	10		T209	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	16		T145	12		T246	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	9		T45	5		T73	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T45	1		T144	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T137	4		T26	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T213	1		T146	10		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T213	1		T243	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	17		T144	13		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	1		T2	1		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	1		T32	14		T87	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T50	10		T96	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	1		T96	11		T91	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	3		T141	14		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T91	5		T164	4		T166	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T7	4		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	1		T16	3		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	1		T89	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	13		T49	1		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	10		T91	7		T209	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	1		T50	17		T145	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T45	4		T292	1		T352	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T1	1		T199	5		T342	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18300	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T90	1		T159	12		T248	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	9		T45	12		T49	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	10		T144	16		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	6		T263	3		T290	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	2		T40	1		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T243	8		T246	2		T158	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T50	11		T144	2		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T4	10		T5	15		T36	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	18		T32	9		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T50	13		T138	15		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	18		T91	10		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	4		T293	17		T282	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T91	8		T164	9		T292	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	15		T243	5		T293	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	3		T145	9		T59	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	9		T263	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T49	16		T144	11		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T91	8		T209	2		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T50	15		T145	17		T246	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T45	4		T292	15		T352	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T353	8		T260	2		T348	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T138	2		T59	10		T303	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T159	11		T248	10		T242	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	10		T45	4		T168	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T325	2		T359	14		T199	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T59	11		T261	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T215	1		T283	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	9		T73	1		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T90	1		T219	1		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	5		T49	1		T137	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T45	1		T144	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	3		T213	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	17		T144	13		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	1		T4	1		T8	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T32	14		T87	1		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T2	1		T5	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T6	1		T96	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	10		T85	11		T141	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T91	8		T164	4		T166	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T138	3		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	1		T16	3		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	4		T89	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	13		T144	15		T147	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T38	1		T91	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T37	1		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T45	4		T168	9		T292	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T304	15		T360	11		T348	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T59	10		T261	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	9		T138	2		T143	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T159	11		T248	10		T242	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	12		T49	8		T137	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	10		T144	16		T146	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T246	2		T158	5		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	11		T144	2		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	10		T37	1		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T32	9		T87	11		T247	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	15		T36	4		T46	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	18		T6	18		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T50	13		T282	2		T217	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T91	18		T164	9		T292	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	4		T243	5		T293	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	3		T145	9		T59	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	15		T263	8		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T144	11		T269	3		T244	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	9		T91	8		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T49	16		T50	15		T145	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30