Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23921

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3283

1

T1

2

T4

30

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21109

1

T1

1

T3

148

T4

11

auto[1]

6095

1

T1

2

T2

1

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	287	1			T248	29		T141	14		T221	10
values[0]	20	1			T327	11		T329	1		T296	1
values[1]	745	1			T1	1		T4	11		T6	19
values[2]	544	1			T8	14		T12	10		T73	1
values[3]	745	1			T50	28		T89	1		T91	15
values[4]	520	1			T11	1		T36	15		T49	9
values[5]	759	1			T7	18		T8	13		T49	17
values[6]	673	1			T6	10		T7	19		T137	10
values[7]	740	1			T1	1		T4	19		T37	1
values[8]	545	1			T6	4		T7	1		T37	3
values[9]	3372	1			T1	1		T2	1		T5	16
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T1	1		T4	11		T6	19
values[1]	552	1			T8	14		T12	10		T73	1
values[2]	767	1			T50	28		T96	3		T138	31
values[3]	531	1			T11	1		T36	15		T49	26
values[4]	772	1			T7	18		T8	13		T50	32
values[5]	693	1			T1	1		T4	19		T6	10
values[6]	2786	1			T2	1		T5	16		T13	2
values[7]	642	1			T6	4		T7	1		T37	3
values[8]	1114	1			T1	1		T45	19		T96	8
values[9]	178	1			T26	3		T91	13		T18	1
minimum	18426	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	19		T45	13		T87	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T4	11		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T252	1		T255	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T73	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T50	12		T138	16		T91	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T96	1		T89	1		T140	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T263	9		T147	5		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T36	9		T49	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	1		T90	1		T59	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	10		T50	16		T209	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T7	16		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	19		T6	10		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T2	1		T5	16		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	1		T18	12		T264	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T37	2		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	4		T96	1		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T45	16		T144	17		T246	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T1	1		T96	1		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T91	9		T18	1		T220	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T26	1		T225	1		T361	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18167	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T47	2		T253	13		T168	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T45	4		T160	1		T167	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	1		T59	14		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	13		T255	2		T289	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	9		T158	4		T102	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T50	16		T138	15		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T96	2		T18	2		T189	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	2		T48	4		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	6		T164	10		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	12		T59	10		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	8		T50	16		T209	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	3		T138	2		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	9		T137	3		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T43	12		T44	23		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T18	8		T166	6		T281	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	1		T146	9		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T96	10		T85	10		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T45	3		T144	16		T164	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T96	7		T144	14		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T91	4		T220	5		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T26	2		T225	1		T361	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	11		T168	5		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T221	1		T241	1		T251	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T248	15		T141	1		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T329	1		T328	5		T362	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T327	11		T296	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	19		T45	13		T87	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T4	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T8	1		T243	9		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T73	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T50	12		T91	9		T243	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T89	1		T140	18		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T138	16		T91	11		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T36	9		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T90	1		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	10		T49	17		T50	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	16		T138	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	10		T137	7		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T145	10		T139	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	19		T37	1		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T37	2		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	4		T85	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T2	1		T5	16		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T1	1		T96	2		T144	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T221	9		T251	12		T181	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T248	14		T141	13		T225	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T328	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T45	4		T39	1		T160	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T38	1		T59	14		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	13		T255	2		T257	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	9		T158	4		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	16		T91	6		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T18	2		T92	6		T351	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	15		T91	2		T147	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	6		T96	2		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	12		T59	10		T252	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	8		T50	16		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	3		T138	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	3		T209	7		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T145	11		T139	10		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T50	9		T248	2		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T37	1		T144	12		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T85	10		T17	3		T166	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T43	12		T44	23		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T96	17		T144	14		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T45	5		T87	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T4	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	14		T252	1		T255	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	10		T73	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T50	17		T138	16		T91	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T96	3		T89	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T263	1		T147	3		T48	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T36	11		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	13		T90	1		T59	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	9		T50	17		T209	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T7	4		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T6	1		T50	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T5	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	1		T18	12		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T37	2		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T96	11		T85	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T45	5		T144	17		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T1	1		T96	8		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T91	5		T18	1		T220	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T26	3		T225	2		T361	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18344	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T47	2		T253	12		T168	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	18		T45	12		T87	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	10		T59	13		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T289	7		T292	15		T170	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T158	5		T143	13		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T50	11		T138	15		T91	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	17		T18	1		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T263	8		T147	4		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T36	4		T49	24		T263	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	10		T252	10		T269	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	9		T50	15		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	15		T138	2		T246	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	18		T6	9		T50	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T5	15		T46	33		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T18	8		T264	1		T281	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T37	1		T146	2		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	3		T145	17		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	14		T144	16		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T144	11		T32	9		T160	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T91	8		T220	3		T242	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T361	3		T330	2		T331	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T39	1		T40	1		T182	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T253	12		T168	4		T327	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T221	10		T241	1		T251	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T248	15		T141	14		T225	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T329	1		T328	2		T362	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T327	1		T296	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	1		T45	5		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T4	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	14		T243	1		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	10		T73	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T50	17		T91	7		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T89	1		T140	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T138	16		T91	3		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T36	11		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	13		T90	1		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	9		T49	1		T50	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	4		T138	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T137	4		T209	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T145	12		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	1		T37	1		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T37	2		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T85	11		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T2	1		T5	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T1	1		T96	19		T144	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T251	12		T363	12		T324	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T248	14		T251	12		T361	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T328	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T327	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	18		T45	12		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	10		T59	13		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T243	8		T292	15		T270	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T158	5		T143	13		T252	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T50	11		T91	8		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	17		T18	1		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	15		T91	10		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T36	4		T49	8		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T59	10		T263	8		T252	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	9		T49	16		T50	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	15		T138	2		T246	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	9		T137	6		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T145	9		T164	9		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	18		T50	13		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	1		T144	2		T138	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T6	3		T17	2		T298	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T5	15		T45	14		T46	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T144	11		T32	9		T145	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30