Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23552

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3652

1

T1

2

T6

19

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21186

1

T1

1

T3

148

T6

23

auto[1]

6018

1

T1

2

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T26	3		T270	11		T364	14
values[0]	72	1			T148	1		T245	1		T104	18
values[1]	740	1			T6	4		T45	8		T16	3
values[2]	2935	1			T2	1		T4	19		T5	16
values[3]	615	1			T1	2		T11	1		T91	15
values[4]	549	1			T89	1		T146	12		T164	21
values[5]	693	1			T4	11		T73	1		T138	31
values[6]	565	1			T7	19		T144	26		T137	10
values[7]	738	1			T6	10		T7	1		T37	3
values[8]	651	1			T6	19		T37	1		T50	23
values[9]	1350	1			T1	1		T7	18		T8	14
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1059	1			T6	4		T8	13		T45	8
values[1]	2735	1			T1	1		T2	1		T4	19
values[2]	606	1			T1	1		T213	1		T246	10
values[3]	579	1			T138	31		T89	1		T146	12
values[4]	761	1			T4	11		T7	19		T73	1
values[5]	613	1			T96	3		T144	26		T138	7
values[6]	726	1			T6	10		T7	1		T37	3
values[7]	586	1			T45	17		T37	1		T87	12
values[8]	1034	1			T1	1		T6	19		T7	18
values[9]	218	1			T8	14		T221	10		T19	1
minimum	18287	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T6	4		T45	5		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T8	1		T96	1		T32	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	1		T2	1		T4	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	9		T144	3		T91	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T246	8		T157	1		T140	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T213	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T138	16		T89	1		T158	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	3		T164	11		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	11		T7	16		T246	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T73	1		T145	10		T59	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	12		T38	1		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T96	1		T138	5		T91	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	10		T37	2		T137	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T50	14		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T87	12		T90	1		T263	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	13		T37	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	10		T12	1		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	1		T6	19		T49	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T221	1		T298	10		T365	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T8	1		T19	1		T298	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18123	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T305	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T45	3		T59	10		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	12		T96	10		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T43	12		T44	23		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T36	6		T144	12		T91	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T246	2		T100	7		T361	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T289	15		T257	13		T359	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	15		T158	2		T141	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T146	9		T164	10		T160	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	3		T164	3		T195	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T145	11		T59	14		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	14		T164	1		T257	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T96	2		T138	2		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	1		T137	3		T158	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	9		T39	1		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T160	10		T248	2		T20	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	4		T38	1		T289	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	8		T12	9		T50	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T50	16		T144	16		T91	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T221	9		T298	10		T365	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T8	13		T298	10		T261	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T305	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T26	1		T270	11		T364	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T366	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T245	1		T367	7		T368	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T148	1		T104	16		T360	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	4		T45	5		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T32	10		T158	6		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T2	1		T4	19		T5	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	1		T36	9		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	1		T11	1		T246	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	1		T91	9		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T89	1		T140	18		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	3		T164	11		T248	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	11		T138	16		T246	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T73	1		T145	10		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	16		T144	12		T137	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T91	11		T59	14		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	10		T37	2		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T96	1		T138	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T87	12		T90	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	19		T37	1		T50	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T7	10		T12	1		T45	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T1	1		T8	1		T45	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T26	2		T364	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T366	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T367	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T104	2		T360	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	3		T17	3		T141	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T32	13		T158	4		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T43	12		T44	23		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	12		T36	6		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T246	2		T100	7		T361	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T91	6		T289	15		T257	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T141	18		T48	4		T168	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T146	9		T164	10		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	15		T164	3		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	11		T160	1		T252	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	3		T144	14		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T91	2		T59	14		T287	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	1		T158	14		T257	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T96	2		T138	2		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T160	10		T248	2		T167	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T50	9		T145	12		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T7	8		T12	9		T50	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T8	13		T45	4		T50	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	1		T45	4		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T8	13		T96	11		T32	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T1	1		T2	1		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	11		T144	13		T91	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T246	3		T157	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T213	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T138	16		T89	1		T158	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T146	10		T164	11		T160	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T7	4		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T73	1		T145	12		T59	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T144	15		T38	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T96	3		T138	3		T91	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T37	2		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	1		T50	10		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T87	1		T90	1		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T45	5		T37	1		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	9		T12	10		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	1		T6	1		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T221	10		T298	11		T365	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T8	14		T19	1		T298	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18259	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T305	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	3		T45	4		T59	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T32	9		T158	5		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T4	18		T5	15		T46	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T36	4		T144	2		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T246	7		T140	17		T293	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	1		T142	8		T289	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T138	15		T158	3		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T146	2		T164	10		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	10		T7	15		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T145	9		T59	13		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	11		T243	5		T190	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	4		T91	10		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	9		T37	1		T137	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	13		T39	1		T145	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T87	11		T263	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	12		T263	3		T269	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	9		T45	10		T50	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	18		T49	24		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T298	9		T369	6		T326	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T298	2		T261	7		T332	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T367	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T305	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T26	3		T270	1		T364	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T366	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T245	1		T367	5		T368	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T148	1		T104	3		T360	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T45	4		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T32	14		T158	5		T159	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	1		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	13		T36	11		T96	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	1		T11	1		T246	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T91	7		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T89	1		T140	1		T141	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T146	10		T164	11		T248	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T138	16		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T73	1		T145	12		T160	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	4		T144	15		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T91	3		T59	15		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T37	2		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T96	3		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T87	1		T90	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	1		T37	1		T50	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T7	9		T12	10		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	455	1			T1	1		T8	14		T45	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T270	10		T364	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T367	6		T368	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T104	15		T360	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	3		T45	4		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	9		T158	5		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T4	18		T5	15		T46	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T36	4		T144	2		T269	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T246	7		T293	17		T370	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T91	8		T40	1		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	17		T48	1		T168	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T146	2		T164	10		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	10		T138	15		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T145	9		T160	12		T264	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	15		T144	11		T137	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T91	10		T59	13		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	9		T37	1		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T138	4		T39	1		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T87	11		T263	8		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	18		T50	13		T145	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	9		T45	10		T50	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T45	12		T49	24		T50	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30