Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23640

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3564

1

T1

2

T4

11

T6

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21391

1

T1

3

T3

148

T7

1

auto[1]

5813

1

T2

1

T4

30

T5

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	323	1			T11	1		T38	2		T158	25
values[0]	57	1			T145	30		T265	10		T371	1
values[1]	741	1			T1	1		T45	8		T36	15
values[2]	562	1			T1	1		T6	10		T12	10
values[3]	486	1			T7	37		T8	13		T45	11
values[4]	2852	1			T2	1		T5	16		T6	4
values[5]	700	1			T39	4		T139	1		T59	28
values[6]	501	1			T6	19		T73	1		T96	14
values[7]	751	1			T4	19		T7	1		T37	1
values[8]	760	1			T1	1		T96	8		T26	3
values[9]	1217	1			T4	11		T45	17		T49	9
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	694	1			T1	2		T6	10		T45	8
values[1]	510	1			T8	13		T12	10		T32	23
values[2]	527	1			T7	37		T45	11		T37	3
values[3]	2935	1			T2	1		T5	16		T6	4
values[4]	650	1			T96	14		T59	28		T243	6
values[5]	569	1			T6	19		T73	1		T138	5
values[6]	729	1			T1	1		T4	19		T7	1
values[7]	815	1			T4	11		T45	17		T49	9
values[8]	1165	1			T11	1		T50	32		T138	31
values[9]	104	1			T38	2		T244	11		T257	16
minimum	18506	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	10		T50	12		T137	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	2		T45	5		T36	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T32	10		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	1		T219	1		T246	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T213	1		T59	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	26		T45	11		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T2	1		T5	16		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	1		T144	12		T91	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T96	2		T59	14		T246	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T243	6		T157	1		T160	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T138	3		T40	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	19		T73	1		T263	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	1		T4	19		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T37	1		T49	17		T50	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	9		T26	1		T247	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	11		T45	13		T243	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T138	16		T90	1		T248	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	1		T50	16		T91	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T38	1		T244	5		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T249	11		T216	9		T272	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18201	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T144	3		T145	18		T303	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	16		T137	3		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T45	3		T36	6		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	9		T32	13		T91	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T8	12		T246	2		T158	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T59	10		T100	7		T202	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	11		T37	1		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T43	12		T44	23		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	13		T144	14		T91	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T96	12		T59	14		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T160	10		T252	2		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	2		T141	18		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T164	3		T147	1		T289	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T96	7		T139	10		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	9		T145	11		T48	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	2		T247	1		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	4		T158	2		T255	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T138	15		T248	14		T256	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T50	16		T91	6		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T38	1		T244	6		T257	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T259	17		T260	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T144	12		T145	12		T303	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T38	1		T248	15		T244	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T11	1		T158	11		T289	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T265	1		T273	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T145	18		T371	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T50	12		T137	7		T138	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T45	5		T36	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	10		T12	1		T32	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T219	1		T246	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	1		T59	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	26		T8	1		T45	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T2	1		T5	16		T6	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	1		T144	12		T91	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T59	14		T246	3		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	3		T139	1		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T96	2		T138	3		T248	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	19		T73	1		T263	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	19		T7	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T37	1		T49	17		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T96	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T243	9		T158	4		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T49	9		T138	16		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T4	11		T45	13		T50	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T38	1		T248	14		T244	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T158	14		T289	6		T308	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T265	9		T273	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T145	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T50	16		T137	3		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	3		T36	6		T144	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	9		T32	13		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T246	2		T158	4		T189	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T59	10		T147	8		T100	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	11		T8	12		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T43	12		T44	23		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	13		T144	14		T91	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T59	14		T251	12		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T39	1		T160	11		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T96	12		T138	2		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	1		T253	11		T266	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T141	18		T18	2		T168	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T50	9		T145	11		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T96	7		T26	2		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T158	2		T48	4		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T138	15		T164	10		T281	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T45	4		T50	16		T91	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	1		T50	17		T137	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	2		T45	4		T36	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	10		T32	14		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	13		T219	1		T246	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T213	1		T59	11		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	13		T45	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	1		T5	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T8	14		T144	15		T91	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T96	14		T59	15		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T243	1		T157	1		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	3		T40	1		T141	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T73	1		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T4	1		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T37	1		T49	1		T50	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	1		T26	3		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T45	5		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T138	16		T90	1		T248	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	1		T50	17		T91	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T38	2		T244	7		T257	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T249	1		T216	1		T272	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18364	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T144	13		T145	13		T303	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	9		T50	11		T137	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	4		T36	4		T144	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	9		T91	10		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T246	7		T158	5		T268	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T59	10		T269	3		T202	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	24		T45	10		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T5	15		T6	3		T46	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	11		T91	8		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T59	13		T246	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T243	5		T160	8		T142	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T138	2		T40	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	18		T263	8		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T4	18		T248	10		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	16		T50	13		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	8		T247	3		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	10		T45	12		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T138	15		T248	14		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	15		T91	8		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T244	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T249	10		T216	8		T272	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T47	1		T168	4		T171	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T144	2		T145	17		T303	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T38	2		T248	15		T244	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T11	1		T158	15		T289	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T265	10		T273	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T145	13		T371	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T50	17		T137	4		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T45	4		T36	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T12	10		T32	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T219	1		T246	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T38	1		T59	11		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	13		T8	13		T45	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	1		T5	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	14		T144	15		T91	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T59	15		T246	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	3		T139	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T96	14		T138	3		T248	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	1		T73	1		T263	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	1		T7	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T37	1		T49	1		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T96	8		T26	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T243	1		T158	3		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T49	1		T138	16		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T4	1		T45	5		T50	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T248	14		T244	4		T168	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T158	10		T289	7		T190	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T273	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T145	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	11		T137	6		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	4		T36	4		T144	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	9		T32	9		T91	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T246	7		T158	5		T189	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T59	10		T17	1		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	24		T45	10		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T5	15		T6	3		T46	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	11		T91	8		T220	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T59	13		T246	2		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	1		T243	5		T160	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T138	2		T248	10		T48	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	18		T263	8		T264	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	18		T40	1		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	16		T50	13		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T247	3		T17	2		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T243	8		T158	3		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T49	8		T138	15		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	10		T45	12		T50	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30