Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23532

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3672

1

T1

2

T6

19

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21178

1

T1

1

T3

148

T6

19

auto[1]

6026

1

T1

2

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	284	1			T7	18		T49	9		T50	32
values[0]	62	1			T245	1		T104	18		T372	15
values[1]	742	1			T6	4		T45	8		T96	11
values[2]	2915	1			T1	1		T2	1		T4	19
values[3]	659	1			T1	1		T11	1		T91	15
values[4]	515	1			T89	1		T146	12		T164	21
values[5]	700	1			T4	11		T73	1		T138	31
values[6]	570	1			T7	19		T144	26		T38	1
values[7]	723	1			T6	10		T7	1		T50	23
values[8]	617	1			T6	19		T37	4		T87	12
values[9]	1163	1			T1	1		T8	14		T12	10
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	833	1			T6	4		T45	8		T96	11
values[1]	2795	1			T1	1		T2	1		T4	19
values[2]	567	1			T1	1		T11	1		T89	1
values[3]	641	1			T138	31		T146	12		T164	21
values[4]	673	1			T4	11		T7	19		T73	1
values[5]	617	1			T96	3		T144	26		T138	7
values[6]	682	1			T6	10		T7	1		T50	23
values[7]	653	1			T6	19		T12	10		T45	17
values[8]	1059	1			T1	1		T7	18		T45	11
values[9]	195	1			T8	14		T255	5		T221	10
minimum	18489	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	4		T45	5		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T96	1		T32	10		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	1		T2	1		T4	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T36	9		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	1		T89	1		T246	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T213	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T138	16		T158	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	3		T164	11		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T4	11		T7	16		T246	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T73	1		T145	10		T252	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	12		T38	1		T243	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T96	1		T138	5		T91	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	10		T137	7		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T50	14		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T37	2		T87	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	19		T45	13		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	10		T45	11		T50	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T1	1		T49	26		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T221	1		T298	10		T369	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T8	1		T255	3		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18205	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T148	1		T104	16		T21	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T45	3		T59	10		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T96	10		T32	13		T158	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T43	12		T44	23		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	12		T36	6		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T246	2		T100	7		T361	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T289	15		T257	13		T359	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	15		T158	2		T141	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T146	9		T164	10		T160	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	3		T164	3		T195	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	11		T252	9		T287	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T144	14		T164	1		T257	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T96	2		T138	2		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T137	3		T158	14		T309	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T50	9		T39	1		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	9		T37	1		T160	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	4		T38	1		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	8		T50	16		T96	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T50	16		T144	16		T91	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T221	9		T298	10		T369	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T8	13		T255	2		T298	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T104	2		T21	3		T360	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	10		T50	16		T252	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T49	9		T267	1		T298	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T245	1		T372	8		T367	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T104	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	4		T45	5		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T96	1		T32	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T1	1		T2	1		T4	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	1		T36	9		T144	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	1		T246	8		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	1		T91	9		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T89	1		T140	18		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T146	3		T164	11		T248	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	11		T138	16		T246	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T73	1		T145	10		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	16		T144	12		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T91	11		T59	14		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	10		T137	7		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T50	14		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	2		T87	12		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	19		T37	1		T145	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	1		T45	11		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T1	1		T8	1		T45	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T7	8		T50	16		T252	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T267	3		T298	10		T170	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T372	7		T367	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T104	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T45	3		T247	1		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T96	10		T32	13		T158	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T43	12		T44	23		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	12		T36	6		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T246	2		T100	7		T361	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T91	6		T289	15		T257	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T141	18		T48	4		T168	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T146	9		T164	10		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	15		T164	3		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T145	11		T160	1		T252	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	3		T144	14		T164	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T91	2		T59	14		T287	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	3		T158	14		T257	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	9		T96	2		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T37	1		T160	10		T308	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T145	12		T168	9		T298	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	9		T96	7		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T8	13		T45	4		T50	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T45	4		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T96	11		T32	14		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T1	1		T2	1		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	13		T36	11		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T89	1		T246	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T213	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T138	16		T158	3		T141	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T146	10		T164	11		T160	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T7	4		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T73	1		T145	12		T252	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T144	15		T38	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T96	3		T138	3		T91	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T137	4		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T50	10		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	10		T37	2		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	1		T45	5		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	9		T45	1		T50	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T1	1		T49	2		T50	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T221	10		T298	11		T369	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T8	14		T255	5		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18335	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T148	1		T104	3		T21	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	3		T45	4		T59	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T32	9		T158	5		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T4	18		T5	15		T46	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T36	4		T144	2		T91	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T246	7		T140	17		T293	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	1		T142	8		T289	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	15		T158	3		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T146	2		T164	10		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	10		T7	15		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	9		T252	10		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	11		T243	5		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	4		T91	10		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	9		T137	6		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	13		T39	1		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	1		T87	11		T263	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	18		T45	12		T145	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	9		T45	10		T50	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T49	24		T50	11		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T298	9		T369	6		T326	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T298	2		T261	7		T358	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T268	12		T372	7		T367	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T104	15		T21	3		T185	20

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	9		T50	17		T252	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T49	1		T267	4		T298	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T245	1		T372	8		T367	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T104	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T45	4		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T96	11		T32	14		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	1		T2	1		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	13		T36	11		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	1		T246	3		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	1		T91	7		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T89	1		T140	1		T141	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T146	10		T164	11		T248	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T138	16		T246	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T73	1		T145	12		T160	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	4		T144	15		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T91	3		T59	15		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T137	4		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T50	10		T96	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	2		T87	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T37	1		T145	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T12	10		T45	1		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T1	1		T8	14		T45	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T7	9		T50	15		T252	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T49	8		T298	2		T170	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T372	7		T367	6		T368	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T104	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	3		T45	4		T247	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T32	9		T158	5		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T4	18		T5	15		T46	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	4		T144	2		T269	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T246	7		T293	17		T370	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T91	8		T40	1		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	17		T48	1		T168	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T146	2		T164	10		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	10		T138	15		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	9		T160	12		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	15		T144	11		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T91	10		T59	13		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	9		T137	6		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	13		T138	4		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	1		T87	11		T263	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	18		T145	17		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T45	10		T138	2		T248	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T45	12		T49	16		T50	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30