Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	2		T144	13		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	13		T45	1		T50	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T142	1		T143	2		T166	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T45	4		T138	16		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	2		T91	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T85	11		T38	2		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	1		T5	1		T13	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T50	17		T138	3		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	4		T45	5		T73	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	10		T12	10		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T90	1		T164	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	2		T91	7		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	1		T37	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T96	19		T144	17		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	14		T48	7		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	1		T139	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T50	17		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	1		T26	3		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T142	1		T279	2		T170	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T1	1		T264	1		T280	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18266	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	1		T144	2		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	10		T50	13		T32	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T142	12		T143	23		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	4		T138	15		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	28		T91	10		T263	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	23		T248	10		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T5	15		T46	33		T161	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T50	11		T138	4		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	15		T45	12		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	9		T36	4		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	9		T147	12		T289	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	27		T91	8		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	8		T87	11		T91	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	16		T138	2		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	3		T291	1		T292	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	16		T243	8		T158	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	15		T144	11		T137	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	3		T145	17		T293	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T142	8		T171	8		T294	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T264	1		T280	1		T295	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T20	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T274	1		T275	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T276	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T254	1		T277	12		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	2		T144	13		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	13		T45	5		T50	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T247	2		T17	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	16		T85	11		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T91	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T38	2		T59	15		T248	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	1		T263	2		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	9		T50	17		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	1		T5	1		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	1		T12	10		T96	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T7	4		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	2		T36	11		T96	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	1		T87	1		T91	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	17		T138	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T37	1		T209	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	1		T96	11		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T8	14		T50	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T1	1		T6	1		T26	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T185	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T37	1		T144	2		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	14		T50	13		T32	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T247	3		T17	2		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T138	15		T286	6		T240	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	10		T91	10		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T59	13		T248	24		T190	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	18		T263	11		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	9		T50	11		T138	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T5	15		T45	12		T46	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T246	2		T18	1		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	15		T147	8		T289	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	27		T36	4		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	8		T87	11		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	16		T138	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T209	2		T158	10		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	16		T243	8		T264	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T50	15		T144	11		T137	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	3		T145	17		T158	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30