Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23585

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3619

1

T1

1

T6

33

T7

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21330

1

T1

1

T3

148

T6

14

auto[1]

5874

1

T1

2

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T6	4		T144	26		T137	10
values[0]	17	1			T254	1		T277	12		T296	1
values[1]	546	1			T8	13		T45	11		T37	3
values[2]	662	1			T45	8		T138	31		T85	11
values[3]	734	1			T4	11		T38	2		T91	13
values[4]	729	1			T4	19		T50	28		T138	7
values[5]	2844	1			T2	1		T5	16		T7	19
values[6]	688	1			T1	1		T6	29		T7	19
values[7]	854	1			T49	9		T96	8		T144	33
values[8]	674	1			T11	1		T37	1		T49	17
values[9]	1002	1			T1	2		T8	14		T50	32
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	613	1			T45	11		T37	3		T50	23
values[1]	691	1			T45	8		T138	31		T85	11
values[2]	704	1			T4	30		T38	2		T91	13
values[3]	2919	1			T2	1		T5	16		T13	2
values[4]	652	1			T7	38		T12	10		T45	17
values[5]	745	1			T1	1		T6	29		T90	1
values[6]	833	1			T11	1		T37	1		T49	9
values[7]	704	1			T8	14		T49	17		T50	32
values[8]	866	1			T1	1		T6	4		T144	26
values[9]	103	1			T1	1		T264	2		T100	7
minimum	18374	1			T3	148		T8	13		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	2		T16	3		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	11		T50	14		T32	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T247	4		T17	4		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	5		T138	16		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	30		T91	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	1		T213	1		T59	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	1		T5	16		T13	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	12		T138	5		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	16		T45	13		T73	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	11		T12	1		T36	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T90	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	29		T145	10		T243	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T11	1		T37	1		T49	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T96	1		T144	17		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	1		T50	16		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	17		T96	1		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T144	12		T137	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	4		T26	1		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T170	1		T171	9		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T1	1		T264	2		T100	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18145	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T8	1		T160	9		T298	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T37	1		T39	1		T189	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	9		T32	13		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T247	1		T17	3		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	3		T138	15		T85	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T91	2		T287	10		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	1		T59	24		T248	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T43	12		T44	23		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	16		T138	2		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	3		T45	4		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	8		T12	9		T36	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T164	3		T147	10		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	11		T159	11		T252	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T91	4		T160	8		T141	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T96	7		T144	16		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	13		T50	16		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T96	10		T158	4		T147	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T144	14		T137	3		T209	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T26	2		T145	12		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T170	12		T297	5		T283	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T100	6		T24	3		T299	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T8	12		T160	10		T298	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T144	12		T137	7		T269	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	4		T26	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T254	1		T277	1		T296	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	2		T144	3		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T45	11		T50	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T247	4		T17	4		T142	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	5		T138	16		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	11		T91	11		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T38	1		T59	14		T248	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	19		T263	13		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T50	12		T138	5		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T2	1		T5	16		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	11		T12	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T7	16		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	29		T36	9		T91	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T49	9		T87	12		T91	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T96	1		T144	17		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T37	1		T209	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	17		T96	1		T243	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T1	1		T8	1		T50	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T89	1		T145	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T144	14		T137	3		T279	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T26	2		T139	10		T284	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T277	11		T285	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T37	1		T144	12		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	12		T50	9		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T247	1		T17	3		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	3		T138	15		T85	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T91	2		T141	2		T166	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T59	14		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T281	6		T287	10		T288	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T50	16		T138	2		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T43	12		T44	23		T45	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	8		T12	9		T96	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	3		T147	8		T289	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	6		T91	6		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	4		T164	3		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T96	7		T144	16		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T209	7		T158	14		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T96	10		T147	1		T290	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	13		T50	16		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T145	12		T164	1		T158	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	2		T16	3		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	1		T50	10		T32	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T247	2		T17	5		T141	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	4		T138	16		T85	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	2		T91	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T38	2		T213	1		T59	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T2	1		T5	1		T13	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	17		T138	3		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	4		T45	5		T73	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	10		T12	10		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T90	1		T164	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	2		T145	12		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	1		T37	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T96	8		T144	17		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	14		T50	17		T158	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T49	1		T96	11		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T144	15		T137	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T6	1		T26	3		T89	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T170	13		T171	1		T297	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T1	1		T264	1		T100	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18284	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T8	13		T160	11		T298	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	1		T39	1		T17	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	10		T50	13		T32	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T247	3		T17	2		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	4		T138	15		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	28		T91	10		T263	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	23		T248	10		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T5	15		T46	33		T161	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T50	11		T138	4		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	15		T45	12		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	9		T36	4		T91	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T164	9		T147	12		T289	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	27		T145	9		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T49	8		T87	11		T91	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	16		T138	2		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	15		T158	10		T48	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	16		T243	8		T158	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T144	11		T137	6		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	3		T145	17		T293	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T171	8		T294	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T264	1		T295	24		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T144	2		T20	6		T300	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T160	8		T298	2		T238	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T144	15		T137	4		T269	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T6	1		T26	3		T139	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T254	1		T277	12		T296	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T37	2		T144	13		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	13		T45	1		T50	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T247	2		T17	5		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	4		T138	16		T85	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	1		T91	3		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	2		T59	15		T248	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	1		T263	2		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T50	17		T138	3		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T2	1		T5	1		T13	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	10		T12	10		T96	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T7	4		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	2		T36	11		T91	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	1		T87	1		T91	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T96	8		T144	17		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T37	1		T209	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T49	1		T96	11		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T8	14		T50	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	1		T89	1		T145	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T144	11		T137	6		T269	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T6	3		T295	24		T284	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T37	1		T144	2		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	10		T50	13		T32	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T247	3		T17	2		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T45	4		T138	15		T158	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	10		T91	10		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T59	13		T248	24		T190	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	18		T263	11		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T50	11		T138	4		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T5	15		T45	12		T46	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	9		T246	2		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	15		T147	8		T289	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	27		T36	4		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	8		T87	11		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	16		T138	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T209	2		T158	10		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	16		T243	8		T264	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T50	15		T146	2		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T145	17		T158	5		T264	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30