Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24003

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3201

1

T1

1

T4

19

T6

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21549

1

T1

2

T3

148

T4

11

auto[1]

5655

1

T1

1

T2

1

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T186	7		T204	47		T301	7
values[0]	84	1			T18	20		T287	11		T254	15
values[1]	751	1			T4	11		T49	9		T96	11
values[2]	613	1			T1	1		T8	13		T144	26
values[3]	623	1			T6	4		T89	1		T213	1
values[4]	894	1			T1	1		T16	3		T87	12
values[5]	762	1			T6	19		T37	1		T50	32
values[6]	551	1			T8	14		T45	11		T36	15
values[7]	808	1			T6	10		T7	20		T49	17
values[8]	2682	1			T1	1		T2	1		T5	16
values[9]	1121	1			T4	19		T11	1		T45	8
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	897	1			T4	11		T49	9		T96	11
values[1]	656	1			T1	1		T6	4		T8	13
values[2]	701	1			T1	1		T87	12		T89	1
values[3]	831	1			T50	32		T16	3		T85	11
values[4]	737	1			T6	19		T8	14		T45	11
values[5]	573	1			T7	19		T36	15		T49	17
values[6]	2918	1			T1	1		T2	1		T5	16
values[7]	531	1			T12	10		T37	3		T50	23
values[8]	868	1			T4	19		T11	1		T45	8
values[9]	199	1			T91	13		T165	1		T147	2
minimum	18293	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T4	11		T90	1		T145	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	9		T96	1		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T8	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	4		T144	12		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T47	4		T179	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	1		T87	12		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T50	16		T16	3		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	2		T160	15		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	19		T144	3		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	1		T45	11		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	17		T157	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	16		T36	9		T145	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1555	1			T1	1		T2	1		T5	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T50	12		T138	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	10		T164	10		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T37	2		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T96	1		T26	1		T59	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	19		T11	1		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T302	15		T303	10		T304	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T91	11		T165	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18145	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T145	11		T158	14		T159	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T96	10		T158	2		T287	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	12		T164	1		T257	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T144	14		T248	14		T221	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T47	2		T100	6		T305	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T146	9		T253	11		T195	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	16		T85	10		T91	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T160	8		T141	13		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T144	12		T138	2		T209	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	13		T96	2		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T164	10		T158	4		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	3		T36	6		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T7	8		T43	12		T44	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	16		T138	2		T141	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	13		T164	3		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	9		T37	1		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T96	7		T26	2		T59	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	3		T138	15		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T302	2		T303	12		T306	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T91	2		T147	1		T220	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	1		T36	7		T73	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T186	3		T204	18		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T301	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T18	12		T254	9		T307	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T287	1		T19	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	11		T137	7		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	9		T96	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T8	1		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T144	12		T146	1		T140	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	4		T179	1		T282	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	4		T89	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T16	3		T141	1		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T87	12		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	19		T50	16		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	1		T96	1		T144	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T157	1		T164	11		T158	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T45	11		T36	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	10		T49	17		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	17		T50	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T1	1		T2	1		T5	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T50	14		T138	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T96	1		T26	1		T59	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T4	19		T11	1		T45	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T186	4		T204	29		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T18	8		T254	6		T307	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T287	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	3		T158	14		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T96	10		T158	2		T288	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	12		T145	11		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	14		T221	13		T308	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	2		T282	11		T100	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T146	9		T248	14		T195	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T141	2		T48	4		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T160	8		T141	13		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	16		T144	12		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T96	2		T144	16		T98	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T164	10		T158	4		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	13		T36	6		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	13		T91	4		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	3		T50	16		T166	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T7	8		T43	12		T44	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	9		T50	9		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T96	7		T26	2		T59	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T45	3		T37	1		T138	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T4	1		T90	1		T145	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	1		T96	11		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	1		T8	13		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T144	15		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T47	5		T179	1		T100	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	1		T87	1		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T50	17		T16	3		T85	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	1		T160	9		T141	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	1		T144	13		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T8	14		T45	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	1		T157	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	4		T36	11		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	1		T2	1		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	1		T50	17		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	14		T164	4		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	10		T37	2		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T96	8		T26	3		T59	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T11	1		T45	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T302	3		T303	13		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T91	3		T165	1		T147	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18268	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T4	10		T145	9		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T49	8		T246	2		T158	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T309	18		T310	10		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	3		T144	11		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T305	24		T311	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T87	11		T146	2		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T50	15		T91	8		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	1		T160	14		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	18		T144	2		T138	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	10		T144	16		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	16		T164	10		T158	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	15		T36	4		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T5	15		T6	9		T7	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	11		T138	4		T264	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T32	9		T164	9		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T37	1		T50	13		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T59	23		T263	3		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	18		T45	4		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T302	14		T303	9		T304	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T91	10		T220	3		T280	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T137	6		T307	19		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T186	5		T204	31		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T301	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T18	12		T254	7		T307	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T287	11		T19	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	1		T137	4		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T49	1		T96	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T8	13		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T144	15		T146	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	5		T179	1		T282	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	1		T89	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T16	3		T141	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T87	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T6	1		T50	17		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	1		T96	3		T144	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T157	1		T164	11		T158	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	14		T45	1		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T49	1		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	5		T50	17		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T1	1		T2	1		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	10		T50	10		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T96	8		T26	3		T59	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T4	1		T11	1		T45	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T186	2		T204	16		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T301	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T18	8		T254	8		T307	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	10		T137	6		T158	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T49	8		T246	2		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T145	9		T290	10		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T144	11		T140	17		T269	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T282	2		T311	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	3		T243	8		T146	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T142	12		T48	1		T289	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T87	11		T17	1		T160	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	18		T50	15		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T144	16		T263	8		T264	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T164	10		T158	5		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T45	10		T36	4		T145	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	9		T49	16		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	15		T50	11		T252	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T5	15		T7	9		T45	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T50	13		T138	4		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T59	23		T263	3		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	18		T45	4		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30