Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23963

1

T1

2

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3241

1

T1

1

T4

19

T6

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21482

1

T1

2

T3

148

T4

11

auto[1]

5722

1

T1

1

T2

1

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	319	1			T73	1		T160	19		T165	1
values[0]	35	1			T18	20		T254	15		-	-
values[1]	788	1			T4	11		T49	9		T96	11
values[2]	687	1			T1	1		T8	13		T144	26
values[3]	589	1			T6	4		T89	1		T213	1
values[4]	829	1			T1	1		T16	3		T85	11
values[5]	814	1			T6	19		T37	1		T50	32
values[6]	494	1			T7	19		T8	14		T45	11
values[7]	827	1			T6	10		T7	1		T49	17
values[8]	2680	1			T1	1		T2	1		T5	16
values[9]	888	1			T4	19		T11	1		T45	8
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T49	9		T96	11		T144	26
values[1]	615	1			T1	1		T6	4		T8	13
values[2]	686	1			T87	12		T89	1		T146	12
values[3]	884	1			T1	1		T50	32		T16	3
values[4]	654	1			T6	19		T45	11		T37	1
values[5]	566	1			T7	19		T8	14		T36	15
values[6]	2948	1			T1	1		T2	1		T5	16
values[7]	563	1			T12	10		T37	3		T50	23
values[8]	943	1			T4	19		T11	1		T45	8
values[9]	110	1			T165	1		T147	2		T220	9
minimum	18480	1			T3	148		T4	11		T9	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T137	7		T145	10		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	9		T96	1		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T8	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	4		T38	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T47	4		T179	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T87	12		T89	1		T146	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T50	16		T16	3		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	1		T40	2		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	19		T144	20		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	11		T37	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	17		T157	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	16		T8	1		T36	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T1	1		T2	1		T5	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T50	12		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T32	10		T278	1		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T37	2		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T96	1		T26	1		T59	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	19		T11	1		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T303	10		T283	1		T304	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T165	1		T147	1		T220	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18198	1			T3	148		T4	11		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T158	4		T305	7		T202	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	3		T145	11		T158	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T96	10		T144	14		T287	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	12		T164	1		T290	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T248	14		T221	9		T308	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T47	2		T100	6		T305	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T146	9		T253	11		T195	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	16		T85	10		T91	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T160	8		T141	13		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T144	28		T138	2		T209	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T96	2		T139	10		T289	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T164	10		T18	2		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	3		T8	13		T36	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T7	8		T43	12		T44	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	16		T141	18		T281	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	13		T164	3		T312	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	9		T37	1		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T96	7		T26	2		T59	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T45	3		T138	15		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T303	12		T283	11		T313	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T147	1		T220	5		T266	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T158	2		T305	4		T202	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T169	9		T102	1		T104	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T73	1		T160	9		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T18	12		T254	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	11		T137	7		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T49	9		T96	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T8	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T144	12		T38	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T47	4		T179	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	4		T89	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T16	3		T85	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T87	12		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	19		T50	16		T144	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	1		T96	1		T264	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T157	1		T164	11		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	16		T8	1		T45	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	10		T49	17		T91	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T50	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T1	1		T2	1		T5	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T50	14		T138	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T96	1		T26	1		T59	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T4	19		T11	1		T45	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T169	6		T102	11		T104	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T160	10		T280	1		T314	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T18	8		T254	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T137	3		T145	11		T158	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T96	10		T158	2		T287	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	12		T164	1		T290	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T144	14		T248	14		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	2		T100	6		T305	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T146	9		T195	16		T221	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	10		T141	2		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T160	8		T141	13		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	16		T144	28		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T96	2		T289	10		T98	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T164	10		T18	2		T314	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	3		T8	13		T36	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T91	4		T158	4		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	16		T281	6		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T7	8		T43	12		T44	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	9		T50	9		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T96	7		T26	2		T59	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T45	3		T37	1		T138	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	4		T145	12		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T96	11		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T8	13		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T38	1		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T47	5		T179	1		T100	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T87	1		T89	1		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T50	17		T16	3		T85	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T40	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T144	30		T138	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	1		T37	1		T96	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	1		T157	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	4		T8	14		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T1	1		T2	1		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T50	17		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T32	14		T278	1		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	10		T37	2		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T96	8		T26	3		T59	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	1		T11	1		T45	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T303	13		T283	12		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T165	1		T147	2		T220	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18327	1			T3	148		T4	1		T9	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T158	3		T305	5		T202	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T137	6		T145	9		T158	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T49	8		T144	11		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T290	10		T310	10		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T6	3		T243	8		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	1		T305	15		T311	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T87	11		T146	2		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	15		T91	8		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	1		T17	1		T160	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	18		T144	18		T138	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	10		T264	1		T269	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	16		T164	10		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	15		T36	4		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T5	15		T6	9		T7	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T50	11		T264	13		T281	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	9		T164	9		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T37	1		T50	13		T138	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T59	23		T263	3		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	18		T45	4		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T303	9		T304	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T220	3		T280	1		T315	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T4	10		T18	8		T143	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T158	3		T305	6		T202	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T169	7		T102	12		T104	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T73	1		T160	11		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T18	12		T254	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	1		T137	4		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	1		T96	11		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T8	13		T164	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	15		T38	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	5		T179	1		T100	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	1		T89	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T16	3		T85	11		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T87	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	1		T50	17		T144	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	1		T96	3		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T157	1		T164	11		T18	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	4		T8	14		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T49	1		T91	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T50	17		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T1	1		T2	1		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	10		T50	10		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T96	8		T26	3		T59	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	1		T11	1		T45	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T169	8		T104	14		T303	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T160	8		T280	1		T316	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T18	8		T254	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	10		T137	6		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T49	8		T246	2		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T290	10		T298	5		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T144	11		T140	17		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	1		T305	15		T311	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	3		T243	8		T146	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T142	12		T48	1		T289	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T87	11		T17	1		T160	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	18		T50	15		T144	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T264	1		T143	10		T289	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T164	10		T18	1		T269	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	15		T45	10		T36	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	9		T49	16		T91	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	11		T281	2		T242	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T5	15		T7	9		T45	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T50	13		T138	4		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	23		T263	3		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	18		T45	4		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30