Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23601

1

T1

3

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3603

1

T4

11

T7

37

T36

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21284

1

T1

1

T3

143

T6

33

auto[1]

5920

1

T1

2

T2

1

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	526	1			T3	5		T10	6		T11	1
values[0]	122	1			T310	11		T317	1		T241	1
values[1]	585	1			T45	17		T38	1		T59	21
values[2]	2723	1			T1	1		T2	1		T5	16
values[3]	768	1			T7	1		T8	14		T45	19
values[4]	659	1			T1	1		T4	11		T6	10
values[5]	619	1			T6	4		T36	15		T37	3
values[6]	837	1			T4	19		T6	19		T73	1
values[7]	747	1			T49	9		T50	32		T32	23
values[8]	787	1			T8	13		T11	1		T138	5
values[9]	1079	1			T1	1		T7	19		T12	10
minimum	17752	1			T3	143		T9	20		T10	122

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T1	1		T45	17		T96	14
values[1]	2773	1			T2	1		T5	16		T7	1
values[2]	562	1			T8	14		T45	19		T49	17
values[3]	792	1			T1	1		T4	11		T6	10
values[4]	651	1			T6	4		T36	15		T144	33
values[5]	804	1			T4	19		T6	19		T37	3
values[6]	822	1			T8	13		T11	1		T50	32
values[7]	666	1			T12	10		T138	36		T87	12
values[8]	823	1			T1	1		T7	19		T37	1
values[9]	158	1			T254	15		T279	2		T261	38
minimum	18295	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	1		T45	13		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T96	1		T59	11		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T2	1		T5	16		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T96	1		T146	3		T248	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	1		T45	16		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	17		T144	12		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T6	10		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	11		T7	10		T50	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	4		T144	17		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	9		T26	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	19		T6	19		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T143	14		T244	5		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	1		T11	1		T50	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T145	18		T160	28		T287	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T91	11		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T138	19		T87	12		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T91	9		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	16		T37	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T258	1		T318	20		T319	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T254	9		T279	1		T261	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18119	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T309	19		T226	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	4		T96	10		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T96	2		T59	10		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T43	12		T44	23		T137	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T96	7		T146	9		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T8	13		T45	3		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T144	14		T164	11		T286	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	1		T18	8		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	8		T50	25		T85	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T144	16		T209	7		T248	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T36	6		T26	2		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	1		T144	12		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T244	6		T189	9		T282	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	12		T50	16		T32	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	12		T160	9		T287	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	9		T91	2		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	17		T158	4		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T91	4		T147	8		T48	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	3		T158	14		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T318	11		T320	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T254	6		T279	1		T261	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T309	11		T226	3		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T3	5		T10	6		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T213	1		T272	22		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T310	11		T317	1		T321	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T241	1		T316	12		T322	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	13		T38	1		T263	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T59	11		T146	3		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T1	1		T2	1		T5	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T96	2		T141	1		T143	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T8	1		T45	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T144	12		T213	1		T164	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T6	10		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	11		T7	10		T49	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	4		T37	2		T144	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	9		T16	3		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	19		T6	19		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T147	5		T244	5		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	9		T50	16		T32	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T145	18		T160	28		T143	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T11	1		T91	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T138	3		T87	12		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	1		T12	1		T91	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T7	16		T37	1		T138	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17614	1			T3	143		T9	20		T10	122
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T321	1		T323	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T316	14		T322	7		T324	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	4		T288	10		T325	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	10		T146	9		T267	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T43	12		T44	23		T96	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T96	9		T141	2		T290	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	13		T45	3		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T144	14		T164	11		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T38	1		T18	8		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	8		T50	25		T305	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	1		T144	16		T209	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	6		T26	2		T85	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	12		T138	2		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T147	2		T244	6		T189	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	16		T32	13		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T145	12		T160	9		T287	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	12		T91	2		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	2		T158	4		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	9		T91	4		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	3		T138	15		T158	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T45	5		T96	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T96	3		T59	11		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	1		T5	1		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T96	8		T146	10		T248	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	14		T45	5		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	1		T144	15		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T6	1		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T7	9		T50	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T144	17		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T36	11		T26	3		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T6	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T143	1		T244	7		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	13		T11	1		T50	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	13		T160	11		T287	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	10		T91	3		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	19		T87	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T91	5		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	4		T37	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T258	1		T318	12		T319	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T254	7		T279	2		T261	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18258	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T309	12		T226	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	12		T39	1		T263	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T59	10		T142	1		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T5	15		T46	33		T137	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	2		T248	14		T290	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T45	14		T145	9		T59	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T49	16		T144	11		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	9		T246	2		T18	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	10		T7	9		T50	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	3		T144	16		T209	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T36	4		T243	5		T263	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	18		T6	18		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T143	13		T244	4		T189	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	15		T32	9		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	17		T160	26		T249	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T91	10		T164	9		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T138	17		T87	11		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T91	8		T147	8		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	15		T158	10		T140	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T318	19		T319	1		T320	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T254	8		T261	17		T92	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T309	18		T226	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T3	5		T10	6		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T213	1		T272	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T310	1		T317	1		T321	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T241	1		T316	15		T322	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	5		T38	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	11		T146	10		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	1		T2	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T96	11		T141	3		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T8	14		T45	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T144	15		T213	1		T164	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T6	1		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	1		T7	9		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	1		T37	2		T144	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T36	11		T16	3		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T6	1		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T147	3		T244	7		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T49	1		T50	17		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	13		T160	11		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	13		T11	1		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T138	3		T87	1		T90	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T12	10		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T7	4		T37	1		T138	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17752	1			T3	143		T9	20		T10	122
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T272	21		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T310	10		T321	10		T323	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T316	11		T322	6		T324	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T45	12		T263	8		T311	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T59	10		T146	2		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T5	15		T46	33		T137	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T143	10		T290	10		T225	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T45	14		T145	9		T59	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	11		T164	10		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	9		T246	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	10		T7	9		T49	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	3		T37	1		T144	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T36	4		T91	8		T243	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	18		T6	18		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T147	4		T244	4		T189	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	8		T50	15		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T145	17		T160	26		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T91	10		T164	9		T269	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	2		T87	11		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T91	8		T147	8		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T7	15		T138	15		T158	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30