Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23789

1

T1

1

T2

1

T3

148

auto[ADC_CTRL_FILTER_COND_OUT]

3415

1

T1

2

T4

30

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21027

1

T1

1

T3

148

T4

11

auto[1]

6177

1

T1

2

T2

1

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T91	13		T242	16		T326	25
values[0]	32	1			T157	1		T181	12		T327	11
values[1]	761	1			T1	1		T4	11		T6	19
values[2]	464	1			T8	14		T12	10		T73	1
values[3]	841	1			T50	28		T89	1		T91	28
values[4]	487	1			T11	1		T36	15		T49	26
values[5]	801	1			T7	18		T8	13		T50	32
values[6]	592	1			T6	10		T7	19		T137	10
values[7]	746	1			T1	1		T4	19		T37	1
values[8]	541	1			T6	4		T7	1		T37	3
values[9]	3631	1			T1	1		T2	1		T5	16
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T1	1		T4	11		T6	19
values[1]	490	1			T8	14		T12	10		T16	3
values[2]	733	1			T50	28		T96	3		T138	31
values[3]	574	1			T11	1		T36	15		T49	26
values[4]	781	1			T7	18		T8	13		T50	32
values[5]	630	1			T1	1		T4	19		T7	19
values[6]	2806	1			T2	1		T5	16		T6	10
values[7]	690	1			T6	4		T7	1		T37	3
values[8]	1044	1			T1	1		T45	19		T96	19
values[9]	226	1			T26	3		T91	13		T164	2
minimum	18258	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T6	19		T45	13		T87	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T4	11		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T243	6		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T16	3		T158	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T50	12		T138	16		T91	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T96	1		T89	1		T91	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T59	11		T263	9		T147	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T36	9		T49	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T38	1		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T7	10		T50	16		T209	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T138	3		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	19		T7	16		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T2	1		T5	16		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	10		T37	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T37	2		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	4		T85	1		T145	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T45	16		T96	1		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T1	1		T96	1		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T91	9		T165	1		T220	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T26	1		T164	1		T147	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18120	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T45	4		T39	1		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	1		T59	14		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	13		T255	2		T289	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	9		T158	4		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T50	16		T138	15		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T96	2		T91	6		T189	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T59	10		T147	2		T48	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	6		T164	10		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	12		T158	2		T252	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	8		T50	16		T209	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T138	2		T254	6		T325	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	3		T50	9		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T43	12		T44	23		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T18	8		T166	6		T281	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	1		T139	10		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T85	10		T145	12		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	3		T96	10		T144	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T96	7		T144	14		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T91	4		T220	5		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T26	2		T164	1		T147	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T91	9		T242	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T326	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T157	1		T328	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T181	1		T327	11		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	19		T45	13		T87	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T4	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T243	9		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	1		T73	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T50	12		T91	11		T243	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T89	1		T91	9		T140	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T138	16		T147	5		T48	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T36	9		T49	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T90	1		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T7	10		T50	16		T263	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T138	3		T38	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	10		T7	16		T137	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T145	10		T139	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	19		T37	1		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T37	2		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	4		T85	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T2	1		T5	16		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	482	1			T1	1		T96	1		T144	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T91	4		T242	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T326	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T328	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T181	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T45	4		T39	1		T160	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T38	1		T59	14		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	13		T255	2		T308	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T12	9		T158	4		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	16		T91	2		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T91	6		T18	2		T170	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T138	15		T147	2		T48	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T36	6		T96	2		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	12		T59	10		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	8		T50	16		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T138	2		T286	1		T254	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	3		T137	3		T209	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T145	11		T139	10		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T50	9		T248	2		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	1		T144	12		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T85	10		T17	3		T298	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T43	12		T44	23		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T96	7		T144	14		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T6	1		T45	5		T87	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T4	1		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	14		T243	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	10		T16	3		T158	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T50	17		T138	16		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T96	3		T89	1		T91	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T59	11		T263	1		T147	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T36	11		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	13		T38	1		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	9		T50	17		T209	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	1		T138	3		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T7	4		T50	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	1		T5	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T37	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T37	2		T139	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T85	11		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T45	5		T96	11		T144	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	1		T96	8		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T91	5		T165	1		T220	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T26	3		T164	2		T147	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18257	1			T3	148		T9	20		T10	128
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	18		T45	12		T87	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	10		T59	13		T159	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T243	5		T289	7		T292	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T158	5		T18	1		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T50	11		T138	15		T91	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T91	8		T140	17		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T59	10		T263	8		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T36	4		T49	24		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T158	3		T252	10		T269	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	9		T50	15		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	2		T143	10		T254	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	18		T7	15		T50	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T5	15		T46	33		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	9		T18	8		T264	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	1		T146	2		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	3		T145	17		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T45	14		T144	16		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T144	11		T32	9		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T91	8		T220	3		T242	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T147	8		T330	2		T331	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T40	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T91	5		T242	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T326	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T157	1		T328	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T181	12		T327	1		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	1		T45	5		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T4	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	14		T243	1		T252	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	10		T73	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T50	17		T91	3		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T89	1		T91	7		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	16		T147	3		T48	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T36	11		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	13		T90	1		T59	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	9		T50	17		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T138	3		T38	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	1		T7	4		T137	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T145	12		T139	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	1		T37	1		T50	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T37	2		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	1		T85	11		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T2	1		T5	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	437	1			T1	1		T96	8		T144	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T91	8		T242	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T326	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T328	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T327	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	18		T45	12		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	10		T59	13		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T243	8		T190	11		T292	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T158	5		T143	13		T252	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T50	11		T91	10		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T91	8		T140	17		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T138	15		T147	4		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T36	4		T49	24		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T59	10		T263	8		T158	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	9		T50	15		T263	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	2		T143	10		T286	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	9		T7	15		T137	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T145	9		T164	9		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	18		T50	13		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T37	1		T144	2		T138	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	3		T17	2		T298	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T5	15		T45	14		T46	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T144	11		T32	9		T145	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30