Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21552

1

T1

2

T3

148

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

5652

1

T1

1

T2

1

T4

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21673

1

T3

148

T6

14

T7

19

auto[1]

5531

1

T1

3

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	48	1			T139	11		T332	21		T333	1
values[0]	44	1			T270	5		T334	1		T201	1
values[1]	620	1			T7	1		T45	28		T49	17
values[2]	537	1			T45	8		T50	32		T85	11
values[3]	693	1			T1	1		T6	10		T144	48
values[4]	731	1			T4	11		T7	18		T12	10
values[5]	634	1			T1	1		T6	4		T96	3
values[6]	695	1			T11	1		T37	3		T73	1
values[7]	717	1			T1	1		T8	14		T50	51
values[8]	692	1			T4	19		T6	19		T37	1
values[9]	3539	1			T2	1		T5	16		T7	19
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	791	1			T7	1		T45	28		T49	17
values[1]	2715	1			T2	1		T5	16		T13	2
values[2]	764	1			T1	1		T4	11		T6	10
values[3]	734	1			T12	10		T89	1		T91	28
values[4]	479	1			T1	1		T6	4		T11	1
values[5]	729	1			T1	1		T8	14		T37	3
values[6]	783	1			T50	51		T16	3		T26	3
values[7]	701	1			T4	19		T6	19		T37	1
values[8]	1041	1			T7	19		T139	12		T263	4
values[9]	205	1			T8	13		T38	2		T164	21
minimum	18262	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	11		T138	16		T17	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	1		T45	13		T49	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T85	1		T90	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1488	1			T2	1		T5	16		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T6	10		T7	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	11		T38	1		T209	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T289	9		T257	1		T335	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	1		T89	1		T91	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	1		T96	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	1		T6	4		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T37	2		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T138	5		T87	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	26		T16	3		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	4		T158	11		T160	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	19		T6	19		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T37	1		T49	9		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T7	16		T139	1		T263	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T139	1		T146	3		T158	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T254	9		T333	1		T304	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T8	1		T38	1		T164	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T100	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T138	15		T17	3		T248	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	4		T167	13		T169	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T85	10		T39	1		T164	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	919	1			T43	12		T44	23		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	8		T36	6		T144	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T209	7		T336	9		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T289	10		T257	13		T305	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	9		T91	8		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T96	10		T160	10		T281	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T96	2		T195	16		T308	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	1		T137	3		T164	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	13		T138	2		T257	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	25		T26	2		T32	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T158	14		T160	8		T189	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T144	14		T138	2		T91	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T96	7		T59	10		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	3		T139	10		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T146	9		T158	2		T252	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T254	6		T337	4		T338	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T8	12		T38	1		T164	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T100	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T139	1		T333	1		T339	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T332	11		T340	5		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T334	1		T341	18		T342	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T270	5		T201	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	11		T138	16		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T45	13		T49	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T85	1		T90	1		T246	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	5		T50	16		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T6	10		T144	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T209	3		T59	14		T293	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	10		T36	9		T145	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	11		T12	1		T89	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	4		T148	1		T289	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T6	4		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	1		T37	2		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T138	5		T87	12		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T50	26		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T40	4		T158	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	19		T6	19		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	1		T160	28		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T7	16		T263	4		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1693	1			T2	1		T5	16		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T139	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T332	10		T340	6		T113	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T341	9		T342	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T138	15		T17	3		T248	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	4		T167	13		T169	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T85	10		T159	11		T288	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	3		T50	16		T279	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	28		T39	1		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T209	7		T59	14		T336	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	8		T36	6		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	9		T343	14		T291	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T47	2		T289	10		T288	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T96	2		T91	8		T244	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	1		T96	10		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	2		T257	15		T242	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	25		T26	2		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	13		T158	14		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	14		T138	2		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T160	9		T141	2		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	3		T18	8		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1171	1			T8	12		T43	12		T44	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	1		T138	16		T17	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	1		T45	5		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T85	11		T90	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1234	1			T2	1		T5	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T6	1		T7	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	1		T38	1		T209	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T289	11		T257	14		T335	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	10		T89	1		T91	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T96	11		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T6	1		T96	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T37	2		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	14		T138	3		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T50	27		T16	3		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	3		T158	15		T160	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	1		T6	1		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T37	1		T49	1		T96	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T7	4		T139	11		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T139	1		T146	10		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T254	7		T333	1		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T8	13		T38	2		T164	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T100	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	10		T138	15		T17	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	12		T49	16		T142	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	1		T243	13		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1173	1			T5	15		T45	4		T46	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	9		T7	9		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	10		T209	2		T293	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T289	8		T180	20		T305	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T91	18		T142	8		T143	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T40	1		T160	8		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T6	3		T269	7		T195	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T37	1		T137	6		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	4		T87	11		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	24		T32	9		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	1		T158	10		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	18		T6	18		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	8		T59	10		T160	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T7	15		T263	3		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	2		T158	3		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T254	8		T304	6		T337	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T164	10		T292	15		T344	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T139	11		T333	1		T339	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T332	11		T340	7		T113	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T334	1		T341	10		T342	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T270	1		T201	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	1		T138	16		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T45	5		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T85	11		T90	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	4		T50	17		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T6	1		T144	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T209	8		T59	15		T293	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	9		T36	11		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	1		T12	10		T89	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	5		T148	1		T289	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T6	1		T96	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	1		T37	2		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T138	3		T87	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T50	27		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	14		T40	3		T158	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T6	1		T144	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	1		T160	11		T141	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T7	4		T263	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1531	1			T2	1		T5	1		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T332	10		T340	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T341	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T270	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T45	10		T138	15		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	12		T49	16		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T246	2		T159	11		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	4		T50	15		T269	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	9		T144	18		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T209	2		T59	13		T293	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	9		T36	4		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	10		T142	8		T343	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T47	1		T289	8		T180	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	3		T91	18		T143	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	1		T137	6		T247	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	4		T87	11		T242	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	24		T145	9		T264	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	1		T158	10		T140	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	18		T6	18		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	26		T18	1		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T7	15		T263	3		T18	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1333	1			T5	15		T46	33		T49	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30