Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27204

1

T1

3

T2

1

T3

148

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21444

1

T1

2

T3

148

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

5760

1

T1

1

T2

1

T4

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21608

1

T3

148

T6

14

T7

19

auto[1]

5596

1

T1

3

T2

1

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23318

1

T1

3

T2

1

T3

148

auto[1]

3886

1

T7

11

T8

25

T11

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T139	11		T157	1		T264	14
values[0]	17	1			T270	5		T205	12		-	-
values[1]	624	1			T7	1		T45	28		T49	17
values[2]	655	1			T45	8		T50	32		T85	11
values[3]	589	1			T1	1		T6	10		T144	48
values[4]	767	1			T4	11		T7	18		T12	10
values[5]	632	1			T1	1		T6	4		T96	3
values[6]	638	1			T8	14		T11	1		T37	3
values[7]	831	1			T1	1		T50	51		T16	3
values[8]	573	1			T4	19		T6	19		T37	1
values[9]	3316	1			T2	1		T5	16		T7	19
minimum	18254	1			T3	148		T9	20		T10	128

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	639	1			T7	1		T45	11		T49	17
values[1]	2751	1			T2	1		T5	16		T13	2
values[2]	713	1			T1	1		T4	11		T6	10
values[3]	739	1			T12	10		T89	1		T38	1
values[4]	533	1			T1	1		T6	4		T11	1
values[5]	682	1			T1	1		T8	14		T37	3
values[6]	806	1			T50	51		T16	3		T26	3
values[7]	713	1			T4	19		T6	19		T37	1
values[8]	1008	1			T7	19		T139	12		T263	4
values[9]	212	1			T8	13		T38	2		T157	1
minimum	18408	1			T3	148		T9	20		T10	128

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

4136

1

T4

28

T5

15

T6

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	11		T248	11		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T49	17		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T85	1		T90	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1504	1			T2	1		T5	16		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T6	10		T7	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	11		T209	3		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T289	9		T257	1		T335	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	1		T89	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	1		T96	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	1		T6	4		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T37	2		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T138	5		T87	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T50	26		T16	3		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	10		T40	4		T158	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	19		T6	19		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T37	1		T49	9		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T7	16		T139	1		T263	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	1		T146	3		T158	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T157	1		T254	9		T182	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T8	1		T38	1		T164	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18163	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T45	13		T266	1		T270	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T248	2		T168	5		T288	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T167	13		T169	6		T100	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T85	10		T39	1		T164	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	921	1			T43	12		T44	23		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	8		T36	6		T144	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T209	7		T336	9		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T289	10		T257	13		T170	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	9		T91	8		T244	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T96	10		T160	10		T281	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T96	2		T195	16		T308	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T37	1		T137	3		T164	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	13		T138	2		T257	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T50	25		T26	2		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T32	13		T158	14		T160	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T138	2		T91	4		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T96	7		T144	14		T59	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	3		T139	10		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T146	9		T158	2		T252	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T254	6		T182	9		T337	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T8	12		T38	1		T164	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T36	7		T73	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T45	4		T266	5		T218	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T139	1		T157	1		T264	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T290	11		T282	15		T279	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T205	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T270	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T45	11		T138	16		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T45	13		T49	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	1		T90	1		T246	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T45	5		T50	16		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T6	10		T144	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T209	3		T165	1		T293	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T7	10		T36	9		T145	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	11		T12	1		T89	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T47	2		T148	1		T289	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T6	4		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T37	2		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T138	5		T87	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T50	26		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T40	4		T158	11		T160	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	19		T6	19		T91	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T144	12		T32	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T7	16		T138	3		T263	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1648	1			T2	1		T5	16		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18116	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T139	10		T307	17		T345	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T290	13		T282	16		T279	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T138	15		T17	3		T248	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	4		T167	13		T169	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T85	10		T288	10		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	3		T50	16		T59	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	28		T39	1		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T209	7		T336	9		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	8		T36	6		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	9		T343	14		T291	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T289	6		T288	16		T305	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T96	2		T91	8		T244	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	1		T96	10		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	13		T138	2		T266	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	25		T26	2		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T158	14		T160	8		T257	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T91	4		T248	14		T147	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	14		T32	13		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	3		T138	2		T18	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1131	1			T8	12		T43	12		T44	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T36	7		T73	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	1		T248	3		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T49	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T85	11		T90	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1243	1			T2	1		T5	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T6	1		T7	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T209	8		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T289	11		T257	14		T335	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	10		T89	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T96	11		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T6	1		T96	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	1		T37	2		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	14		T138	3		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T50	27		T16	3		T26	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T32	14		T40	3		T158	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	1		T6	1		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	1		T49	1		T96	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	4		T139	11		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T139	1		T146	10		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T157	1		T254	7		T182	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T8	13		T38	2		T164	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18289	1			T3	148		T9	20		T10	128
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T45	5		T266	6		T270	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	10		T248	10		T168	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	16		T142	1		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	1		T243	13		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1182	1			T5	15		T45	4		T46	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	9		T7	9		T36	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	10		T209	2		T293	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T289	8		T180	20		T170	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T91	18		T142	8		T143	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T40	1		T160	8		T281	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T6	3		T269	7		T195	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	1		T137	6		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	4		T87	11		T140	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	24		T145	9		T247	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T32	9		T40	1		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	18		T6	18		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	8		T144	11		T59	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T7	15		T263	3		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	2		T158	3		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T254	8		T182	9		T304	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T164	10		T344	11		T346	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T138	15		T17	2		T169	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T45	12		T270	4		T330	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T139	11		T157	1		T264	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T290	14		T282	17		T279	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T205	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T45	1		T138	16		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T45	5		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	11		T90	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T45	4		T50	17		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T6	1		T144	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T209	8		T165	1		T293	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	9		T36	11		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T12	10		T89	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	2		T148	1		T289	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T6	1		T96	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T37	2		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	14		T138	3		T87	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	1		T50	27		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T40	3		T158	15		T160	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	1		T6	1		T91	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	1		T144	15		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	4		T138	3		T263	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1483	1			T2	1		T5	1		T8	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18254	1			T3	148		T9	20		T10	128
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T264	13		T307	20		T345	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T290	10		T282	14		T279	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T205	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T270	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	10		T138	15		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	12		T49	16		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T246	2		T48	2		T298	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	4		T50	15		T59	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	9		T144	18		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T209	2		T293	17		T336	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	9		T36	4		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	10		T142	8		T343	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T289	7		T305	9		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	3		T91	18		T143	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	1		T137	6		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T138	4		T87	11		T305	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	24		T145	9		T247	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	1		T158	10		T160	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	18		T6	18		T91	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T144	11		T32	9		T160	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	15		T138	2		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1296	1			T5	15		T46	33		T49	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23068

1

T1

3

T2

1

T3

148

auto[1]

auto[0]

4136

1

T4

28

T5

15

T6

30