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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.66


Total test records in report: 919
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T799 /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2198112950 Mar 26 12:28:13 PM PDT 24 Mar 26 12:32:36 PM PDT 24 415129986215 ps
T800 /workspace/coverage/default/48.adc_ctrl_filters_wakeup.280888328 Mar 26 12:28:19 PM PDT 24 Mar 26 12:35:28 PM PDT 24 184681685063 ps
T323 /workspace/coverage/default/35.adc_ctrl_stress_all.2265596595 Mar 26 12:29:04 PM PDT 24 Mar 26 12:34:55 PM PDT 24 341594147952 ps
T801 /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2966985274 Mar 26 12:26:11 PM PDT 24 Mar 26 12:26:32 PM PDT 24 33644481150 ps
T56 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2192478150 Mar 26 12:22:00 PM PDT 24 Mar 26 12:22:47 PM PDT 24 36688785777 ps
T57 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1333875362 Mar 26 12:22:39 PM PDT 24 Mar 26 12:22:58 PM PDT 24 4429555706 ps
T93 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.780423380 Mar 26 12:22:44 PM PDT 24 Mar 26 12:22:46 PM PDT 24 594420335 ps
T802 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1034569265 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:20 PM PDT 24 495480526 ps
T117 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1742062369 Mar 26 12:26:33 PM PDT 24 Mar 26 12:26:34 PM PDT 24 352106982 ps
T803 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.85383130 Mar 26 12:24:33 PM PDT 24 Mar 26 12:24:35 PM PDT 24 367025341 ps
T58 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3573820162 Mar 26 12:27:07 PM PDT 24 Mar 26 12:27:09 PM PDT 24 2291820545 ps
T136 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4276256545 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:40 PM PDT 24 1309647632 ps
T804 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3835236785 Mar 26 12:24:56 PM PDT 24 Mar 26 12:24:58 PM PDT 24 382331252 ps
T64 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.230671645 Mar 26 12:23:01 PM PDT 24 Mar 26 12:23:02 PM PDT 24 514492574 ps
T805 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3332596783 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:25 PM PDT 24 395254780 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.77863994 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:25 PM PDT 24 490458783 ps
T118 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1252693214 Mar 26 12:27:04 PM PDT 24 Mar 26 12:27:05 PM PDT 24 324345484 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2941062420 Mar 26 12:25:40 PM PDT 24 Mar 26 12:25:47 PM PDT 24 2155065774 ps
T806 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3984026922 Mar 26 12:26:20 PM PDT 24 Mar 26 12:26:21 PM PDT 24 322639010 ps
T119 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2499786023 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:37 PM PDT 24 1213218801 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3200855994 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:50 PM PDT 24 4204187246 ps
T807 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.283132626 Mar 26 12:26:38 PM PDT 24 Mar 26 12:26:39 PM PDT 24 489810475 ps
T77 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.336320008 Mar 26 12:26:20 PM PDT 24 Mar 26 12:26:21 PM PDT 24 821839738 ps
T78 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.593673145 Mar 26 12:23:01 PM PDT 24 Mar 26 12:23:03 PM PDT 24 716446813 ps
T808 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.426568058 Mar 26 12:23:44 PM PDT 24 Mar 26 12:23:46 PM PDT 24 361160241 ps
T120 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2684548442 Mar 26 12:26:35 PM PDT 24 Mar 26 12:28:19 PM PDT 24 43949841291 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.35168987 Mar 26 12:22:44 PM PDT 24 Mar 26 12:22:46 PM PDT 24 312074209 ps
T61 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1936328405 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:29 PM PDT 24 4789363092 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1846490830 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:23 PM PDT 24 410426042 ps
T132 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4153718416 Mar 26 12:27:03 PM PDT 24 Mar 26 12:27:09 PM PDT 24 2112985388 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1625605880 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:08 PM PDT 24 453523897 ps
T133 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.711459191 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:58 PM PDT 24 4108725218 ps
T810 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2020512385 Mar 26 12:26:32 PM PDT 24 Mar 26 12:26:35 PM PDT 24 281901916 ps
T811 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3470842253 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:11 PM PDT 24 521788379 ps
T62 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2143494537 Mar 26 12:26:38 PM PDT 24 Mar 26 12:26:50 PM PDT 24 4780123804 ps
T812 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3541019074 Mar 26 12:24:32 PM PDT 24 Mar 26 12:24:33 PM PDT 24 548420542 ps
T80 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3748190930 Mar 26 12:22:59 PM PDT 24 Mar 26 12:23:01 PM PDT 24 350925922 ps
T123 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1641157118 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:24 PM PDT 24 465834503 ps
T70 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3994842149 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:51 PM PDT 24 537764978 ps
T66 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142487339 Mar 26 12:23:28 PM PDT 24 Mar 26 12:23:41 PM PDT 24 4367958035 ps
T74 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1365497007 Mar 26 12:25:25 PM PDT 24 Mar 26 12:25:31 PM PDT 24 3931501681 ps
T107 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1917183397 Mar 26 12:22:18 PM PDT 24 Mar 26 12:22:21 PM PDT 24 362052706 ps
T71 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2133966071 Mar 26 12:23:57 PM PDT 24 Mar 26 12:24:00 PM PDT 24 329178904 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.205890552 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:37 PM PDT 24 576115363 ps
T814 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.648492493 Mar 26 12:27:08 PM PDT 24 Mar 26 12:27:09 PM PDT 24 336163504 ps
T72 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2033577309 Mar 26 12:22:40 PM PDT 24 Mar 26 12:22:42 PM PDT 24 534387257 ps
T815 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4102900119 Mar 26 12:24:17 PM PDT 24 Mar 26 12:24:31 PM PDT 24 4736177700 ps
T816 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2124397837 Mar 26 12:27:03 PM PDT 24 Mar 26 12:27:05 PM PDT 24 437658471 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.896710067 Mar 26 12:26:43 PM PDT 24 Mar 26 12:26:51 PM PDT 24 4471996780 ps
T75 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1258548817 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:35 PM PDT 24 399432843 ps
T134 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1927225894 Mar 26 12:26:33 PM PDT 24 Mar 26 12:26:39 PM PDT 24 5296134854 ps
T135 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1115158118 Mar 26 12:26:38 PM PDT 24 Mar 26 12:26:45 PM PDT 24 4708688699 ps
T373 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2855615477 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:36 PM PDT 24 4345850957 ps
T818 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1757551763 Mar 26 12:23:38 PM PDT 24 Mar 26 12:23:40 PM PDT 24 503345833 ps
T819 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3615152989 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:25 PM PDT 24 398846019 ps
T820 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3443270919 Mar 26 12:23:08 PM PDT 24 Mar 26 12:23:09 PM PDT 24 418268536 ps
T76 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3317889341 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:40 PM PDT 24 555614661 ps
T821 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.86636262 Mar 26 12:24:39 PM PDT 24 Mar 26 12:24:43 PM PDT 24 974505757 ps
T822 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.595196002 Mar 26 12:26:32 PM PDT 24 Mar 26 12:26:35 PM PDT 24 469406628 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.822024435 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:11 PM PDT 24 618810442 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3552531155 Mar 26 12:26:35 PM PDT 24 Mar 26 12:27:01 PM PDT 24 9381789421 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2139450266 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:35 PM PDT 24 2375458248 ps
T826 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1267567029 Mar 26 12:24:01 PM PDT 24 Mar 26 12:24:06 PM PDT 24 4282043558 ps
T376 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1483798678 Mar 26 12:25:49 PM PDT 24 Mar 26 12:25:53 PM PDT 24 4341397811 ps
T124 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1604831343 Mar 26 12:23:49 PM PDT 24 Mar 26 12:23:51 PM PDT 24 330957906 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2759167477 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:41 PM PDT 24 2771042420 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1253807980 Mar 26 12:23:22 PM PDT 24 Mar 26 12:23:23 PM PDT 24 530773384 ps
T829 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3539033255 Mar 26 12:26:23 PM PDT 24 Mar 26 12:26:25 PM PDT 24 484553468 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3649172100 Mar 26 12:22:38 PM PDT 24 Mar 26 12:22:40 PM PDT 24 854774129 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1788072805 Mar 26 12:24:39 PM PDT 24 Mar 26 12:24:41 PM PDT 24 416741610 ps
T831 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.62721296 Mar 26 12:23:00 PM PDT 24 Mar 26 12:23:03 PM PDT 24 416785465 ps
T832 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3767482935 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:31 PM PDT 24 4579006640 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.224554692 Mar 26 12:26:14 PM PDT 24 Mar 26 12:26:15 PM PDT 24 350868991 ps
T834 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3223342469 Mar 26 12:26:19 PM PDT 24 Mar 26 12:26:25 PM PDT 24 4151532381 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.513972195 Mar 26 12:21:44 PM PDT 24 Mar 26 12:21:46 PM PDT 24 355418796 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2487782599 Mar 26 12:26:38 PM PDT 24 Mar 26 12:26:39 PM PDT 24 503537769 ps
T836 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3101742244 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:37 PM PDT 24 560225785 ps
T837 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1773592322 Mar 26 12:26:30 PM PDT 24 Mar 26 12:26:34 PM PDT 24 645563743 ps
T838 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.914812657 Mar 26 12:22:53 PM PDT 24 Mar 26 12:22:54 PM PDT 24 348806161 ps
T839 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1617831583 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:43 PM PDT 24 2560733268 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.66206028 Mar 26 12:26:49 PM PDT 24 Mar 26 12:26:50 PM PDT 24 513616427 ps
T841 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.258711380 Mar 26 12:24:41 PM PDT 24 Mar 26 12:24:47 PM PDT 24 1210897504 ps
T842 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2842604033 Mar 26 12:25:46 PM PDT 24 Mar 26 12:25:55 PM PDT 24 2165830917 ps
T843 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1221766341 Mar 26 12:27:04 PM PDT 24 Mar 26 12:27:07 PM PDT 24 2342279326 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1894559027 Mar 26 12:24:30 PM PDT 24 Mar 26 12:24:31 PM PDT 24 373417147 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3525209265 Mar 26 12:22:20 PM PDT 24 Mar 26 12:22:23 PM PDT 24 543461955 ps
T846 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4234886830 Mar 26 12:26:33 PM PDT 24 Mar 26 12:26:41 PM PDT 24 8750235715 ps
T847 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3872629078 Mar 26 12:23:21 PM PDT 24 Mar 26 12:23:22 PM PDT 24 346055990 ps
T79 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1516840676 Mar 26 12:24:32 PM PDT 24 Mar 26 12:24:35 PM PDT 24 540613733 ps
T848 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3825090436 Mar 26 12:23:36 PM PDT 24 Mar 26 12:23:39 PM PDT 24 1266916266 ps
T849 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.75713080 Mar 26 12:24:03 PM PDT 24 Mar 26 12:24:07 PM PDT 24 4499441561 ps
T130 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2109013619 Mar 26 12:26:42 PM PDT 24 Mar 26 12:26:44 PM PDT 24 470203282 ps
T850 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2951406698 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:24 PM PDT 24 503575067 ps
T851 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.88036629 Mar 26 12:23:20 PM PDT 24 Mar 26 12:23:22 PM PDT 24 473639491 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1339682858 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:41 PM PDT 24 1153937141 ps
T852 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1049697278 Mar 26 12:21:42 PM PDT 24 Mar 26 12:21:48 PM PDT 24 2257116715 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2606977697 Mar 26 12:26:44 PM PDT 24 Mar 26 12:26:57 PM PDT 24 3080332762 ps
T854 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1585844403 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:23 PM PDT 24 450583080 ps
T81 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2039448321 Mar 26 12:22:19 PM PDT 24 Mar 26 12:22:31 PM PDT 24 8572263898 ps
T855 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2728978395 Mar 26 12:24:59 PM PDT 24 Mar 26 12:25:00 PM PDT 24 518255156 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4067155138 Mar 26 12:22:52 PM PDT 24 Mar 26 12:22:54 PM PDT 24 418547252 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3390696083 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:07 PM PDT 24 458650540 ps
T858 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.439713727 Mar 26 12:26:49 PM PDT 24 Mar 26 12:26:52 PM PDT 24 797413352 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2320394351 Mar 26 12:22:08 PM PDT 24 Mar 26 12:22:12 PM PDT 24 698235736 ps
T859 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.88973624 Mar 26 12:21:54 PM PDT 24 Mar 26 12:22:06 PM PDT 24 5042563855 ps
T128 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1572035312 Mar 26 12:24:41 PM PDT 24 Mar 26 12:24:47 PM PDT 24 6168097773 ps
T860 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2217561397 Mar 26 12:24:39 PM PDT 24 Mar 26 12:24:41 PM PDT 24 310477895 ps
T861 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.294979377 Mar 26 12:23:34 PM PDT 24 Mar 26 12:23:35 PM PDT 24 377381109 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1345664039 Mar 26 12:22:19 PM PDT 24 Mar 26 12:22:22 PM PDT 24 622116451 ps
T863 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3893141343 Mar 26 12:26:14 PM PDT 24 Mar 26 12:26:17 PM PDT 24 411312161 ps
T864 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4249396709 Mar 26 12:26:23 PM PDT 24 Mar 26 12:26:25 PM PDT 24 323727410 ps
T865 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.513903262 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:08 PM PDT 24 457639334 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1858269533 Mar 26 12:23:07 PM PDT 24 Mar 26 12:23:10 PM PDT 24 667406838 ps
T867 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3609595420 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:39 PM PDT 24 440971010 ps
T868 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2213194613 Mar 26 12:25:19 PM PDT 24 Mar 26 12:25:22 PM PDT 24 2227826096 ps
T869 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1674449488 Mar 26 12:22:26 PM PDT 24 Mar 26 12:22:28 PM PDT 24 323050200 ps
T374 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2809936945 Mar 26 12:25:25 PM PDT 24 Mar 26 12:25:33 PM PDT 24 8146798648 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.14072968 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:33 PM PDT 24 609207773 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1866701665 Mar 26 12:24:23 PM PDT 24 Mar 26 12:24:25 PM PDT 24 426498997 ps
T872 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.917069362 Mar 26 12:27:06 PM PDT 24 Mar 26 12:27:08 PM PDT 24 363215740 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4076786608 Mar 26 12:22:42 PM PDT 24 Mar 26 12:22:43 PM PDT 24 544705729 ps
T874 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.474711286 Mar 26 12:25:26 PM PDT 24 Mar 26 12:25:27 PM PDT 24 455682384 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2586697811 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:10 PM PDT 24 296033020 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.817530375 Mar 26 12:25:39 PM PDT 24 Mar 26 12:25:42 PM PDT 24 807361304 ps
T877 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.190530903 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:38 PM PDT 24 373314014 ps
T878 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.991202133 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 367159066 ps
T879 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.358204881 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:23 PM PDT 24 453954340 ps
T375 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.98019150 Mar 26 12:27:03 PM PDT 24 Mar 26 12:27:26 PM PDT 24 8687539584 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3352491638 Mar 26 12:24:32 PM PDT 24 Mar 26 12:24:34 PM PDT 24 394452538 ps
T881 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1241753571 Mar 26 12:23:50 PM PDT 24 Mar 26 12:23:52 PM PDT 24 412157496 ps
T882 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3009206080 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:43 PM PDT 24 4403852810 ps
T883 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3652183586 Mar 26 12:26:19 PM PDT 24 Mar 26 12:26:21 PM PDT 24 535304576 ps
T884 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.710639461 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:34 PM PDT 24 523005386 ps
T885 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4092939464 Mar 26 12:25:24 PM PDT 24 Mar 26 12:25:25 PM PDT 24 326945441 ps
T886 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2692614595 Mar 26 12:23:19 PM PDT 24 Mar 26 12:23:25 PM PDT 24 3599473964 ps
T887 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2227048161 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:52 PM PDT 24 470482844 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2836814038 Mar 26 12:25:09 PM PDT 24 Mar 26 12:26:57 PM PDT 24 26949886115 ps
T889 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.262264890 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:40 PM PDT 24 675037885 ps
T890 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.221644089 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:38 PM PDT 24 26259838008 ps
T891 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.641009226 Mar 26 12:24:45 PM PDT 24 Mar 26 12:24:45 PM PDT 24 403767535 ps
T892 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.564897562 Mar 26 12:26:49 PM PDT 24 Mar 26 12:26:50 PM PDT 24 512594833 ps
T893 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.182920706 Mar 26 12:23:13 PM PDT 24 Mar 26 12:23:14 PM PDT 24 438138426 ps
T894 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.767536839 Mar 26 12:25:26 PM PDT 24 Mar 26 12:25:28 PM PDT 24 517559407 ps
T895 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3209775679 Mar 26 12:22:59 PM PDT 24 Mar 26 12:23:01 PM PDT 24 418032245 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3382033562 Mar 26 12:25:21 PM PDT 24 Mar 26 12:25:24 PM PDT 24 395483297 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2176298268 Mar 26 12:26:41 PM PDT 24 Mar 26 12:26:43 PM PDT 24 814700527 ps
T898 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.410314718 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:49 PM PDT 24 664038355 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2199166820 Mar 26 12:24:20 PM PDT 24 Mar 26 12:24:35 PM PDT 24 3579797734 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3843582191 Mar 26 12:26:37 PM PDT 24 Mar 26 12:26:38 PM PDT 24 719792497 ps
T901 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1866443717 Mar 26 12:23:10 PM PDT 24 Mar 26 12:23:12 PM PDT 24 381678705 ps
T902 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3741496497 Mar 26 12:26:36 PM PDT 24 Mar 26 12:26:37 PM PDT 24 333427872 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.976646989 Mar 26 12:25:09 PM PDT 24 Mar 26 12:25:10 PM PDT 24 533136578 ps
T904 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.341384091 Mar 26 12:25:26 PM PDT 24 Mar 26 12:25:28 PM PDT 24 376517609 ps
T905 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2625628373 Mar 26 12:25:08 PM PDT 24 Mar 26 12:25:10 PM PDT 24 487297177 ps
T906 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.119993293 Mar 26 12:25:48 PM PDT 24 Mar 26 12:25:52 PM PDT 24 491321186 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3678431963 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:51 PM PDT 24 4295385832 ps
T908 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3167165917 Mar 26 12:26:22 PM PDT 24 Mar 26 12:26:24 PM PDT 24 831804960 ps
T909 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2331281894 Mar 26 12:26:31 PM PDT 24 Mar 26 12:26:34 PM PDT 24 313181475 ps
T910 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4265880743 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:50 PM PDT 24 398231561 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1541971191 Mar 26 12:21:52 PM PDT 24 Mar 26 12:21:54 PM PDT 24 939471572 ps
T912 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3850136886 Mar 26 12:23:30 PM PDT 24 Mar 26 12:23:32 PM PDT 24 435128819 ps
T913 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1339951843 Mar 26 12:26:35 PM PDT 24 Mar 26 12:26:37 PM PDT 24 1090458939 ps
T914 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3088605032 Mar 26 12:26:39 PM PDT 24 Mar 26 12:26:41 PM PDT 24 495990304 ps
T915 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.316158663 Mar 26 12:26:23 PM PDT 24 Mar 26 12:26:26 PM PDT 24 509103810 ps
T916 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.580814737 Mar 26 12:26:48 PM PDT 24 Mar 26 12:26:55 PM PDT 24 4328782298 ps
T917 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1586253325 Mar 26 12:23:13 PM PDT 24 Mar 26 12:23:15 PM PDT 24 527984143 ps
T918 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3181193523 Mar 26 12:25:26 PM PDT 24 Mar 26 12:25:28 PM PDT 24 486267547 ps
T919 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3001440009 Mar 26 12:24:35 PM PDT 24 Mar 26 12:24:37 PM PDT 24 553040507 ps
T82 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1661447464 Mar 26 12:25:40 PM PDT 24 Mar 26 12:25:45 PM PDT 24 8718196972 ps

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1345114099
Short name T6
Test name
Test status
Simulation time 590823391559 ps
CPU time 346.14 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:34:12 PM PDT 24
Peak memory 201740 kb
Host smart-f5684635-6227-437b-9ba9-6c2c13fc18df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345114099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1345114099
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.915844257
Short name T12
Test name
Test status
Simulation time 302242261802 ps
CPU time 1024.44 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:45:22 PM PDT 24
Peak memory 210252 kb
Host smart-eddf137c-9f24-4101-a5c0-307af208b9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915844257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
915844257
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.538735550
Short name T18
Test name
Test status
Simulation time 271065018743 ps
CPU time 192.99 seconds
Started Mar 26 12:27:27 PM PDT 24
Finished Mar 26 12:30:40 PM PDT 24
Peak memory 210224 kb
Host smart-824cb8ca-bf18-43b2-b7e7-72f6f99aca62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538735550 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.538735550
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2153393040
Short name T138
Test name
Test status
Simulation time 491101770242 ps
CPU time 223.23 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 201704 kb
Host smart-c6969904-3689-40e2-9fd7-de1cc4553371
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153393040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2153393040
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2082232989
Short name T45
Test name
Test status
Simulation time 503101048374 ps
CPU time 775.08 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:39:32 PM PDT 24
Peak memory 201740 kb
Host smart-01ff41f2-14ba-4961-adf7-61a20f18fdd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082232989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2082232989
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3766963548
Short name T158
Test name
Test status
Simulation time 561625642395 ps
CPU time 575.31 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:38:04 PM PDT 24
Peak memory 201804 kb
Host smart-96b6f52e-a13a-48f0-9601-72c204673031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766963548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3766963548
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3924027099
Short name T164
Test name
Test status
Simulation time 513854671467 ps
CPU time 210.19 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:31:46 PM PDT 24
Peak memory 201732 kb
Host smart-c8c57588-8117-42c8-823c-e10b8c63536c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924027099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3924027099
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3768058527
Short name T38
Test name
Test status
Simulation time 90752394030 ps
CPU time 192.44 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:31:12 PM PDT 24
Peak memory 217984 kb
Host smart-579878ca-12bc-4368-9d25-7ffcf34f161c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768058527 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3768058527
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3685903725
Short name T160
Test name
Test status
Simulation time 501260924829 ps
CPU time 311.43 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:33:24 PM PDT 24
Peak memory 201724 kb
Host smart-753b1d3c-3178-46db-8ec8-2978957e6da2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685903725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3685903725
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3340076515
Short name T284
Test name
Test status
Simulation time 170501957561 ps
CPU time 223.71 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:32:04 PM PDT 24
Peak memory 210416 kb
Host smart-01474112-770d-407c-a916-fefaa44a4563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340076515 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3340076515
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.593673145
Short name T78
Test name
Test status
Simulation time 716446813 ps
CPU time 1.76 seconds
Started Mar 26 12:23:01 PM PDT 24
Finished Mar 26 12:23:03 PM PDT 24
Peak memory 201888 kb
Host smart-0e2d7a13-c3cb-4729-a30f-d14750e516c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593673145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.593673145
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3478672475
Short name T7
Test name
Test status
Simulation time 529661113735 ps
CPU time 1280.19 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:47:42 PM PDT 24
Peak memory 201724 kb
Host smart-70580b1f-b758-4f93-b924-b05fcee3d75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478672475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3478672475
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.716212853
Short name T59
Test name
Test status
Simulation time 366054700609 ps
CPU time 850.96 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:40:22 PM PDT 24
Peak memory 201732 kb
Host smart-a47d5d43-7985-42ec-9b78-e37642428353
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716212853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.716212853
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3942529121
Short name T68
Test name
Test status
Simulation time 4079625168 ps
CPU time 9.62 seconds
Started Mar 26 12:26:10 PM PDT 24
Finished Mar 26 12:26:20 PM PDT 24
Peak memory 217168 kb
Host smart-a5b7bf1a-0347-40e9-b06b-20ca997559ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942529121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3942529121
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1133146642
Short name T91
Test name
Test status
Simulation time 589969164288 ps
CPU time 654.43 seconds
Started Mar 26 12:27:19 PM PDT 24
Finished Mar 26 12:38:13 PM PDT 24
Peak memory 201832 kb
Host smart-668cef6d-b452-4285-a4d6-e15f00b2b232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133146642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1133146642
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2395675325
Short name T144
Test name
Test status
Simulation time 489626938697 ps
CPU time 536.01 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:36:15 PM PDT 24
Peak memory 201524 kb
Host smart-fd3ce102-d659-4858-94ab-98f11ce3a2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395675325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2395675325
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2492726347
Short name T217
Test name
Test status
Simulation time 511719842024 ps
CPU time 272.51 seconds
Started Mar 26 12:27:42 PM PDT 24
Finished Mar 26 12:32:15 PM PDT 24
Peak memory 201472 kb
Host smart-8c2565e3-5355-454e-bdb5-568ea9cf1faa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492726347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2492726347
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2684548442
Short name T120
Test name
Test status
Simulation time 43949841291 ps
CPU time 102.65 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:28:19 PM PDT 24
Peak memory 200752 kb
Host smart-90ab7e89-8e56-4e1b-a34c-45cd73752ce2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684548442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2684548442
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2765357557
Short name T298
Test name
Test status
Simulation time 517966360631 ps
CPU time 311.78 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:33:33 PM PDT 24
Peak memory 201820 kb
Host smart-a7f54827-c474-40d8-8501-957d89231123
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765357557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2765357557
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4041714436
Short name T96
Test name
Test status
Simulation time 487671476944 ps
CPU time 563.57 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:37:49 PM PDT 24
Peak memory 201820 kb
Host smart-e07b497d-2871-4015-887d-d55a3c50c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041714436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4041714436
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4228696819
Short name T100
Test name
Test status
Simulation time 339118135281 ps
CPU time 425.38 seconds
Started Mar 26 12:28:07 PM PDT 24
Finished Mar 26 12:35:13 PM PDT 24
Peak memory 201736 kb
Host smart-6bfd5fad-238b-41d0-885f-1339279b0821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228696819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4228696819
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1349077813
Short name T182
Test name
Test status
Simulation time 508132213055 ps
CPU time 173.21 seconds
Started Mar 26 12:27:52 PM PDT 24
Finished Mar 26 12:30:45 PM PDT 24
Peak memory 202064 kb
Host smart-ef6d4e33-9cc2-4d92-b6bd-3caba2845cf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349077813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1349077813
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2770560527
Short name T4
Test name
Test status
Simulation time 351697520427 ps
CPU time 885.06 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:43:01 PM PDT 24
Peak memory 201700 kb
Host smart-0cda437a-8a2c-47fc-85a5-703aba9b2a56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770560527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2770560527
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3640189907
Short name T145
Test name
Test status
Simulation time 348738997134 ps
CPU time 754.08 seconds
Started Mar 26 12:27:41 PM PDT 24
Finished Mar 26 12:40:16 PM PDT 24
Peak memory 201768 kb
Host smart-4e7ce86c-4bf7-427d-9d36-2f571f46c66d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640189907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3640189907
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3309078498
Short name T48
Test name
Test status
Simulation time 288955965632 ps
CPU time 393.13 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:34:46 PM PDT 24
Peak memory 210480 kb
Host smart-9a5624e6-54cf-4faf-97d7-98930d80e219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309078498 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3309078498
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1599340697
Short name T261
Test name
Test status
Simulation time 548588288462 ps
CPU time 1222.01 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:49:27 PM PDT 24
Peak memory 201412 kb
Host smart-9fb96199-c787-48eb-98f7-f79969ebf117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599340697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1599340697
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4117685974
Short name T257
Test name
Test status
Simulation time 329233675425 ps
CPU time 368.42 seconds
Started Mar 26 12:27:29 PM PDT 24
Finished Mar 26 12:33:38 PM PDT 24
Peak memory 201832 kb
Host smart-6f41eeb8-aeb6-43e6-974f-c69459296462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117685974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4117685974
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4021745233
Short name T104
Test name
Test status
Simulation time 338666838847 ps
CPU time 159.07 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:31:01 PM PDT 24
Peak memory 201732 kb
Host smart-fb1a989f-49bc-455b-86da-cea3bbe6e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021745233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4021745233
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1607103716
Short name T51
Test name
Test status
Simulation time 299138925 ps
CPU time 0.95 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:36 PM PDT 24
Peak memory 200764 kb
Host smart-18babf42-2c56-4759-af38-9a0d985bf8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607103716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1607103716
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2538257059
Short name T258
Test name
Test status
Simulation time 604304451677 ps
CPU time 621.87 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:38:41 PM PDT 24
Peak memory 218048 kb
Host smart-1e0f4870-795b-431a-8740-a14ca1907ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538257059 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2538257059
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3552531155
Short name T824
Test name
Test status
Simulation time 9381789421 ps
CPU time 25.48 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:27:01 PM PDT 24
Peak memory 200772 kb
Host smart-cefbe48a-84e4-4421-88f3-08369ad852e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552531155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3552531155
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3086431729
Short name T304
Test name
Test status
Simulation time 644145405837 ps
CPU time 1517.23 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:52:33 PM PDT 24
Peak memory 201752 kb
Host smart-c1a36a14-ebac-4918-9d17-e74b9306dcd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086431729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3086431729
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3457527341
Short name T157
Test name
Test status
Simulation time 496392921936 ps
CPU time 325.65 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:33:39 PM PDT 24
Peak memory 201792 kb
Host smart-42b85d95-810f-4649-bfc0-a270cb2c0278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457527341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3457527341
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1319903541
Short name T270
Test name
Test status
Simulation time 679806834860 ps
CPU time 1595.39 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:54:50 PM PDT 24
Peak memory 201712 kb
Host smart-8fb773af-514e-4029-8bd0-b9131ffcf8e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319903541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1319903541
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1516840676
Short name T79
Test name
Test status
Simulation time 540613733 ps
CPU time 3.3 seconds
Started Mar 26 12:24:32 PM PDT 24
Finished Mar 26 12:24:35 PM PDT 24
Peak memory 210020 kb
Host smart-635b8843-0b82-4502-a069-331cc413a719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516840676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1516840676
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1063105209
Short name T242
Test name
Test status
Simulation time 343529971784 ps
CPU time 69.36 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:29:30 PM PDT 24
Peak memory 201544 kb
Host smart-15c87274-d660-461e-89c2-434c1fa6b3f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063105209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1063105209
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3613066730
Short name T328
Test name
Test status
Simulation time 141760606547 ps
CPU time 85.33 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:29:43 PM PDT 24
Peak memory 210728 kb
Host smart-73c16b1d-1940-4174-9d1d-a971a49dcfa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613066730 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3613066730
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.655808136
Short name T5
Test name
Test status
Simulation time 200612812853 ps
CPU time 227.05 seconds
Started Mar 26 12:25:56 PM PDT 24
Finished Mar 26 12:29:44 PM PDT 24
Peak memory 201708 kb
Host smart-662aea46-7aec-4f11-a12c-1c00e41ee764
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655808136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.655808136
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2265596595
Short name T323
Test name
Test status
Simulation time 341594147952 ps
CPU time 351.34 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:34:55 PM PDT 24
Peak memory 201368 kb
Host smart-22fdbcef-b5ae-45a4-b47e-8912961518c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265596595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2265596595
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.121395123
Short name T296
Test name
Test status
Simulation time 43068402711 ps
CPU time 121.85 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:30:25 PM PDT 24
Peak memory 210460 kb
Host smart-b9db9929-e552-4967-8d10-395cf532c2fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121395123 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.121395123
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3506566072
Short name T240
Test name
Test status
Simulation time 586747323266 ps
CPU time 1032.27 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:45:30 PM PDT 24
Peak memory 212428 kb
Host smart-75e0203d-f030-4b0a-8131-07a215b982b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506566072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3506566072
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1528575310
Short name T348
Test name
Test status
Simulation time 357654667693 ps
CPU time 736.93 seconds
Started Mar 26 12:27:44 PM PDT 24
Finished Mar 26 12:40:02 PM PDT 24
Peak memory 201716 kb
Host smart-4d8ee6b3-daaa-4739-b2aa-7a8a5e137ff8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528575310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1528575310
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.871341777
Short name T332
Test name
Test status
Simulation time 182381515003 ps
CPU time 463.81 seconds
Started Mar 26 12:26:38 PM PDT 24
Finished Mar 26 12:34:22 PM PDT 24
Peak memory 201812 kb
Host smart-45815c44-cdef-4ab6-8065-8bc7c620e945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871341777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.871341777
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3500476381
Short name T324
Test name
Test status
Simulation time 1643238377031 ps
CPU time 1920.82 seconds
Started Mar 26 12:27:55 PM PDT 24
Finished Mar 26 12:59:56 PM PDT 24
Peak memory 213124 kb
Host smart-5e7f0a52-1962-4bca-88b3-341168ee7bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500476381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3500476381
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2878024977
Short name T253
Test name
Test status
Simulation time 160521098504 ps
CPU time 185.2 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 201732 kb
Host smart-05eaeaad-688e-4954-a7bb-307f962a6182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878024977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2878024977
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3077604138
Short name T283
Test name
Test status
Simulation time 484751833137 ps
CPU time 1231.59 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:49:08 PM PDT 24
Peak memory 201504 kb
Host smart-e4e5a737-98d1-434f-9914-e85a4f5a7fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077604138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3077604138
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.344195135
Short name T367
Test name
Test status
Simulation time 421011213255 ps
CPU time 1015.16 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:46:21 PM PDT 24
Peak memory 199916 kb
Host smart-ce303d10-8540-4912-987c-fc3e7206d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344195135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.344195135
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3531378475
Short name T301
Test name
Test status
Simulation time 478153759617 ps
CPU time 545.87 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:37:28 PM PDT 24
Peak memory 201748 kb
Host smart-4dab141d-0913-412b-b603-1f6b3fd1414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531378475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3531378475
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1846490830
Short name T122
Test name
Test status
Simulation time 410426042 ps
CPU time 1.32 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:23 PM PDT 24
Peak memory 200800 kb
Host smart-5e130235-a8e4-4e81-94c4-e377f3d6926f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846490830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1846490830
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2923358861
Short name T272
Test name
Test status
Simulation time 352492534365 ps
CPU time 805.85 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:41:51 PM PDT 24
Peak memory 201804 kb
Host smart-e33d865b-6d29-4ad9-9904-027c075cb259
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923358861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2923358861
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1837932957
Short name T330
Test name
Test status
Simulation time 616073252578 ps
CPU time 390.96 seconds
Started Mar 26 12:27:27 PM PDT 24
Finished Mar 26 12:33:58 PM PDT 24
Peak memory 201792 kb
Host smart-97907e64-ef1e-4c3a-af5c-96d48e2c780c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837932957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1837932957
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2247893713
Short name T320
Test name
Test status
Simulation time 386280342913 ps
CPU time 454.78 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:36:04 PM PDT 24
Peak memory 210368 kb
Host smart-36a2a21e-ca72-48c7-bcaa-422ef38fc810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247893713 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2247893713
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3579512934
Short name T254
Test name
Test status
Simulation time 499040936693 ps
CPU time 412.05 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:35:18 PM PDT 24
Peak memory 201792 kb
Host smart-2da3c478-08e3-4c9b-9ebd-ce68de42f6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579512934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3579512934
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.836378810
Short name T276
Test name
Test status
Simulation time 404168775631 ps
CPU time 314.12 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:33:26 PM PDT 24
Peak memory 202016 kb
Host smart-407309a0-41cb-4c84-a77a-8a40deb6f759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836378810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
836378810
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3840480719
Short name T139
Test name
Test status
Simulation time 330961379236 ps
CPU time 80 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 201724 kb
Host smart-13e0c388-2fb2-4d63-8d58-8074ef3b7f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840480719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3840480719
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3906273986
Short name T204
Test name
Test status
Simulation time 609210261821 ps
CPU time 380.81 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:34:57 PM PDT 24
Peak memory 210248 kb
Host smart-def02b79-6fe1-4c7c-adf8-1747fb0f9e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906273986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3906273986
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.648798509
Short name T387
Test name
Test status
Simulation time 160678671258 ps
CPU time 337.26 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:32:18 PM PDT 24
Peak memory 201776 kb
Host smart-36f83c0a-afe2-414b-a421-2044b4dbcd18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=648798509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.648798509
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.644952718
Short name T42
Test name
Test status
Simulation time 100568638333 ps
CPU time 530.79 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:35:29 PM PDT 24
Peak memory 202060 kb
Host smart-97299e8a-23ce-4361-9f32-cc8b9168452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644952718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.644952718
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2667715566
Short name T309
Test name
Test status
Simulation time 182030130177 ps
CPU time 322.05 seconds
Started Mar 26 12:27:02 PM PDT 24
Finished Mar 26 12:32:24 PM PDT 24
Peak memory 201796 kb
Host smart-d88a3910-8154-45f0-b940-15e9e8583aed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667715566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2667715566
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2938345186
Short name T273
Test name
Test status
Simulation time 552656630409 ps
CPU time 368.1 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:34:14 PM PDT 24
Peak memory 201712 kb
Host smart-5762c50d-ebe7-45ee-a24b-f027cb08ee45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938345186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2938345186
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.664790012
Short name T334
Test name
Test status
Simulation time 496979202598 ps
CPU time 1069.13 seconds
Started Mar 26 12:27:25 PM PDT 24
Finished Mar 26 12:45:15 PM PDT 24
Peak memory 201752 kb
Host smart-3225cbc2-4061-4ec9-8b1a-d1948da95b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664790012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.664790012
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.706677879
Short name T326
Test name
Test status
Simulation time 377532165648 ps
CPU time 409.86 seconds
Started Mar 26 12:27:55 PM PDT 24
Finished Mar 26 12:34:45 PM PDT 24
Peak memory 201708 kb
Host smart-04fa4086-d440-49cd-854d-51191adad3cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706677879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.706677879
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1216131585
Short name T305
Test name
Test status
Simulation time 494058525118 ps
CPU time 1187.93 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:49:14 PM PDT 24
Peak memory 199932 kb
Host smart-c712ff47-90d8-4153-8fbd-584b4ab7201b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216131585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1216131585
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3005016238
Short name T8
Test name
Test status
Simulation time 331465004469 ps
CPU time 774.52 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:39:35 PM PDT 24
Peak memory 201808 kb
Host smart-2bcbaee7-405b-4ca1-adf3-c9580aa6e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005016238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3005016238
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3317532765
Short name T366
Test name
Test status
Simulation time 166558752032 ps
CPU time 372.13 seconds
Started Mar 26 12:26:49 PM PDT 24
Finished Mar 26 12:33:01 PM PDT 24
Peak memory 201728 kb
Host smart-35e0a21e-2f5e-4557-9784-13f6fd7a630f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317532765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3317532765
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1622709834
Short name T205
Test name
Test status
Simulation time 564501785380 ps
CPU time 287.1 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:33:03 PM PDT 24
Peak memory 201680 kb
Host smart-d63c2271-3045-4e70-b1db-c35ce57365ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622709834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1622709834
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2519370114
Short name T307
Test name
Test status
Simulation time 335960510884 ps
CPU time 783.6 seconds
Started Mar 26 12:26:58 PM PDT 24
Finished Mar 26 12:40:02 PM PDT 24
Peak memory 201820 kb
Host smart-345ed16b-2433-401c-ad6f-0cffeef2500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519370114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2519370114
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4114283377
Short name T275
Test name
Test status
Simulation time 817751849318 ps
CPU time 393.66 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:33:28 PM PDT 24
Peak memory 201736 kb
Host smart-42c7950f-c95d-4be9-b6f1-5bfa6d4aab94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114283377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4114283377
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.150715750
Short name T287
Test name
Test status
Simulation time 164385656765 ps
CPU time 26.97 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:28:55 PM PDT 24
Peak memory 201720 kb
Host smart-4ae22589-9168-44e1-9d4c-adc621b9f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150715750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.150715750
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1661447464
Short name T82
Test name
Test status
Simulation time 8718196972 ps
CPU time 5.67 seconds
Started Mar 26 12:25:40 PM PDT 24
Finished Mar 26 12:25:45 PM PDT 24
Peak memory 201788 kb
Host smart-ae38ad26-400b-4120-b8e3-138210c30746
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661447464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1661447464
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1574609685
Short name T229
Test name
Test status
Simulation time 138252622572 ps
CPU time 692.78 seconds
Started Mar 26 12:26:03 PM PDT 24
Finished Mar 26 12:37:36 PM PDT 24
Peak memory 202076 kb
Host smart-7b617ea6-6069-4d56-9df0-4484b2a829b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574609685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1574609685
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2040493246
Short name T244
Test name
Test status
Simulation time 252699653229 ps
CPU time 553.58 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:35:22 PM PDT 24
Peak memory 201804 kb
Host smart-c34eb52a-2d42-4184-b6e0-a5b1baf8c56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040493246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2040493246
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2557406069
Short name T364
Test name
Test status
Simulation time 338865046190 ps
CPU time 219.5 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:30:39 PM PDT 24
Peak memory 201736 kb
Host smart-f5ffd876-a740-41bd-9f9b-497e37041195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557406069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2557406069
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2955762514
Short name T379
Test name
Test status
Simulation time 87675793451 ps
CPU time 309.55 seconds
Started Mar 26 12:27:25 PM PDT 24
Finished Mar 26 12:32:34 PM PDT 24
Peak memory 202032 kb
Host smart-84c623d0-491e-4cc2-8a94-e7ed890b8cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955762514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2955762514
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.708566818
Short name T285
Test name
Test status
Simulation time 493480054621 ps
CPU time 732.78 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:40:29 PM PDT 24
Peak memory 201720 kb
Host smart-9a5006e9-cfec-4870-b95f-b89b4d6a6120
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708566818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.708566818
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.857783376
Short name T341
Test name
Test status
Simulation time 181136472011 ps
CPU time 194.6 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:31:34 PM PDT 24
Peak memory 201720 kb
Host smart-b5e1c228-f9b1-410b-818f-9b5fec61e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857783376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.857783376
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2454954864
Short name T327
Test name
Test status
Simulation time 171803999091 ps
CPU time 88.46 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 201612 kb
Host smart-5577dc7a-c86b-483f-99f8-960a8beeebc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454954864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2454954864
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.98019150
Short name T375
Test name
Test status
Simulation time 8687539584 ps
CPU time 22.98 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:27:26 PM PDT 24
Peak memory 201780 kb
Host smart-a0102ca8-2289-471d-b8a3-234a13fa5fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98019150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_int
g_err.98019150
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2552629004
Short name T181
Test name
Test status
Simulation time 497759620840 ps
CPU time 564.32 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:35:19 PM PDT 24
Peak memory 201688 kb
Host smart-7fdd76ff-6a36-434b-9838-171249549aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552629004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2552629004
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1668079804
Short name T295
Test name
Test status
Simulation time 172447614802 ps
CPU time 111.98 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:27:47 PM PDT 24
Peak memory 201856 kb
Host smart-9dc5ca0b-65e9-4b7e-8dbb-840cfdd4b194
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668079804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1668079804
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1761205832
Short name T238
Test name
Test status
Simulation time 174738030232 ps
CPU time 202.83 seconds
Started Mar 26 12:25:58 PM PDT 24
Finished Mar 26 12:29:21 PM PDT 24
Peak memory 218940 kb
Host smart-efd8e759-6dd7-45eb-a77b-2f7c24a0c047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761205832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1761205832
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3403602521
Short name T361
Test name
Test status
Simulation time 357846603916 ps
CPU time 143.98 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:29:20 PM PDT 24
Peak memory 201616 kb
Host smart-e9698249-c8fb-416a-aa11-4f4a327df89a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403602521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3403602521
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3935111730
Short name T150
Test name
Test status
Simulation time 127590781165 ps
CPU time 671.73 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:38:26 PM PDT 24
Peak memory 202016 kb
Host smart-5d68f76c-3727-4163-a5d0-d8f63e888aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935111730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3935111730
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.727175942
Short name T235
Test name
Test status
Simulation time 87696637229 ps
CPU time 294.78 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:31:07 PM PDT 24
Peak memory 201996 kb
Host smart-34f5ed0b-cbe2-43d8-8cd8-229de219c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727175942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.727175942
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3613847698
Short name T259
Test name
Test status
Simulation time 495212459913 ps
CPU time 164.19 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:30:52 PM PDT 24
Peak memory 201312 kb
Host smart-9640358c-fdb6-445d-b84b-886897e820f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613847698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3613847698
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3461576318
Short name T231
Test name
Test status
Simulation time 900259503401 ps
CPU time 1283.31 seconds
Started Mar 26 12:27:25 PM PDT 24
Finished Mar 26 12:48:48 PM PDT 24
Peak memory 210404 kb
Host smart-24f6bbe1-821f-4a2c-a86a-77e3ea635c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461576318 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3461576318
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2323215011
Short name T306
Test name
Test status
Simulation time 502535379746 ps
CPU time 297.55 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:33:20 PM PDT 24
Peak memory 201792 kb
Host smart-9ce63759-d18d-44cf-b4f4-b554126b116a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323215011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2323215011
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2321413786
Short name T185
Test name
Test status
Simulation time 554470839656 ps
CPU time 338.92 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:31:51 PM PDT 24
Peak memory 201880 kb
Host smart-34fb0175-7c48-433c-8a75-51239dcb6e3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321413786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2321413786
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1696677777
Short name T20
Test name
Test status
Simulation time 125195814365 ps
CPU time 129.42 seconds
Started Mar 26 12:27:25 PM PDT 24
Finished Mar 26 12:29:34 PM PDT 24
Peak memory 212404 kb
Host smart-03078d25-6b23-47de-8be5-3e0024560f1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696677777 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1696677777
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3436584542
Short name T171
Test name
Test status
Simulation time 359324229499 ps
CPU time 298.36 seconds
Started Mar 26 12:27:50 PM PDT 24
Finished Mar 26 12:32:48 PM PDT 24
Peak memory 201724 kb
Host smart-36b0bc0c-7289-44ac-a507-3859900578de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436584542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3436584542
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2945725001
Short name T236
Test name
Test status
Simulation time 77765534845 ps
CPU time 456.77 seconds
Started Mar 26 12:27:49 PM PDT 24
Finished Mar 26 12:35:26 PM PDT 24
Peak memory 202024 kb
Host smart-c5461161-afc4-4319-9053-abd5fd3e2b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945725001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2945725001
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3595989099
Short name T40
Test name
Test status
Simulation time 107287737487 ps
CPU time 105.45 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:30:07 PM PDT 24
Peak memory 217716 kb
Host smart-66aab420-9efc-41d6-8efb-ff2df6ec6420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595989099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3595989099
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4276256545
Short name T136
Test name
Test status
Simulation time 1309647632 ps
CPU time 3.84 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:40 PM PDT 24
Peak memory 199948 kb
Host smart-8ba48432-7ba1-4013-a739-f6390f19fb06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276256545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.4276256545
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2499786023
Short name T119
Test name
Test status
Simulation time 1213218801 ps
CPU time 1.1 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 199648 kb
Host smart-0a50b2be-028e-41b8-814a-e8e9b0bb5f83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499786023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2499786023
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1345664039
Short name T862
Test name
Test status
Simulation time 622116451 ps
CPU time 2.29 seconds
Started Mar 26 12:22:19 PM PDT 24
Finished Mar 26 12:22:22 PM PDT 24
Peak memory 201608 kb
Host smart-c5e38703-fb3e-4b38-a91b-1cd6e043377d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345664039 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1345664039
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2586697811
Short name T875
Test name
Test status
Simulation time 296033020 ps
CPU time 0.95 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 200028 kb
Host smart-fe49097b-fc9a-436b-8ab3-dd39b0eb7013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586697811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2586697811
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2606977697
Short name T853
Test name
Test status
Simulation time 3080332762 ps
CPU time 12.9 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 201632 kb
Host smart-4ba4818a-5383-4ec5-bdf2-4831c642abb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606977697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2606977697
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3609595420
Short name T867
Test name
Test status
Simulation time 440971010 ps
CPU time 3.14 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:39 PM PDT 24
Peak memory 216160 kb
Host smart-53ae950a-9876-4d79-a0e9-5342b42c4517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609595420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3609595420
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.896710067
Short name T817
Test name
Test status
Simulation time 4471996780 ps
CPU time 7.06 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 201528 kb
Host smart-2d708537-137f-46fd-b442-93908ced66a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896710067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.896710067
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1339682858
Short name T126
Test name
Test status
Simulation time 1153937141 ps
CPU time 5.52 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:41 PM PDT 24
Peak memory 199508 kb
Host smart-90957c63-8ef0-4a29-82ab-946d59e4b792
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339682858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1339682858
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2836814038
Short name T888
Test name
Test status
Simulation time 26949886115 ps
CPU time 107.69 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:26:57 PM PDT 24
Peak memory 199644 kb
Host smart-f75b6c0b-17af-45a6-81e8-b7cd8201abb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836814038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2836814038
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3843582191
Short name T900
Test name
Test status
Simulation time 719792497 ps
CPU time 1.61 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:38 PM PDT 24
Peak memory 201360 kb
Host smart-16ec90cd-6bce-4c16-a778-41ca97fdea40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843582191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3843582191
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1917183397
Short name T107
Test name
Test status
Simulation time 362052706 ps
CPU time 1.73 seconds
Started Mar 26 12:22:18 PM PDT 24
Finished Mar 26 12:22:21 PM PDT 24
Peak memory 201568 kb
Host smart-d4dbbb1b-1e7b-482a-bab8-7f42c3b1d745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917183397 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1917183397
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1894559027
Short name T844
Test name
Test status
Simulation time 373417147 ps
CPU time 1.05 seconds
Started Mar 26 12:24:30 PM PDT 24
Finished Mar 26 12:24:31 PM PDT 24
Peak memory 201560 kb
Host smart-6bd2716b-b2cc-48bf-b83c-10a8653736ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894559027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1894559027
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.976646989
Short name T903
Test name
Test status
Simulation time 533136578 ps
CPU time 0.79 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 199160 kb
Host smart-a567ac07-0db4-4555-b666-4e734b9a154e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976646989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.976646989
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2941062420
Short name T131
Test name
Test status
Simulation time 2155065774 ps
CPU time 6.93 seconds
Started Mar 26 12:25:40 PM PDT 24
Finished Mar 26 12:25:47 PM PDT 24
Peak memory 201572 kb
Host smart-dae4036f-1c4b-43c9-a20b-8bcc178b263a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941062420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2941062420
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.822024435
Short name T823
Test name
Test status
Simulation time 618810442 ps
CPU time 1.38 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 200492 kb
Host smart-8e8feea6-8074-4434-b27f-a0a5f310ee9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822024435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.822024435
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.914812657
Short name T838
Test name
Test status
Simulation time 348806161 ps
CPU time 1.21 seconds
Started Mar 26 12:22:53 PM PDT 24
Finished Mar 26 12:22:54 PM PDT 24
Peak memory 201620 kb
Host smart-3373d303-4b5c-4dd6-af06-343ca4bb3143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914812657 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.914812657
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1641157118
Short name T123
Test name
Test status
Simulation time 465834503 ps
CPU time 1.91 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:24 PM PDT 24
Peak memory 199492 kb
Host smart-8dd7ddb0-48ee-447a-8fd7-827218de4ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641157118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1641157118
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.564897562
Short name T892
Test name
Test status
Simulation time 512594833 ps
CPU time 0.81 seconds
Started Mar 26 12:26:49 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 200732 kb
Host smart-d11d7255-5193-4c8f-9ce3-9f1123ae85a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564897562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.564897562
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2692614595
Short name T886
Test name
Test status
Simulation time 3599473964 ps
CPU time 5.67 seconds
Started Mar 26 12:23:19 PM PDT 24
Finished Mar 26 12:23:25 PM PDT 24
Peak memory 201812 kb
Host smart-9ca12043-8eaa-451c-b477-a784bc37ec4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692614595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2692614595
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.77863994
Short name T65
Test name
Test status
Simulation time 490458783 ps
CPU time 2.47 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 199656 kb
Host smart-4b822d11-7f7c-4767-bf0a-246c76b7f8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77863994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.77863994
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3678431963
Short name T907
Test name
Test status
Simulation time 4295385832 ps
CPU time 11.62 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 201768 kb
Host smart-350fd7fe-6043-4d86-a118-cf5254d80636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678431963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3678431963
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3317889341
Short name T76
Test name
Test status
Simulation time 555614661 ps
CPU time 1.24 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:40 PM PDT 24
Peak memory 201472 kb
Host smart-243d4068-2bd7-4fa0-9f2d-9248009cd449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317889341 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3317889341
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.35168987
Short name T121
Test name
Test status
Simulation time 312074209 ps
CPU time 1.58 seconds
Started Mar 26 12:22:44 PM PDT 24
Finished Mar 26 12:22:46 PM PDT 24
Peak memory 201536 kb
Host smart-0416bb8d-d5c2-476d-b5fc-ee2baac9f061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35168987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.35168987
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3872629078
Short name T847
Test name
Test status
Simulation time 346055990 ps
CPU time 0.86 seconds
Started Mar 26 12:23:21 PM PDT 24
Finished Mar 26 12:23:22 PM PDT 24
Peak memory 201544 kb
Host smart-29bf1ba7-5a27-4d22-b8d2-430c28314a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872629078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3872629078
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2213194613
Short name T868
Test name
Test status
Simulation time 2227826096 ps
CPU time 2.96 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:22 PM PDT 24
Peak memory 201624 kb
Host smart-00a3fa15-b497-4adb-be35-d6f18a567ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213194613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2213194613
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1858269533
Short name T866
Test name
Test status
Simulation time 667406838 ps
CPU time 3.08 seconds
Started Mar 26 12:23:07 PM PDT 24
Finished Mar 26 12:23:10 PM PDT 24
Peak memory 201860 kb
Host smart-3454bd28-aa29-4b1b-a381-a3b6d5d27bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858269533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1858269533
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2809936945
Short name T374
Test name
Test status
Simulation time 8146798648 ps
CPU time 7.26 seconds
Started Mar 26 12:25:25 PM PDT 24
Finished Mar 26 12:25:33 PM PDT 24
Peak memory 201620 kb
Host smart-d2ede6d0-b8ce-4a93-a9ee-33add93d7c71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809936945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2809936945
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.710639461
Short name T884
Test name
Test status
Simulation time 523005386 ps
CPU time 2 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 201548 kb
Host smart-ec2df84a-ddcf-4370-9734-f76c24cbc5c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710639461 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.710639461
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1252693214
Short name T118
Test name
Test status
Simulation time 324345484 ps
CPU time 1.12 seconds
Started Mar 26 12:27:04 PM PDT 24
Finished Mar 26 12:27:05 PM PDT 24
Peak memory 201544 kb
Host smart-8e045819-ebb0-4ca3-a9c3-202406bd48ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252693214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1252693214
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3984026922
Short name T806
Test name
Test status
Simulation time 322639010 ps
CPU time 1.29 seconds
Started Mar 26 12:26:20 PM PDT 24
Finished Mar 26 12:26:21 PM PDT 24
Peak memory 201212 kb
Host smart-afec8bff-d8db-4a7e-9482-09bc04c58e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984026922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3984026922
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.711459191
Short name T133
Test name
Test status
Simulation time 4108725218 ps
CPU time 9.03 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:58 PM PDT 24
Peak memory 200684 kb
Host smart-f594ba70-b0a4-40b4-a76f-ee1c3942aaac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711459191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.711459191
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3994842149
Short name T70
Test name
Test status
Simulation time 537764978 ps
CPU time 1.9 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 200608 kb
Host smart-211622b7-ac64-47ea-988f-5d1be61c00ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994842149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3994842149
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3009206080
Short name T882
Test name
Test status
Simulation time 4403852810 ps
CPU time 11.77 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 201844 kb
Host smart-d949e7f2-ceff-4fc7-a10a-b28b3c15e38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009206080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3009206080
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.62721296
Short name T831
Test name
Test status
Simulation time 416785465 ps
CPU time 1.99 seconds
Started Mar 26 12:23:00 PM PDT 24
Finished Mar 26 12:23:03 PM PDT 24
Peak memory 200792 kb
Host smart-7fa5c6e6-69f3-46f7-bf6b-36184a8bd425
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62721296 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.62721296
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2109013619
Short name T130
Test name
Test status
Simulation time 470203282 ps
CPU time 1.94 seconds
Started Mar 26 12:26:42 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 201264 kb
Host smart-9052e15d-9767-445b-8ba0-e96f2f866579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109013619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2109013619
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.205890552
Short name T813
Test name
Test status
Simulation time 576115363 ps
CPU time 0.82 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 199404 kb
Host smart-6582b6ad-697e-419b-b68f-2a8cfe5e3948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205890552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.205890552
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1221766341
Short name T843
Test name
Test status
Simulation time 2342279326 ps
CPU time 2.6 seconds
Started Mar 26 12:27:04 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 201604 kb
Host smart-4313fad7-7ded-4079-af4a-35e1ce1f9df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221766341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1221766341
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1339951843
Short name T913
Test name
Test status
Simulation time 1090458939 ps
CPU time 1.56 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 199776 kb
Host smart-a06ff0e7-9393-4924-ab72-141562f9bc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339951843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1339951843
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4067155138
Short name T856
Test name
Test status
Simulation time 418547252 ps
CPU time 1.9 seconds
Started Mar 26 12:22:52 PM PDT 24
Finished Mar 26 12:22:54 PM PDT 24
Peak memory 201620 kb
Host smart-fde9d61a-4ce1-4c0b-b195-42f4143c1286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067155138 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4067155138
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1742062369
Short name T117
Test name
Test status
Simulation time 352106982 ps
CPU time 0.88 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 201512 kb
Host smart-59f9882c-3a10-43b4-9442-4d260602076e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742062369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1742062369
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.190530903
Short name T877
Test name
Test status
Simulation time 373314014 ps
CPU time 0.96 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:38 PM PDT 24
Peak memory 201340 kb
Host smart-df6a9422-f6d8-430b-8082-0dd15c9caf9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190530903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.190530903
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3573820162
Short name T58
Test name
Test status
Simulation time 2291820545 ps
CPU time 2.04 seconds
Started Mar 26 12:27:07 PM PDT 24
Finished Mar 26 12:27:09 PM PDT 24
Peak memory 201252 kb
Host smart-89736482-664b-4527-9c79-95374669c084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573820162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3573820162
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2227048161
Short name T887
Test name
Test status
Simulation time 470482844 ps
CPU time 2.68 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:52 PM PDT 24
Peak memory 216184 kb
Host smart-40eb69e9-fd1b-4d69-bc80-8760ed4a4360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227048161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2227048161
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4234886830
Short name T846
Test name
Test status
Simulation time 8750235715 ps
CPU time 7.48 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:26:41 PM PDT 24
Peak memory 201724 kb
Host smart-05e0e4e3-c9ca-4bc5-8f5e-6a69893968eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234886830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4234886830
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3748190930
Short name T80
Test name
Test status
Simulation time 350925922 ps
CPU time 1.72 seconds
Started Mar 26 12:22:59 PM PDT 24
Finished Mar 26 12:23:01 PM PDT 24
Peak memory 201600 kb
Host smart-ee96e302-4a00-47c4-ab36-1ade02509b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748190930 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3748190930
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2331281894
Short name T909
Test name
Test status
Simulation time 313181475 ps
CPU time 1.46 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 201480 kb
Host smart-5cae9d3e-a33e-4520-94c8-d20eab86a132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331281894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2331281894
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3352491638
Short name T880
Test name
Test status
Simulation time 394452538 ps
CPU time 1.57 seconds
Started Mar 26 12:24:32 PM PDT 24
Finished Mar 26 12:24:34 PM PDT 24
Peak memory 201532 kb
Host smart-72a6a2ee-f573-413d-8a90-58ae0118b3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352491638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3352491638
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4153718416
Short name T132
Test name
Test status
Simulation time 2112985388 ps
CPU time 5.37 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:27:09 PM PDT 24
Peak memory 201544 kb
Host smart-c38d43a3-edbe-4af4-8f68-fa27b645653b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153718416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.4153718416
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1258548817
Short name T75
Test name
Test status
Simulation time 399432843 ps
CPU time 2.3 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:35 PM PDT 24
Peak memory 201852 kb
Host smart-93a07234-5b5f-4862-b843-5dbad1c099b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258548817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1258548817
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.580814737
Short name T916
Test name
Test status
Simulation time 4328782298 ps
CPU time 6.14 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 200400 kb
Host smart-4a64bcbf-c1a4-4c48-8582-0f1c11405176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580814737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.580814737
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1773592322
Short name T837
Test name
Test status
Simulation time 645563743 ps
CPU time 2.38 seconds
Started Mar 26 12:26:30 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 201604 kb
Host smart-578537a3-c6da-439f-87c6-39f900fc1376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773592322 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1773592322
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3652183586
Short name T883
Test name
Test status
Simulation time 535304576 ps
CPU time 1.41 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:21 PM PDT 24
Peak memory 200508 kb
Host smart-9f004dd6-2c07-4244-b60d-ecfacc5a1a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652183586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3652183586
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1625605880
Short name T809
Test name
Test status
Simulation time 453523897 ps
CPU time 1.66 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:08 PM PDT 24
Peak memory 200304 kb
Host smart-bd1f8425-79bb-4866-8070-b4908105c5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625605880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1625605880
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2139450266
Short name T825
Test name
Test status
Simulation time 2375458248 ps
CPU time 3.09 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:35 PM PDT 24
Peak memory 201608 kb
Host smart-379bb7bf-04d8-4dee-96cb-dd2243c523e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139450266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2139450266
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.439713727
Short name T858
Test name
Test status
Simulation time 797413352 ps
CPU time 2.66 seconds
Started Mar 26 12:26:49 PM PDT 24
Finished Mar 26 12:26:52 PM PDT 24
Peak memory 217256 kb
Host smart-a685cef4-b2ba-4aba-99e4-bacda06dba1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439713727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.439713727
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4102900119
Short name T815
Test name
Test status
Simulation time 4736177700 ps
CPU time 13.25 seconds
Started Mar 26 12:24:17 PM PDT 24
Finished Mar 26 12:24:31 PM PDT 24
Peak memory 201848 kb
Host smart-3e579f0d-e6c6-4809-9b13-79ecfb422348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102900119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4102900119
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.14072968
Short name T870
Test name
Test status
Simulation time 609207773 ps
CPU time 1.13 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:33 PM PDT 24
Peak memory 201604 kb
Host smart-6b3ed573-e15a-4388-9485-bd0e9bc0edd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14072968 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.14072968
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3390696083
Short name T857
Test name
Test status
Simulation time 458650540 ps
CPU time 0.89 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 200436 kb
Host smart-e1166bd2-1240-4203-b2d9-02a05fb84f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390696083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3390696083
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.85383130
Short name T803
Test name
Test status
Simulation time 367025341 ps
CPU time 1.46 seconds
Started Mar 26 12:24:33 PM PDT 24
Finished Mar 26 12:24:35 PM PDT 24
Peak memory 201556 kb
Host smart-33bca654-9579-43b9-9e0a-c0a8d2cc07bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85383130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.85383130
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1617831583
Short name T839
Test name
Test status
Simulation time 2560733268 ps
CPU time 6.74 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 201424 kb
Host smart-02b0c97c-e261-4307-9ea0-258c5e06ade1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617831583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1617831583
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2124397837
Short name T816
Test name
Test status
Simulation time 437658471 ps
CPU time 2.18 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:27:05 PM PDT 24
Peak memory 201848 kb
Host smart-17e1655a-25e6-459f-bec8-2c072f35bb8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124397837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2124397837
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3223342469
Short name T834
Test name
Test status
Simulation time 4151532381 ps
CPU time 5.83 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 200716 kb
Host smart-b214de8a-bab3-4a05-91f4-4df3f969b890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223342469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3223342469
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1866701665
Short name T871
Test name
Test status
Simulation time 426498997 ps
CPU time 1.93 seconds
Started Mar 26 12:24:23 PM PDT 24
Finished Mar 26 12:24:25 PM PDT 24
Peak memory 201604 kb
Host smart-3ae990ed-ef7d-4e2b-a1e1-8e6910ec99f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866701665 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1866701665
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3101742244
Short name T836
Test name
Test status
Simulation time 560225785 ps
CPU time 1.1 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 199552 kb
Host smart-6114e564-e38a-4070-ab92-1ec63d39c700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101742244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3101742244
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3541019074
Short name T812
Test name
Test status
Simulation time 548420542 ps
CPU time 0.96 seconds
Started Mar 26 12:24:32 PM PDT 24
Finished Mar 26 12:24:33 PM PDT 24
Peak memory 201544 kb
Host smart-675bde06-2b3f-4c28-b1cf-4b7518bfe2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541019074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3541019074
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1927225894
Short name T134
Test name
Test status
Simulation time 5296134854 ps
CPU time 5.85 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:26:39 PM PDT 24
Peak memory 201796 kb
Host smart-3f41e8f4-2bf8-4ca4-92f6-90669f6e67eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927225894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1927225894
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.336320008
Short name T77
Test name
Test status
Simulation time 821839738 ps
CPU time 1.44 seconds
Started Mar 26 12:26:20 PM PDT 24
Finished Mar 26 12:26:21 PM PDT 24
Peak memory 201452 kb
Host smart-2d6fcaad-11aa-4606-bd02-cc700973d5c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336320008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.336320008
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3167165917
Short name T908
Test name
Test status
Simulation time 831804960 ps
CPU time 1.26 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:24 PM PDT 24
Peak memory 200236 kb
Host smart-ee8e882c-b750-4d82-a554-f8c229e765f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167165917 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3167165917
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3209775679
Short name T895
Test name
Test status
Simulation time 418032245 ps
CPU time 1.29 seconds
Started Mar 26 12:22:59 PM PDT 24
Finished Mar 26 12:23:01 PM PDT 24
Peak memory 201576 kb
Host smart-f4b2d9aa-60e2-4156-b5ca-db5505052fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209775679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3209775679
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.66206028
Short name T840
Test name
Test status
Simulation time 513616427 ps
CPU time 1.22 seconds
Started Mar 26 12:26:49 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 201100 kb
Host smart-929bfa35-a0fd-4c97-91a5-3029212c3355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66206028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.66206028
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3767482935
Short name T832
Test name
Test status
Simulation time 4579006640 ps
CPU time 5.5 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:31 PM PDT 24
Peak memory 201784 kb
Host smart-cdd966b8-5bb7-4519-a12e-e49b1f116ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767482935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3767482935
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2855615477
Short name T373
Test name
Test status
Simulation time 4345850957 ps
CPU time 4.07 seconds
Started Mar 26 12:26:31 PM PDT 24
Finished Mar 26 12:26:36 PM PDT 24
Peak memory 201820 kb
Host smart-832e5130-035d-4f62-9be9-88b29dcb8277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855615477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2855615477
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3825090436
Short name T848
Test name
Test status
Simulation time 1266916266 ps
CPU time 3.23 seconds
Started Mar 26 12:23:36 PM PDT 24
Finished Mar 26 12:23:39 PM PDT 24
Peak memory 201732 kb
Host smart-804494b3-d754-41cb-b864-e437bd712fbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825090436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3825090436
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.221644089
Short name T890
Test name
Test status
Simulation time 26259838008 ps
CPU time 28.46 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:38 PM PDT 24
Peak memory 199532 kb
Host smart-46f0ea88-f6f1-4a5b-a031-f83fc09308a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221644089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.221644089
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3649172100
Short name T125
Test name
Test status
Simulation time 854774129 ps
CPU time 1.74 seconds
Started Mar 26 12:22:38 PM PDT 24
Finished Mar 26 12:22:40 PM PDT 24
Peak memory 201916 kb
Host smart-3e12b893-5a05-460d-b327-7af36a18ba45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649172100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3649172100
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.262264890
Short name T889
Test name
Test status
Simulation time 675037885 ps
CPU time 1.27 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:40 PM PDT 24
Peak memory 201548 kb
Host smart-ccd3fb8b-6b69-463a-8e5f-f5b634830b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262264890 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.262264890
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.513972195
Short name T129
Test name
Test status
Simulation time 355418796 ps
CPU time 1.72 seconds
Started Mar 26 12:21:44 PM PDT 24
Finished Mar 26 12:21:46 PM PDT 24
Peak memory 201544 kb
Host smart-87574d32-8a10-47bf-a829-adb0033aa34e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513972195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.513972195
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3470842253
Short name T811
Test name
Test status
Simulation time 521788379 ps
CPU time 1.38 seconds
Started Mar 26 12:25:09 PM PDT 24
Finished Mar 26 12:25:11 PM PDT 24
Peak memory 199544 kb
Host smart-00a7b6ac-3a37-434e-ae87-a4f42b410954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470842253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3470842253
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1049697278
Short name T852
Test name
Test status
Simulation time 2257116715 ps
CPU time 2.77 seconds
Started Mar 26 12:21:42 PM PDT 24
Finished Mar 26 12:21:48 PM PDT 24
Peak memory 201744 kb
Host smart-29c906df-0d86-442d-9cbe-19df52fea1c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049697278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1049697278
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.817530375
Short name T876
Test name
Test status
Simulation time 807361304 ps
CPU time 2.14 seconds
Started Mar 26 12:25:39 PM PDT 24
Finished Mar 26 12:25:42 PM PDT 24
Peak memory 201836 kb
Host smart-b60021b0-a1f0-478a-b1d2-c84ee6c1513f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817530375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.817530375
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2039448321
Short name T81
Test name
Test status
Simulation time 8572263898 ps
CPU time 10.74 seconds
Started Mar 26 12:22:19 PM PDT 24
Finished Mar 26 12:22:31 PM PDT 24
Peak memory 201840 kb
Host smart-a4983b95-425d-4ee2-9a38-27b1415d4d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039448321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2039448321
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1757551763
Short name T818
Test name
Test status
Simulation time 503345833 ps
CPU time 1.31 seconds
Started Mar 26 12:23:38 PM PDT 24
Finished Mar 26 12:23:40 PM PDT 24
Peak memory 201680 kb
Host smart-61560e91-e1f5-471f-abf3-a4feefe2a61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757551763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1757551763
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.182920706
Short name T893
Test name
Test status
Simulation time 438138426 ps
CPU time 1.22 seconds
Started Mar 26 12:23:13 PM PDT 24
Finished Mar 26 12:23:14 PM PDT 24
Peak memory 201564 kb
Host smart-bc47de8a-4832-4440-8d64-eb1c0fca69ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182920706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.182920706
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3539033255
Short name T829
Test name
Test status
Simulation time 484553468 ps
CPU time 0.98 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 199504 kb
Host smart-83f96e21-e781-47a0-a4ff-4467ab789d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539033255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3539033255
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3443270919
Short name T820
Test name
Test status
Simulation time 418268536 ps
CPU time 1.5 seconds
Started Mar 26 12:23:08 PM PDT 24
Finished Mar 26 12:23:09 PM PDT 24
Peak memory 201468 kb
Host smart-b6470530-368f-41d8-8a8c-56622fc02d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443270919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3443270919
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3181193523
Short name T918
Test name
Test status
Simulation time 486267547 ps
CPU time 1.84 seconds
Started Mar 26 12:25:26 PM PDT 24
Finished Mar 26 12:25:28 PM PDT 24
Peak memory 200040 kb
Host smart-f8ac5943-d875-43fd-87fd-d8c8f4d7cef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181193523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3181193523
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1241753571
Short name T881
Test name
Test status
Simulation time 412157496 ps
CPU time 1.13 seconds
Started Mar 26 12:23:50 PM PDT 24
Finished Mar 26 12:23:52 PM PDT 24
Peak memory 201556 kb
Host smart-286b75c1-5fea-4b93-999f-fcc30a5e35f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241753571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1241753571
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.767536839
Short name T894
Test name
Test status
Simulation time 517559407 ps
CPU time 1.84 seconds
Started Mar 26 12:25:26 PM PDT 24
Finished Mar 26 12:25:28 PM PDT 24
Peak memory 200240 kb
Host smart-f23b0c18-6067-4402-a639-0262dd3b0b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767536839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.767536839
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.474711286
Short name T874
Test name
Test status
Simulation time 455682384 ps
CPU time 0.91 seconds
Started Mar 26 12:25:26 PM PDT 24
Finished Mar 26 12:25:27 PM PDT 24
Peak memory 199956 kb
Host smart-875657a2-e96f-4b95-b146-5f4994cb2f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474711286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.474711286
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.88036629
Short name T851
Test name
Test status
Simulation time 473639491 ps
CPU time 1.17 seconds
Started Mar 26 12:23:20 PM PDT 24
Finished Mar 26 12:23:22 PM PDT 24
Peak memory 201552 kb
Host smart-76593574-6ac0-47df-8b65-be9ea91263d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88036629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.88036629
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1866443717
Short name T901
Test name
Test status
Simulation time 381678705 ps
CPU time 0.94 seconds
Started Mar 26 12:23:10 PM PDT 24
Finished Mar 26 12:23:12 PM PDT 24
Peak memory 201544 kb
Host smart-b8fcf0b2-f516-4bed-aecc-b8edce2bb827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866443717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1866443717
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2320394351
Short name T127
Test name
Test status
Simulation time 698235736 ps
CPU time 3.1 seconds
Started Mar 26 12:22:08 PM PDT 24
Finished Mar 26 12:22:12 PM PDT 24
Peak memory 201756 kb
Host smart-8338b062-6edb-4ada-9b92-438bbca66c5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320394351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2320394351
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2192478150
Short name T56
Test name
Test status
Simulation time 36688785777 ps
CPU time 46.24 seconds
Started Mar 26 12:22:00 PM PDT 24
Finished Mar 26 12:22:47 PM PDT 24
Peak memory 202160 kb
Host smart-0dd29f46-5327-49fc-bea4-56a94ce9f195
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192478150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2192478150
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2176298268
Short name T897
Test name
Test status
Simulation time 814700527 ps
CPU time 2.46 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 201500 kb
Host smart-200cd84c-3afe-4436-b074-7afa851521f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176298268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2176298268
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.410314718
Short name T898
Test name
Test status
Simulation time 664038355 ps
CPU time 1.09 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 201536 kb
Host smart-5470eb80-0b87-4b8b-98b3-b33e6c6534bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410314718 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.410314718
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3088605032
Short name T914
Test name
Test status
Simulation time 495990304 ps
CPU time 2.03 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:41 PM PDT 24
Peak memory 201508 kb
Host smart-ec9e546b-0a03-4087-a23e-960eb5884f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088605032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3088605032
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.283132626
Short name T807
Test name
Test status
Simulation time 489810475 ps
CPU time 1.22 seconds
Started Mar 26 12:26:38 PM PDT 24
Finished Mar 26 12:26:39 PM PDT 24
Peak memory 201488 kb
Host smart-6bc79c74-a018-45fd-856d-08d7cceb80a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283132626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.283132626
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.88973624
Short name T859
Test name
Test status
Simulation time 5042563855 ps
CPU time 11.51 seconds
Started Mar 26 12:21:54 PM PDT 24
Finished Mar 26 12:22:06 PM PDT 24
Peak memory 201804 kb
Host smart-7e957817-2eea-464d-b083-dfd2a8bc93b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88973624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctr
l_same_csr_outstanding.88973624
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1541971191
Short name T911
Test name
Test status
Simulation time 939471572 ps
CPU time 2.34 seconds
Started Mar 26 12:21:52 PM PDT 24
Finished Mar 26 12:21:54 PM PDT 24
Peak memory 218100 kb
Host smart-0fedf7b8-9787-45cf-a845-cbd573b3b84c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541971191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1541971191
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142487339
Short name T66
Test name
Test status
Simulation time 4367958035 ps
CPU time 12.88 seconds
Started Mar 26 12:23:28 PM PDT 24
Finished Mar 26 12:23:41 PM PDT 24
Peak memory 201840 kb
Host smart-ba1aa6b1-73a2-465e-9693-cd025c813039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142487339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.142487339
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3332596783
Short name T805
Test name
Test status
Simulation time 395254780 ps
CPU time 0.9 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 201500 kb
Host smart-44412ff6-4ba8-4ad6-9f09-40f785f36f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332596783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3332596783
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1586253325
Short name T917
Test name
Test status
Simulation time 527984143 ps
CPU time 1.88 seconds
Started Mar 26 12:23:13 PM PDT 24
Finished Mar 26 12:23:15 PM PDT 24
Peak memory 201676 kb
Host smart-984ba397-8eb8-44a2-9580-1ff32d4908e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586253325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1586253325
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.426568058
Short name T808
Test name
Test status
Simulation time 361160241 ps
CPU time 0.83 seconds
Started Mar 26 12:23:44 PM PDT 24
Finished Mar 26 12:23:46 PM PDT 24
Peak memory 201572 kb
Host smart-62b9ab31-0937-4c67-b3c8-6e2f7f850b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426568058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.426568058
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2951406698
Short name T850
Test name
Test status
Simulation time 503575067 ps
CPU time 1.88 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:24 PM PDT 24
Peak memory 200536 kb
Host smart-542d8e1a-9ab7-4b61-acdc-32ce0709f91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951406698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2951406698
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.4092939464
Short name T885
Test name
Test status
Simulation time 326945441 ps
CPU time 1.32 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 201488 kb
Host smart-2a9d57bc-9953-455b-bed7-09a5381e07fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092939464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4092939464
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3615152989
Short name T819
Test name
Test status
Simulation time 398846019 ps
CPU time 0.84 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:25 PM PDT 24
Peak memory 201492 kb
Host smart-665a4b4e-6048-4d56-9776-e0c831cd43cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615152989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3615152989
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.358204881
Short name T879
Test name
Test status
Simulation time 453954340 ps
CPU time 0.91 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 200020 kb
Host smart-a6207d23-6565-4cd7-b15a-854f0ec02886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358204881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.358204881
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2728978395
Short name T855
Test name
Test status
Simulation time 518255156 ps
CPU time 0.92 seconds
Started Mar 26 12:24:59 PM PDT 24
Finished Mar 26 12:25:00 PM PDT 24
Peak memory 201880 kb
Host smart-fad9e96d-5ad7-429a-a40d-100a635ee5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728978395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2728978395
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.341384091
Short name T904
Test name
Test status
Simulation time 376517609 ps
CPU time 0.84 seconds
Started Mar 26 12:25:26 PM PDT 24
Finished Mar 26 12:25:28 PM PDT 24
Peak memory 201892 kb
Host smart-fe1834d6-2084-418f-9245-d50883652ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341384091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.341384091
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.294979377
Short name T861
Test name
Test status
Simulation time 377381109 ps
CPU time 1.2 seconds
Started Mar 26 12:23:34 PM PDT 24
Finished Mar 26 12:23:35 PM PDT 24
Peak memory 201564 kb
Host smart-34068322-4e0f-4d6e-b81f-6f3b038faa8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294979377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.294979377
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.258711380
Short name T841
Test name
Test status
Simulation time 1210897504 ps
CPU time 5.9 seconds
Started Mar 26 12:24:41 PM PDT 24
Finished Mar 26 12:24:47 PM PDT 24
Peak memory 201760 kb
Host smart-6c5999dd-3bd0-4894-a0fb-b008c7c515aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258711380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.258711380
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1572035312
Short name T128
Test name
Test status
Simulation time 6168097773 ps
CPU time 5.59 seconds
Started Mar 26 12:24:41 PM PDT 24
Finished Mar 26 12:24:47 PM PDT 24
Peak memory 201840 kb
Host smart-f3e001c1-9e13-49a3-ad39-ee205c0de906
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572035312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1572035312
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.86636262
Short name T821
Test name
Test status
Simulation time 974505757 ps
CPU time 3.2 seconds
Started Mar 26 12:24:39 PM PDT 24
Finished Mar 26 12:24:43 PM PDT 24
Peak memory 201884 kb
Host smart-44588650-9652-43a5-9327-233b94429924
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86636262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_res
et.86636262
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2625628373
Short name T905
Test name
Test status
Simulation time 487297177 ps
CPU time 1.25 seconds
Started Mar 26 12:25:08 PM PDT 24
Finished Mar 26 12:25:10 PM PDT 24
Peak memory 200524 kb
Host smart-c40c41b6-2d00-47c5-bf74-4a79bd6bd795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625628373 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2625628373
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1604831343
Short name T124
Test name
Test status
Simulation time 330957906 ps
CPU time 1.16 seconds
Started Mar 26 12:23:49 PM PDT 24
Finished Mar 26 12:23:51 PM PDT 24
Peak memory 201904 kb
Host smart-b5a0fe9f-b9ea-4574-bf30-aa15aae183d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604831343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1604831343
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.224554692
Short name T833
Test name
Test status
Simulation time 350868991 ps
CPU time 0.72 seconds
Started Mar 26 12:26:14 PM PDT 24
Finished Mar 26 12:26:15 PM PDT 24
Peak memory 201232 kb
Host smart-50f19ac2-ea99-4da5-8ab7-64cbdb0792b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224554692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.224554692
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1115158118
Short name T135
Test name
Test status
Simulation time 4708688699 ps
CPU time 6.49 seconds
Started Mar 26 12:26:38 PM PDT 24
Finished Mar 26 12:26:45 PM PDT 24
Peak memory 201828 kb
Host smart-0195e9bd-eedf-4024-9e6c-f1014fa1ff56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115158118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1115158118
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2217561397
Short name T860
Test name
Test status
Simulation time 310477895 ps
CPU time 2.15 seconds
Started Mar 26 12:24:39 PM PDT 24
Finished Mar 26 12:24:41 PM PDT 24
Peak memory 201808 kb
Host smart-5a798af4-0b74-4ac9-a8c7-2a72b403a847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217561397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2217561397
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1483798678
Short name T376
Test name
Test status
Simulation time 4341397811 ps
CPU time 3.98 seconds
Started Mar 26 12:25:49 PM PDT 24
Finished Mar 26 12:25:53 PM PDT 24
Peak memory 201532 kb
Host smart-3b3fccc0-6077-4b77-96c2-ae3831488646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483798678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1483798678
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.513903262
Short name T865
Test name
Test status
Simulation time 457639334 ps
CPU time 1.74 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:08 PM PDT 24
Peak memory 200676 kb
Host smart-6e790d8a-72ca-4685-b429-90cf0784bb36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513903262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.513903262
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.641009226
Short name T891
Test name
Test status
Simulation time 403767535 ps
CPU time 0.78 seconds
Started Mar 26 12:24:45 PM PDT 24
Finished Mar 26 12:24:45 PM PDT 24
Peak memory 201664 kb
Host smart-2f5812da-40e9-4c51-b262-38a8cd2f94b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641009226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.641009226
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2020512385
Short name T810
Test name
Test status
Simulation time 281901916 ps
CPU time 1.26 seconds
Started Mar 26 12:26:32 PM PDT 24
Finished Mar 26 12:26:35 PM PDT 24
Peak memory 200628 kb
Host smart-00847568-f5a1-4340-8db6-a4b648032e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020512385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2020512385
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.917069362
Short name T872
Test name
Test status
Simulation time 363215740 ps
CPU time 1.51 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:08 PM PDT 24
Peak memory 201284 kb
Host smart-df561c55-1d48-44de-a0ee-b55a577d9f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917069362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.917069362
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4265880743
Short name T910
Test name
Test status
Simulation time 398231561 ps
CPU time 1.57 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 201516 kb
Host smart-62c000cd-38df-4042-b0e7-f71331ea40f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265880743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4265880743
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3835236785
Short name T804
Test name
Test status
Simulation time 382331252 ps
CPU time 1.51 seconds
Started Mar 26 12:24:56 PM PDT 24
Finished Mar 26 12:24:58 PM PDT 24
Peak memory 201576 kb
Host smart-3aac18f5-fa1e-4eb3-89d0-cdf8832caa97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835236785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3835236785
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.648492493
Short name T814
Test name
Test status
Simulation time 336163504 ps
CPU time 0.86 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:27:09 PM PDT 24
Peak memory 201508 kb
Host smart-508aca05-9534-4cb1-8ed5-bcabd58ece26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648492493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.648492493
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3850136886
Short name T912
Test name
Test status
Simulation time 435128819 ps
CPU time 1.72 seconds
Started Mar 26 12:23:30 PM PDT 24
Finished Mar 26 12:23:32 PM PDT 24
Peak memory 201880 kb
Host smart-ff2ca4b7-68dc-4ff5-8efe-6495d950bb2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850136886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3850136886
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.991202133
Short name T878
Test name
Test status
Simulation time 367159066 ps
CPU time 1.4 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:26:49 PM PDT 24
Peak memory 201500 kb
Host smart-6fcded69-0efd-465a-9bf0-c648288e4b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991202133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.991202133
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.595196002
Short name T822
Test name
Test status
Simulation time 469406628 ps
CPU time 1.83 seconds
Started Mar 26 12:26:32 PM PDT 24
Finished Mar 26 12:26:35 PM PDT 24
Peak memory 200480 kb
Host smart-076128ff-c777-4610-8adb-0de5aeeea09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595196002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.595196002
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3525209265
Short name T845
Test name
Test status
Simulation time 543461955 ps
CPU time 2.07 seconds
Started Mar 26 12:22:20 PM PDT 24
Finished Mar 26 12:22:23 PM PDT 24
Peak memory 201548 kb
Host smart-10c9b9dd-0254-4ea7-9621-b072378bf535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525209265 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3525209265
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3741496497
Short name T902
Test name
Test status
Simulation time 333427872 ps
CPU time 1.48 seconds
Started Mar 26 12:26:36 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 201480 kb
Host smart-9e0d8f5e-fdba-447d-8ac9-a4e0dd7fb5db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741496497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3741496497
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1788072805
Short name T830
Test name
Test status
Simulation time 416741610 ps
CPU time 1.73 seconds
Started Mar 26 12:24:39 PM PDT 24
Finished Mar 26 12:24:41 PM PDT 24
Peak memory 201548 kb
Host smart-368d9163-d252-4cad-9197-e1ba323170ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788072805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1788072805
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1267567029
Short name T826
Test name
Test status
Simulation time 4282043558 ps
CPU time 4.65 seconds
Started Mar 26 12:24:01 PM PDT 24
Finished Mar 26 12:24:06 PM PDT 24
Peak memory 202168 kb
Host smart-19735915-3e4f-4f5d-afa0-95e3f8d79378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267567029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1267567029
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3893141343
Short name T863
Test name
Test status
Simulation time 411312161 ps
CPU time 2.62 seconds
Started Mar 26 12:26:14 PM PDT 24
Finished Mar 26 12:26:17 PM PDT 24
Peak memory 217288 kb
Host smart-e554e2a4-9ce4-4186-9787-2e5516143d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893141343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3893141343
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2143494537
Short name T62
Test name
Test status
Simulation time 4780123804 ps
CPU time 11.78 seconds
Started Mar 26 12:26:38 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 201824 kb
Host smart-6d967a75-a23f-4fde-96f4-c419b59a64d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143494537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2143494537
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.230671645
Short name T64
Test name
Test status
Simulation time 514492574 ps
CPU time 1.4 seconds
Started Mar 26 12:23:01 PM PDT 24
Finished Mar 26 12:23:02 PM PDT 24
Peak memory 201636 kb
Host smart-941d20a2-a516-4518-8b0a-dde8130fa843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230671645 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.230671645
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2487782599
Short name T835
Test name
Test status
Simulation time 503537769 ps
CPU time 0.9 seconds
Started Mar 26 12:26:38 PM PDT 24
Finished Mar 26 12:26:39 PM PDT 24
Peak memory 201548 kb
Host smart-36494646-08be-4410-973b-0c708e8b40fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487782599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2487782599
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1674449488
Short name T869
Test name
Test status
Simulation time 323050200 ps
CPU time 1.46 seconds
Started Mar 26 12:22:26 PM PDT 24
Finished Mar 26 12:22:28 PM PDT 24
Peak memory 201656 kb
Host smart-6790d13e-b666-494b-9a8b-c75aed9dcff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674449488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1674449488
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2199166820
Short name T899
Test name
Test status
Simulation time 3579797734 ps
CPU time 14.68 seconds
Started Mar 26 12:24:20 PM PDT 24
Finished Mar 26 12:24:35 PM PDT 24
Peak memory 201808 kb
Host smart-cec24da6-8270-4cc4-aad8-2ee720a93315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199166820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2199166820
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.75713080
Short name T849
Test name
Test status
Simulation time 4499441561 ps
CPU time 4.2 seconds
Started Mar 26 12:24:03 PM PDT 24
Finished Mar 26 12:24:07 PM PDT 24
Peak memory 201844 kb
Host smart-85b4bb04-cddc-48b1-be61-f2f2820acbd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75713080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg
_err.75713080
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4076786608
Short name T873
Test name
Test status
Simulation time 544705729 ps
CPU time 1.17 seconds
Started Mar 26 12:22:42 PM PDT 24
Finished Mar 26 12:22:43 PM PDT 24
Peak memory 201628 kb
Host smart-b35093b7-b203-45ec-be75-482d89ab0fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076786608 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4076786608
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.316158663
Short name T915
Test name
Test status
Simulation time 509103810 ps
CPU time 1.93 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 199708 kb
Host smart-8d69606c-8ff6-468e-a897-6026bce7f131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316158663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.316158663
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1585844403
Short name T854
Test name
Test status
Simulation time 450583080 ps
CPU time 0.91 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:23 PM PDT 24
Peak memory 199452 kb
Host smart-46c8b9b0-7426-4522-bbd5-432fb7296704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585844403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1585844403
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2759167477
Short name T827
Test name
Test status
Simulation time 2771042420 ps
CPU time 2.49 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:41 PM PDT 24
Peak memory 201768 kb
Host smart-6ed419a0-5b2b-4209-979d-548d093d17ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759167477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2759167477
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.119993293
Short name T906
Test name
Test status
Simulation time 491321186 ps
CPU time 3.37 seconds
Started Mar 26 12:25:48 PM PDT 24
Finished Mar 26 12:25:52 PM PDT 24
Peak memory 201016 kb
Host smart-5f116bbc-22fd-46bc-924b-540730fa03c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119993293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.119993293
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1365497007
Short name T74
Test name
Test status
Simulation time 3931501681 ps
CPU time 5.98 seconds
Started Mar 26 12:25:25 PM PDT 24
Finished Mar 26 12:25:31 PM PDT 24
Peak memory 201776 kb
Host smart-123a2676-4c5d-4b62-a72b-cbe65db647f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365497007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1365497007
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.780423380
Short name T93
Test name
Test status
Simulation time 594420335 ps
CPU time 1.17 seconds
Started Mar 26 12:22:44 PM PDT 24
Finished Mar 26 12:22:46 PM PDT 24
Peak memory 201640 kb
Host smart-1abef4bb-fcd1-4327-8b34-d66ba8156a31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780423380 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.780423380
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1253807980
Short name T828
Test name
Test status
Simulation time 530773384 ps
CPU time 1.05 seconds
Started Mar 26 12:23:22 PM PDT 24
Finished Mar 26 12:23:23 PM PDT 24
Peak memory 201896 kb
Host smart-245a4194-2012-44c9-899b-7e66ee009e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253807980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1253807980
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1034569265
Short name T802
Test name
Test status
Simulation time 495480526 ps
CPU time 1.18 seconds
Started Mar 26 12:25:19 PM PDT 24
Finished Mar 26 12:25:20 PM PDT 24
Peak memory 201556 kb
Host smart-0e386543-ceeb-40ed-a4f0-22212e242b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034569265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1034569265
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1333875362
Short name T57
Test name
Test status
Simulation time 4429555706 ps
CPU time 18.95 seconds
Started Mar 26 12:22:39 PM PDT 24
Finished Mar 26 12:22:58 PM PDT 24
Peak memory 201800 kb
Host smart-0677686c-b285-4bc5-893c-1669293fbe00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333875362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1333875362
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2133966071
Short name T71
Test name
Test status
Simulation time 329178904 ps
CPU time 2.95 seconds
Started Mar 26 12:23:57 PM PDT 24
Finished Mar 26 12:24:00 PM PDT 24
Peak memory 201868 kb
Host smart-e1ad00f4-704e-4a65-8842-eab4790c3481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133966071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2133966071
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1936328405
Short name T61
Test name
Test status
Simulation time 4789363092 ps
CPU time 4.35 seconds
Started Mar 26 12:25:24 PM PDT 24
Finished Mar 26 12:25:29 PM PDT 24
Peak memory 200904 kb
Host smart-e9109411-cdaf-41fa-a37d-2e67a8205727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936328405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1936328405
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2033577309
Short name T72
Test name
Test status
Simulation time 534387257 ps
CPU time 2.26 seconds
Started Mar 26 12:22:40 PM PDT 24
Finished Mar 26 12:22:42 PM PDT 24
Peak memory 201748 kb
Host smart-b97b42e2-b4ef-4b13-847d-5ae182c497cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033577309 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2033577309
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3001440009
Short name T919
Test name
Test status
Simulation time 553040507 ps
CPU time 2.09 seconds
Started Mar 26 12:24:35 PM PDT 24
Finished Mar 26 12:24:37 PM PDT 24
Peak memory 201560 kb
Host smart-6a5faae6-b6ce-40bb-a9e6-c2efcf467db7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001440009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3001440009
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4249396709
Short name T864
Test name
Test status
Simulation time 323727410 ps
CPU time 1.44 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 199636 kb
Host smart-501eacea-0ed2-46b5-83b9-4a05c2b71f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249396709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4249396709
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2842604033
Short name T842
Test name
Test status
Simulation time 2165830917 ps
CPU time 8.29 seconds
Started Mar 26 12:25:46 PM PDT 24
Finished Mar 26 12:25:55 PM PDT 24
Peak memory 201624 kb
Host smart-6def02b2-8324-44e7-9396-9ac2c763ed1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842604033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2842604033
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3382033562
Short name T896
Test name
Test status
Simulation time 395483297 ps
CPU time 2.36 seconds
Started Mar 26 12:25:21 PM PDT 24
Finished Mar 26 12:25:24 PM PDT 24
Peak memory 199460 kb
Host smart-2e37deac-fb70-47cd-ab98-72a2a9bb6599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382033562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3382033562
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3200855994
Short name T60
Test name
Test status
Simulation time 4204187246 ps
CPU time 11.16 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:50 PM PDT 24
Peak memory 201688 kb
Host smart-82c22a74-4520-47a1-b2d9-3469eed29f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200855994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3200855994
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3207751511
Short name T468
Test name
Test status
Simulation time 515945067 ps
CPU time 0.85 seconds
Started Mar 26 12:27:42 PM PDT 24
Finished Mar 26 12:27:43 PM PDT 24
Peak memory 201140 kb
Host smart-2590e0ea-f7a6-4a85-b768-14e6ffa63673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207751511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3207751511
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3463340498
Short name T247
Test name
Test status
Simulation time 230000670948 ps
CPU time 117.99 seconds
Started Mar 26 12:25:48 PM PDT 24
Finished Mar 26 12:27:46 PM PDT 24
Peak memory 202068 kb
Host smart-d822d757-a9c6-4479-8939-3737114b2c82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463340498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3463340498
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2790657821
Short name T206
Test name
Test status
Simulation time 358284328609 ps
CPU time 223.34 seconds
Started Mar 26 12:25:47 PM PDT 24
Finished Mar 26 12:29:30 PM PDT 24
Peak memory 201820 kb
Host smart-e763131b-4889-44cf-9805-7e791769176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790657821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2790657821
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.474612581
Short name T288
Test name
Test status
Simulation time 334146295523 ps
CPU time 793.06 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:39:22 PM PDT 24
Peak memory 201840 kb
Host smart-e2ff8a4f-6a4c-4b37-a5d2-4e9121f1bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474612581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.474612581
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.470109330
Short name T569
Test name
Test status
Simulation time 501326143165 ps
CPU time 1118.1 seconds
Started Mar 26 12:25:44 PM PDT 24
Finished Mar 26 12:44:22 PM PDT 24
Peak memory 201796 kb
Host smart-b392bb3f-07ff-4036-8468-e814c77acace
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=470109330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.470109330
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2625305456
Short name T760
Test name
Test status
Simulation time 163565973029 ps
CPU time 97.29 seconds
Started Mar 26 12:25:47 PM PDT 24
Finished Mar 26 12:27:25 PM PDT 24
Peak memory 201844 kb
Host smart-706dd63f-f5b6-4143-8c9e-9176e1eff6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625305456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2625305456
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.412675627
Short name T608
Test name
Test status
Simulation time 323832943978 ps
CPU time 48.25 seconds
Started Mar 26 12:26:12 PM PDT 24
Finished Mar 26 12:27:00 PM PDT 24
Peak memory 201680 kb
Host smart-ab5609b3-bbbb-4583-8ec6-dc92d9a53b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412675627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.412675627
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3216927896
Short name T346
Test name
Test status
Simulation time 532397031644 ps
CPU time 301.65 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:31:12 PM PDT 24
Peak memory 201936 kb
Host smart-579bc874-0046-4150-aa0b-dc61db83c2df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216927896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3216927896
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2955944922
Short name T787
Test name
Test status
Simulation time 390145815229 ps
CPU time 128.62 seconds
Started Mar 26 12:26:47 PM PDT 24
Finished Mar 26 12:28:56 PM PDT 24
Peak memory 201660 kb
Host smart-f9fe2ef3-04e5-40c7-b818-6fd478ec55a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955944922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2955944922
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4058340589
Short name T193
Test name
Test status
Simulation time 42305104617 ps
CPU time 26.08 seconds
Started Mar 26 12:25:59 PM PDT 24
Finished Mar 26 12:26:25 PM PDT 24
Peak memory 201532 kb
Host smart-157ae505-dc68-443b-801b-aa2dc01d8a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058340589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4058340589
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3948879613
Short name T479
Test name
Test status
Simulation time 5247460599 ps
CPU time 3.37 seconds
Started Mar 26 12:25:59 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 201532 kb
Host smart-4986fb43-194f-4aa7-83fa-7c777e15c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948879613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3948879613
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.79475166
Short name T84
Test name
Test status
Simulation time 7928625634 ps
CPU time 7.5 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 218036 kb
Host smart-70710f21-4cc4-4a24-aff4-b3facdb5b895
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79475166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.79475166
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4129451440
Short name T688
Test name
Test status
Simulation time 5633225263 ps
CPU time 7.2 seconds
Started Mar 26 12:26:10 PM PDT 24
Finished Mar 26 12:26:17 PM PDT 24
Peak memory 201540 kb
Host smart-93b17f23-fc8e-438a-8fc1-2c3cec846518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129451440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4129451440
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1039408172
Short name T316
Test name
Test status
Simulation time 342732490230 ps
CPU time 56.98 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:26:52 PM PDT 24
Peak memory 201776 kb
Host smart-ba6c8c41-1484-41b8-93fe-95f1bd9062ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039408172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1039408172
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3321486733
Short name T19
Test name
Test status
Simulation time 5112084875 ps
CPU time 15.22 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:26:09 PM PDT 24
Peak memory 210216 kb
Host smart-b0d5ee77-c4d6-4317-afb7-f25ac0e8680d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321486733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3321486733
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1188811843
Short name T603
Test name
Test status
Simulation time 432211779 ps
CPU time 0.72 seconds
Started Mar 26 12:25:56 PM PDT 24
Finished Mar 26 12:25:57 PM PDT 24
Peak memory 201764 kb
Host smart-04af96a0-72ef-4b1c-a7a1-3b4ce4bc360a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188811843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1188811843
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2838624613
Short name T281
Test name
Test status
Simulation time 194383241395 ps
CPU time 63.8 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:26:58 PM PDT 24
Peak memory 202148 kb
Host smart-285a0883-ab67-4d59-98af-3405924aef10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838624613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2838624613
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3332239205
Short name T539
Test name
Test status
Simulation time 162562122582 ps
CPU time 386.69 seconds
Started Mar 26 12:25:58 PM PDT 24
Finished Mar 26 12:32:25 PM PDT 24
Peak memory 201720 kb
Host smart-ffdcf37f-2099-4c31-a00d-8eb13d21dc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332239205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3332239205
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1013895021
Short name T630
Test name
Test status
Simulation time 165753755373 ps
CPU time 99.96 seconds
Started Mar 26 12:26:34 PM PDT 24
Finished Mar 26 12:28:14 PM PDT 24
Peak memory 201684 kb
Host smart-37639f34-8ca1-4ed4-b475-e72246d49c1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013895021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1013895021
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.455169816
Short name T333
Test name
Test status
Simulation time 164424170865 ps
CPU time 91.52 seconds
Started Mar 26 12:27:02 PM PDT 24
Finished Mar 26 12:28:33 PM PDT 24
Peak memory 201736 kb
Host smart-a147556e-f1a7-4e58-9137-a745d71fd176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455169816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.455169816
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3403269970
Short name T565
Test name
Test status
Simulation time 164790581814 ps
CPU time 94.46 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:27:29 PM PDT 24
Peak memory 201680 kb
Host smart-377ccf59-1c43-4808-a767-2e2cceb80153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403269970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3403269970
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.4157886997
Short name T233
Test name
Test status
Simulation time 98379201822 ps
CPU time 332.54 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:32:10 PM PDT 24
Peak memory 202092 kb
Host smart-5d01f050-2533-48b2-8e97-b63fb904d7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157886997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.4157886997
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2573195177
Short name T621
Test name
Test status
Simulation time 45928190049 ps
CPU time 53.33 seconds
Started Mar 26 12:25:58 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 201424 kb
Host smart-416e4dcb-d769-4ca7-bf1e-26869b7c7658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573195177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2573195177
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1743558887
Short name T500
Test name
Test status
Simulation time 3127190944 ps
CPU time 7.24 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:26:01 PM PDT 24
Peak memory 201892 kb
Host smart-e0ebe97a-3223-47f9-b01a-93fc76b55491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743558887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1743558887
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1298395292
Short name T83
Test name
Test status
Simulation time 4283915304 ps
CPU time 7.48 seconds
Started Mar 26 12:25:54 PM PDT 24
Finished Mar 26 12:26:02 PM PDT 24
Peak memory 217672 kb
Host smart-b1ed5848-0a5f-4b12-b961-a8b003f92add
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298395292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1298395292
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1375844818
Short name T155
Test name
Test status
Simulation time 5584860112 ps
CPU time 7.66 seconds
Started Mar 26 12:25:59 PM PDT 24
Finished Mar 26 12:26:07 PM PDT 24
Peak memory 201528 kb
Host smart-329b08b8-eea6-4add-b6b5-74f4ff1017f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375844818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1375844818
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3047578498
Short name T73
Test name
Test status
Simulation time 184338066370 ps
CPU time 401.61 seconds
Started Mar 26 12:25:55 PM PDT 24
Finished Mar 26 12:32:37 PM PDT 24
Peak memory 202048 kb
Host smart-589699ec-9516-49e6-9ee6-b48c17103242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047578498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3047578498
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1346776930
Short name T650
Test name
Test status
Simulation time 367165438 ps
CPU time 0.88 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:26:41 PM PDT 24
Peak memory 201408 kb
Host smart-6746b996-f173-4a60-9cf3-0233590ff44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346776930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1346776930
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4058565251
Short name T351
Test name
Test status
Simulation time 346177708921 ps
CPU time 794.11 seconds
Started Mar 26 12:26:42 PM PDT 24
Finished Mar 26 12:39:56 PM PDT 24
Peak memory 201792 kb
Host smart-bf126c20-1717-4e52-be37-e0fb99d01050
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058565251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4058565251
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1874363083
Short name T312
Test name
Test status
Simulation time 504527844623 ps
CPU time 1187.16 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:48:04 PM PDT 24
Peak memory 201740 kb
Host smart-fc495aa3-aaf5-446a-acdf-3be5a051459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874363083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1874363083
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4292542922
Short name T339
Test name
Test status
Simulation time 165157660728 ps
CPU time 89.2 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:28:15 PM PDT 24
Peak memory 201700 kb
Host smart-82aa694a-7c8f-4761-a5c5-49a2e3c4e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292542922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4292542922
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.750816334
Short name T111
Test name
Test status
Simulation time 498479662632 ps
CPU time 1154.46 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:47:28 PM PDT 24
Peak memory 201704 kb
Host smart-9cba6b6e-5bd1-4bff-92b8-d403ca060ff8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=750816334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.750816334
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3863499100
Short name T613
Test name
Test status
Simulation time 170005725329 ps
CPU time 82.46 seconds
Started Mar 26 12:26:36 PM PDT 24
Finished Mar 26 12:27:59 PM PDT 24
Peak memory 201820 kb
Host smart-cc59af1a-7a04-47f5-b33a-c42629c2c8bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863499100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3863499100
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.584329736
Short name T464
Test name
Test status
Simulation time 193488933486 ps
CPU time 102.25 seconds
Started Mar 26 12:26:36 PM PDT 24
Finished Mar 26 12:28:18 PM PDT 24
Peak memory 201732 kb
Host smart-f60f6919-dd80-4301-83eb-372e01c41f9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584329736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.584329736
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.327714288
Short name T397
Test name
Test status
Simulation time 34965962610 ps
CPU time 42.76 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:27:16 PM PDT 24
Peak memory 201560 kb
Host smart-a386bbde-157d-4094-beb1-834592977bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327714288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.327714288
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2613329091
Short name T441
Test name
Test status
Simulation time 4890487056 ps
CPU time 11.3 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:32 PM PDT 24
Peak memory 201584 kb
Host smart-d1a4d92f-8590-4b89-8ef4-e462ff10f139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613329091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2613329091
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2838048087
Short name T547
Test name
Test status
Simulation time 5683383136 ps
CPU time 4.08 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 201524 kb
Host smart-d4f00577-775c-47bd-971f-608f225ce151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838048087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2838048087
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.949409409
Short name T239
Test name
Test status
Simulation time 496130233135 ps
CPU time 950.42 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:42:34 PM PDT 24
Peak memory 202064 kb
Host smart-79d96ebb-4d24-4f4f-a16f-02c646a684f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949409409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
949409409
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3140032098
Short name T47
Test name
Test status
Simulation time 212015703653 ps
CPU time 153.32 seconds
Started Mar 26 12:27:16 PM PDT 24
Finished Mar 26 12:29:50 PM PDT 24
Peak memory 210340 kb
Host smart-f2195608-0aa1-49a1-a9fd-04be3353caac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140032098 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3140032098
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.102917837
Short name T560
Test name
Test status
Simulation time 457705550 ps
CPU time 1.13 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:27:14 PM PDT 24
Peak memory 201428 kb
Host smart-88067798-7c67-4f64-ba07-bbc220c7cb5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102917837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.102917837
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1624939440
Short name T184
Test name
Test status
Simulation time 327336903596 ps
CPU time 123.78 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:29:01 PM PDT 24
Peak memory 201740 kb
Host smart-3ad710d0-5a58-41f6-948e-6ef1d9606e58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624939440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1624939440
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3465853820
Short name T290
Test name
Test status
Simulation time 164088286683 ps
CPU time 381.39 seconds
Started Mar 26 12:27:11 PM PDT 24
Finished Mar 26 12:33:32 PM PDT 24
Peak memory 201784 kb
Host smart-881f2d5c-54d5-486c-bec0-62cf39d5ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465853820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3465853820
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2729775785
Short name T498
Test name
Test status
Simulation time 328135579067 ps
CPU time 704.81 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:38:24 PM PDT 24
Peak memory 201688 kb
Host smart-dbc20a0c-893e-4cf7-b2a0-abc3e5f87e80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729775785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2729775785
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3031404374
Short name T201
Test name
Test status
Simulation time 325374762436 ps
CPU time 67.95 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:27:48 PM PDT 24
Peak memory 201704 kb
Host smart-dc7d6c73-e478-4ee9-821d-9b60cecec7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031404374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3031404374
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1899196090
Short name T574
Test name
Test status
Simulation time 160791735466 ps
CPU time 102.26 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 201716 kb
Host smart-5f896ba1-92ac-41ff-aae7-a9be4ff3778d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899196090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1899196090
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2353294917
Short name T293
Test name
Test status
Simulation time 540179249977 ps
CPU time 163.14 seconds
Started Mar 26 12:26:58 PM PDT 24
Finished Mar 26 12:29:41 PM PDT 24
Peak memory 201816 kb
Host smart-e592210e-6c4f-4f75-a8bf-aee660b9f79e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353294917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2353294917
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2449719690
Short name T447
Test name
Test status
Simulation time 193674617300 ps
CPU time 70.91 seconds
Started Mar 26 12:27:35 PM PDT 24
Finished Mar 26 12:28:46 PM PDT 24
Peak memory 201732 kb
Host smart-208310c2-e40a-4d32-960b-1f78e0d6efb5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449719690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2449719690
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3407005526
Short name T54
Test name
Test status
Simulation time 67477510682 ps
CPU time 227.95 seconds
Started Mar 26 12:27:50 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 202012 kb
Host smart-3742d715-eebe-4873-b001-5d52ceede132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407005526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3407005526
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3574120990
Short name T434
Test name
Test status
Simulation time 32196048895 ps
CPU time 20.17 seconds
Started Mar 26 12:26:58 PM PDT 24
Finished Mar 26 12:27:18 PM PDT 24
Peak memory 201528 kb
Host smart-6e70f865-35d8-4c0e-a623-9abc7bc4d06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574120990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3574120990
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2005101348
Short name T667
Test name
Test status
Simulation time 3206149886 ps
CPU time 1.18 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:28:11 PM PDT 24
Peak memory 201556 kb
Host smart-8e25bad7-751d-4e39-ad2a-1b3dbf148223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005101348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2005101348
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1863338646
Short name T99
Test name
Test status
Simulation time 6176636583 ps
CPU time 8.2 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 201528 kb
Host smart-5e95dde3-f33f-4954-b1bd-fc31df3af908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863338646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1863338646
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3802656424
Short name T769
Test name
Test status
Simulation time 42323763115 ps
CPU time 77.24 seconds
Started Mar 26 12:27:27 PM PDT 24
Finished Mar 26 12:28:44 PM PDT 24
Peak memory 201532 kb
Host smart-84119e12-d87e-4059-8770-5c01a4671fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802656424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3802656424
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3809760866
Short name T639
Test name
Test status
Simulation time 52941189430 ps
CPU time 156.78 seconds
Started Mar 26 12:26:36 PM PDT 24
Finished Mar 26 12:29:13 PM PDT 24
Peak memory 218584 kb
Host smart-a82b5358-172a-4d03-b5f4-9e12bbe8e949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809760866 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3809760866
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2886475785
Short name T509
Test name
Test status
Simulation time 643064932 ps
CPU time 0.67 seconds
Started Mar 26 12:26:58 PM PDT 24
Finished Mar 26 12:26:59 PM PDT 24
Peak memory 201424 kb
Host smart-5e14601b-a19e-4eb6-90fb-8d91ae4979b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886475785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2886475785
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3103408006
Short name T758
Test name
Test status
Simulation time 237797494275 ps
CPU time 613.25 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:36:53 PM PDT 24
Peak memory 201800 kb
Host smart-894a4141-e2e8-40a2-9d43-f8d0b2ad1531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103408006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3103408006
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1504716814
Short name T481
Test name
Test status
Simulation time 325140598727 ps
CPU time 811.85 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:41:47 PM PDT 24
Peak memory 201764 kb
Host smart-caef4e8c-17bc-47de-9635-13730b91b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504716814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1504716814
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2277955176
Short name T420
Test name
Test status
Simulation time 166706854848 ps
CPU time 24.9 seconds
Started Mar 26 12:27:26 PM PDT 24
Finished Mar 26 12:27:51 PM PDT 24
Peak memory 201704 kb
Host smart-2ca9fbe6-e07c-49a0-866d-00c1abae541d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277955176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2277955176
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.208766560
Short name T435
Test name
Test status
Simulation time 169228916838 ps
CPU time 22.3 seconds
Started Mar 26 12:27:39 PM PDT 24
Finished Mar 26 12:28:02 PM PDT 24
Peak memory 201724 kb
Host smart-f6e0c6de-b792-4233-868f-37c03b5dd47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208766560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.208766560
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2105949053
Short name T450
Test name
Test status
Simulation time 333459202923 ps
CPU time 186.46 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:29:46 PM PDT 24
Peak memory 201688 kb
Host smart-3c38ed22-df1c-48ba-bb9e-bfcc474b0a8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105949053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2105949053
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2640905417
Short name T583
Test name
Test status
Simulation time 169247895907 ps
CPU time 369.65 seconds
Started Mar 26 12:27:24 PM PDT 24
Finished Mar 26 12:33:34 PM PDT 24
Peak memory 201804 kb
Host smart-2a432d6c-01e2-4386-97cd-1ed9e68a5ac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640905417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2640905417
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1030570394
Short name T545
Test name
Test status
Simulation time 396818660799 ps
CPU time 223.51 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:30:25 PM PDT 24
Peak memory 201820 kb
Host smart-ec4a75e3-e76d-4015-9118-55665d545c04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030570394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1030570394
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1041494188
Short name T151
Test name
Test status
Simulation time 92525101800 ps
CPU time 344.01 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:34:00 PM PDT 24
Peak memory 202060 kb
Host smart-2b1616a6-26de-4bd4-bb5e-2eaf93235608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041494188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1041494188
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3531544485
Short name T666
Test name
Test status
Simulation time 29243460100 ps
CPU time 18.48 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:58 PM PDT 24
Peak memory 201536 kb
Host smart-8249e30d-aa7f-48f6-a5d5-b083f22e2166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531544485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3531544485
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2342792147
Short name T406
Test name
Test status
Simulation time 4598203884 ps
CPU time 11.24 seconds
Started Mar 26 12:26:51 PM PDT 24
Finished Mar 26 12:27:02 PM PDT 24
Peak memory 201644 kb
Host smart-ce226bc4-bb71-49e0-b581-eb71f7fca79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342792147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2342792147
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4173149006
Short name T403
Test name
Test status
Simulation time 6009912261 ps
CPU time 4.19 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:24 PM PDT 24
Peak memory 201540 kb
Host smart-81d61141-d9bf-44c6-8b8d-5adf285f4814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173149006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4173149006
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2813911858
Short name T644
Test name
Test status
Simulation time 467099039448 ps
CPU time 633.93 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:37:33 PM PDT 24
Peak memory 202024 kb
Host smart-11eaddb7-5fb4-4dfc-b310-62e16e711a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813911858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2813911858
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1357064
Short name T112
Test name
Test status
Simulation time 121999016541 ps
CPU time 30.39 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:28:25 PM PDT 24
Peak memory 210160 kb
Host smart-2a8ae02f-c1a7-470f-b056-a1e87a255467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357064 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1357064
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3341990691
Short name T471
Test name
Test status
Simulation time 465850771 ps
CPU time 0.87 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:26:56 PM PDT 24
Peak memory 201436 kb
Host smart-e6821c05-061f-4205-84d6-4de0f9c1ed48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341990691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3341990691
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.664117072
Short name T692
Test name
Test status
Simulation time 512945502546 ps
CPU time 497.54 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:34:57 PM PDT 24
Peak memory 201740 kb
Host smart-4b814d35-4adf-474b-913c-65af2c7bd49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664117072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.664117072
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1429193412
Short name T554
Test name
Test status
Simulation time 329649855662 ps
CPU time 213.84 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:30:11 PM PDT 24
Peak memory 201552 kb
Host smart-576fcccd-5d9f-4842-9c58-62360fe9709c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429193412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1429193412
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.721963258
Short name T165
Test name
Test status
Simulation time 500068094066 ps
CPU time 233.26 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:30:37 PM PDT 24
Peak memory 201720 kb
Host smart-24f57c95-2566-4fd5-892b-24799c8543d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721963258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.721963258
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2589015139
Short name T746
Test name
Test status
Simulation time 487396690171 ps
CPU time 1106.59 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:45:06 PM PDT 24
Peak memory 201696 kb
Host smart-7b9ec3d2-a43e-431b-982b-f1c1ea3c0735
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589015139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2589015139
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.879029921
Short name T110
Test name
Test status
Simulation time 566973464205 ps
CPU time 641.72 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:37:28 PM PDT 24
Peak memory 201804 kb
Host smart-d7fa770d-cde4-4f01-b1c1-ebb2ff8bce8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879029921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.879029921
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3211066804
Short name T636
Test name
Test status
Simulation time 597239288121 ps
CPU time 240.61 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:32:16 PM PDT 24
Peak memory 201724 kb
Host smart-adfa28d2-7a70-44ec-9f09-8b079ed8a8a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211066804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3211066804
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.847557325
Short name T214
Test name
Test status
Simulation time 101834998524 ps
CPU time 490.75 seconds
Started Mar 26 12:27:23 PM PDT 24
Finished Mar 26 12:35:33 PM PDT 24
Peak memory 202016 kb
Host smart-4080e422-5c1b-40d1-aef8-a6f0963f70b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847557325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.847557325
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3060119335
Short name T427
Test name
Test status
Simulation time 38765214725 ps
CPU time 79.31 seconds
Started Mar 26 12:27:04 PM PDT 24
Finished Mar 26 12:28:24 PM PDT 24
Peak memory 201536 kb
Host smart-c76fbfe4-4ea8-41aa-9181-30b50c0f552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060119335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3060119335
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1498857197
Short name T677
Test name
Test status
Simulation time 3352931185 ps
CPU time 8.61 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:52 PM PDT 24
Peak memory 201536 kb
Host smart-6ba6999f-0e8a-4d08-999e-6ec046fe3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498857197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1498857197
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.949028156
Short name T707
Test name
Test status
Simulation time 6130725730 ps
CPU time 4.23 seconds
Started Mar 26 12:26:39 PM PDT 24
Finished Mar 26 12:26:43 PM PDT 24
Peak memory 201496 kb
Host smart-9ab88930-320b-4c29-b465-384cf01a176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949028156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.949028156
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.978011201
Short name T712
Test name
Test status
Simulation time 169051826359 ps
CPU time 213.04 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:30:33 PM PDT 24
Peak memory 201020 kb
Host smart-dfe74ce8-8a58-45f6-ac11-b7a36c8cb7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978011201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
978011201
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2474088254
Short name T25
Test name
Test status
Simulation time 191670420123 ps
CPU time 400.01 seconds
Started Mar 26 12:27:41 PM PDT 24
Finished Mar 26 12:34:22 PM PDT 24
Peak memory 210396 kb
Host smart-cc40ee71-7562-4e0d-b883-5d6d0abd83d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474088254 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2474088254
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2852385713
Short name T407
Test name
Test status
Simulation time 336092722 ps
CPU time 0.81 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:26:55 PM PDT 24
Peak memory 201764 kb
Host smart-212be919-4c1a-48d7-8822-9e2807b6e179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852385713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2852385713
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.307149431
Short name T189
Test name
Test status
Simulation time 185473963658 ps
CPU time 417.8 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:33:52 PM PDT 24
Peak memory 201732 kb
Host smart-b4dc6975-eeeb-4223-8ce4-9c423cd13468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307149431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.307149431
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3368286689
Short name T222
Test name
Test status
Simulation time 325089747313 ps
CPU time 677.24 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:38:12 PM PDT 24
Peak memory 201720 kb
Host smart-04eec755-6be8-4507-8e93-eb4d777febf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368286689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3368286689
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3105904373
Short name T536
Test name
Test status
Simulation time 167283319377 ps
CPU time 51.21 seconds
Started Mar 26 12:27:04 PM PDT 24
Finished Mar 26 12:27:55 PM PDT 24
Peak memory 201664 kb
Host smart-bcd46e84-0471-4e76-bc96-c8a749f9ee2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105904373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3105904373
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3082562840
Short name T335
Test name
Test status
Simulation time 479536798732 ps
CPU time 1123.82 seconds
Started Mar 26 12:26:46 PM PDT 24
Finished Mar 26 12:45:30 PM PDT 24
Peak memory 201580 kb
Host smart-d78ad55a-367b-4ccb-8bc0-ab3762171650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082562840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3082562840
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1739843119
Short name T88
Test name
Test status
Simulation time 494652170171 ps
CPU time 1188.91 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:46:44 PM PDT 24
Peak memory 201712 kb
Host smart-af6d08a6-23f2-4881-9125-380198075e12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739843119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1739843119
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3223991843
Short name T368
Test name
Test status
Simulation time 180092525420 ps
CPU time 228.29 seconds
Started Mar 26 12:27:05 PM PDT 24
Finished Mar 26 12:30:53 PM PDT 24
Peak memory 201456 kb
Host smart-9b6d942f-d761-4211-b407-bc91bd3c86bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223991843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3223991843
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1707999047
Short name T508
Test name
Test status
Simulation time 577001758110 ps
CPU time 1360.6 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:49:44 PM PDT 24
Peak memory 202124 kb
Host smart-a57906d1-f85a-4355-8ac1-0c1497ddbf55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707999047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1707999047
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3771870790
Short name T739
Test name
Test status
Simulation time 73905032800 ps
CPU time 412.35 seconds
Started Mar 26 12:26:52 PM PDT 24
Finished Mar 26 12:33:45 PM PDT 24
Peak memory 202012 kb
Host smart-ea7f06dd-32a5-4fbf-a063-d0e6f29cbe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771870790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3771870790
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.868278260
Short name T567
Test name
Test status
Simulation time 25647465286 ps
CPU time 56.81 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:27:52 PM PDT 24
Peak memory 201532 kb
Host smart-a4904999-6971-42ea-a217-8b88ff91a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868278260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.868278260
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3501870150
Short name T424
Test name
Test status
Simulation time 4020307227 ps
CPU time 9.39 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 201892 kb
Host smart-07b7f773-dbcc-4347-ae04-e3427bb27440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501870150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3501870150
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3985538146
Short name T577
Test name
Test status
Simulation time 5963601568 ps
CPU time 3.26 seconds
Started Mar 26 12:26:57 PM PDT 24
Finished Mar 26 12:27:00 PM PDT 24
Peak memory 201548 kb
Host smart-f96d6e8d-5214-4915-b4ae-26d7756e2756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985538146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3985538146
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3297846480
Short name T369
Test name
Test status
Simulation time 496719958275 ps
CPU time 316.09 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:32:31 PM PDT 24
Peak memory 201788 kb
Host smart-208f06c4-b289-4b85-8f24-8511872c97e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297846480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3297846480
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.687437946
Short name T39
Test name
Test status
Simulation time 61491561149 ps
CPU time 186.8 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:30:27 PM PDT 24
Peak memory 210392 kb
Host smart-a74890c2-f626-40b0-b50a-3b0b610e6bbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687437946 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.687437946
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2612118609
Short name T512
Test name
Test status
Simulation time 416101197 ps
CPU time 0.98 seconds
Started Mar 26 12:27:01 PM PDT 24
Finished Mar 26 12:27:02 PM PDT 24
Peak memory 201440 kb
Host smart-9491ef70-affa-4200-8228-3e61b541eed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612118609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2612118609
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4248515901
Short name T598
Test name
Test status
Simulation time 162796368163 ps
CPU time 49.9 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:27:43 PM PDT 24
Peak memory 201712 kb
Host smart-fee83454-95bb-4a0d-bccd-a06765ebec29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248515901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4248515901
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.124042865
Short name T773
Test name
Test status
Simulation time 188703730470 ps
CPU time 409.27 seconds
Started Mar 26 12:26:55 PM PDT 24
Finished Mar 26 12:33:44 PM PDT 24
Peak memory 201728 kb
Host smart-17dcbf9c-51cd-43f4-a9bc-1c78f9bb4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124042865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.124042865
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.843470429
Short name T267
Test name
Test status
Simulation time 163684906933 ps
CPU time 118.48 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:30:21 PM PDT 24
Peak memory 201836 kb
Host smart-aa04da8b-dabd-4f75-83d5-4b6eca4f9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843470429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.843470429
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2689099132
Short name T740
Test name
Test status
Simulation time 490635790409 ps
CPU time 1166.04 seconds
Started Mar 26 12:27:01 PM PDT 24
Finished Mar 26 12:46:28 PM PDT 24
Peak memory 201712 kb
Host smart-f82ef81e-605b-437a-a0b8-28db7af1c341
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689099132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2689099132
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2367408590
Short name T717
Test name
Test status
Simulation time 164829835283 ps
CPU time 56.57 seconds
Started Mar 26 12:26:49 PM PDT 24
Finished Mar 26 12:27:46 PM PDT 24
Peak memory 201016 kb
Host smart-02cbaeb3-2054-41d8-83af-d0ea85cff0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367408590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2367408590
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3134342068
Short name T33
Test name
Test status
Simulation time 485374301742 ps
CPU time 105.23 seconds
Started Mar 26 12:26:48 PM PDT 24
Finished Mar 26 12:28:33 PM PDT 24
Peak memory 201800 kb
Host smart-27b4a77f-3d26-4652-9d4c-6bc8e91272bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134342068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3134342068
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3721181367
Short name T742
Test name
Test status
Simulation time 203417216246 ps
CPU time 126.79 seconds
Started Mar 26 12:26:54 PM PDT 24
Finished Mar 26 12:29:01 PM PDT 24
Peak memory 201808 kb
Host smart-5fcb7655-c3b0-4ef5-807e-168417a7f7c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721181367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3721181367
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3252539875
Short name T398
Test name
Test status
Simulation time 104494832894 ps
CPU time 520.54 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:35:37 PM PDT 24
Peak memory 202100 kb
Host smart-06936d7c-0253-4bc8-8094-c98c52991fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252539875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3252539875
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1436674908
Short name T537
Test name
Test status
Simulation time 45821660782 ps
CPU time 98.97 seconds
Started Mar 26 12:27:55 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 201884 kb
Host smart-a4af586d-9f40-4f0f-9092-b90273f6b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436674908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1436674908
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1275485124
Short name T747
Test name
Test status
Simulation time 3850764860 ps
CPU time 9.35 seconds
Started Mar 26 12:26:57 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 201516 kb
Host smart-3db7233a-8032-4dc1-a88a-692503ccf895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275485124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1275485124
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3622175494
Short name T97
Test name
Test status
Simulation time 5787842917 ps
CPU time 14.01 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:27:13 PM PDT 24
Peak memory 201528 kb
Host smart-e05d0871-1500-47a6-8b18-6f6677ab2371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622175494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3622175494
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2895588651
Short name T518
Test name
Test status
Simulation time 230754396295 ps
CPU time 384.48 seconds
Started Mar 26 12:26:57 PM PDT 24
Finished Mar 26 12:33:22 PM PDT 24
Peak memory 211760 kb
Host smart-ee0ab194-53f9-493b-8eeb-f8a000444de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895588651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2895588651
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1760530214
Short name T349
Test name
Test status
Simulation time 2022816360945 ps
CPU time 406.15 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:33:45 PM PDT 24
Peak memory 217844 kb
Host smart-b302f715-324b-4dc2-91c0-45e6175cb02c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760530214 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1760530214
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3187918037
Short name T764
Test name
Test status
Simulation time 404920718 ps
CPU time 0.66 seconds
Started Mar 26 12:27:20 PM PDT 24
Finished Mar 26 12:27:21 PM PDT 24
Peak memory 201404 kb
Host smart-59a7067f-21d3-4ec4-955d-74a2f464cd5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187918037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3187918037
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1855585382
Short name T187
Test name
Test status
Simulation time 487826359167 ps
CPU time 309.63 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:32:13 PM PDT 24
Peak memory 201816 kb
Host smart-3777aaa4-b46a-439c-99e3-e415741f5681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855585382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1855585382
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3759115554
Short name T625
Test name
Test status
Simulation time 490897828457 ps
CPU time 1164.22 seconds
Started Mar 26 12:26:57 PM PDT 24
Finished Mar 26 12:46:21 PM PDT 24
Peak memory 201780 kb
Host smart-b60deab6-28bb-4f68-89db-7e3f1fcb41a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759115554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3759115554
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1115895450
Short name T759
Test name
Test status
Simulation time 325679298534 ps
CPU time 767.01 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:39:46 PM PDT 24
Peak memory 201716 kb
Host smart-176a836c-ac56-4200-b2e5-84c9aee1872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115895450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1115895450
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1766109401
Short name T591
Test name
Test status
Simulation time 488857276626 ps
CPU time 285.67 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:32:56 PM PDT 24
Peak memory 201732 kb
Host smart-134b8e85-4766-45c2-9ef1-ae08a2568cbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766109401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1766109401
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1204713070
Short name T784
Test name
Test status
Simulation time 392809375203 ps
CPU time 906.23 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:42:20 PM PDT 24
Peak memory 201736 kb
Host smart-83e389f9-44d8-4881-8e77-f4a1eeeb3c2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204713070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1204713070
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2778198417
Short name T228
Test name
Test status
Simulation time 140776006291 ps
CPU time 487.61 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:35:21 PM PDT 24
Peak memory 202164 kb
Host smart-c24e7441-9d97-4b96-83b8-658c4248698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778198417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2778198417
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.719764597
Short name T645
Test name
Test status
Simulation time 36617014969 ps
CPU time 23.05 seconds
Started Mar 26 12:26:57 PM PDT 24
Finished Mar 26 12:27:20 PM PDT 24
Peak memory 201628 kb
Host smart-61d033ea-832b-4501-81ce-4be1723ac6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719764597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.719764597
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4294165886
Short name T423
Test name
Test status
Simulation time 3111938421 ps
CPU time 7.69 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 201612 kb
Host smart-f14ca14c-bde5-4521-bdf0-b75879f6a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294165886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4294165886
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2258061818
Short name T106
Test name
Test status
Simulation time 5671986200 ps
CPU time 6.59 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:27:16 PM PDT 24
Peak memory 201880 kb
Host smart-b994db20-161d-47a5-b73c-ee525858bda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258061818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2258061818
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1195689202
Short name T693
Test name
Test status
Simulation time 204896761179 ps
CPU time 114.19 seconds
Started Mar 26 12:27:12 PM PDT 24
Finished Mar 26 12:29:07 PM PDT 24
Peak memory 200996 kb
Host smart-c886056e-9265-493a-899c-6137ad527f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195689202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1195689202
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.662012652
Short name T796
Test name
Test status
Simulation time 310326503 ps
CPU time 1.25 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:16 PM PDT 24
Peak memory 201448 kb
Host smart-5f64ca6a-2d30-40b3-886a-211b07baee07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662012652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.662012652
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3510937287
Short name T311
Test name
Test status
Simulation time 382618576821 ps
CPU time 870.13 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:41:45 PM PDT 24
Peak memory 201740 kb
Host smart-79281f13-9c31-4c43-95dc-381f67e11bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510937287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3510937287
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1700158757
Short name T218
Test name
Test status
Simulation time 321291034413 ps
CPU time 153.93 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:29:44 PM PDT 24
Peak memory 201812 kb
Host smart-5e6b37f9-5233-462b-83ec-a456e4288a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700158757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1700158757
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2370536240
Short name T437
Test name
Test status
Simulation time 164964560106 ps
CPU time 110.43 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:28:54 PM PDT 24
Peak memory 201696 kb
Host smart-da99abf1-82e3-46ab-bdc4-0846adb4b95d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370536240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2370536240
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2650975941
Short name T148
Test name
Test status
Simulation time 492208179153 ps
CPU time 1146.12 seconds
Started Mar 26 12:27:29 PM PDT 24
Finished Mar 26 12:46:35 PM PDT 24
Peak memory 201668 kb
Host smart-5b8c3df9-b5b4-46c6-93b9-f0c91ece48bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650975941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2650975941
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.6327633
Short name T737
Test name
Test status
Simulation time 162590068939 ps
CPU time 382.44 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:33:20 PM PDT 24
Peak memory 201024 kb
Host smart-63a8b832-e9f7-4056-8cb2-a87ef0bb0922
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=6327633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.6327633
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3348798751
Short name T264
Test name
Test status
Simulation time 389414363936 ps
CPU time 894.41 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:42:07 PM PDT 24
Peak memory 201716 kb
Host smart-d6823fd9-04e7-4c71-b111-ae4b132395db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348798751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3348798751
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1144967061
Short name T421
Test name
Test status
Simulation time 599437374686 ps
CPU time 350.09 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:34:10 PM PDT 24
Peak memory 201768 kb
Host smart-dfe381f2-751a-46c8-8c54-5d1cdf25f985
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144967061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1144967061
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.486030788
Short name T519
Test name
Test status
Simulation time 91117590941 ps
CPU time 462.49 seconds
Started Mar 26 12:27:05 PM PDT 24
Finished Mar 26 12:34:48 PM PDT 24
Peak memory 202088 kb
Host smart-1a87fbfa-117a-490b-af76-5f9336d83f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486030788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.486030788
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.818906889
Short name T114
Test name
Test status
Simulation time 45267340678 ps
CPU time 24.77 seconds
Started Mar 26 12:27:09 PM PDT 24
Finished Mar 26 12:27:34 PM PDT 24
Peak memory 201668 kb
Host smart-7085e1ad-37b4-4ed2-b605-08c59ce19b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818906889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.818906889
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1701405480
Short name T543
Test name
Test status
Simulation time 5477908745 ps
CPU time 6.89 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:27:04 PM PDT 24
Peak memory 201504 kb
Host smart-25c5c241-def7-4842-bcae-d01d9c0154e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701405480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1701405480
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2247077601
Short name T714
Test name
Test status
Simulation time 5882815306 ps
CPU time 4.59 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:27:01 PM PDT 24
Peak memory 201632 kb
Host smart-266f11c7-6771-44f7-8765-68016ad21652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247077601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2247077601
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.175347749
Short name T271
Test name
Test status
Simulation time 343550453220 ps
CPU time 206.73 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 201796 kb
Host smart-ae437966-acfe-4989-8c42-65e47a51a781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175347749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
175347749
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1758108896
Short name T37
Test name
Test status
Simulation time 13051531574 ps
CPU time 32.15 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:46 PM PDT 24
Peak memory 210368 kb
Host smart-ba4ccdfa-3657-4a88-b5eb-db7c45ad1dff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758108896 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1758108896
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.944518550
Short name T541
Test name
Test status
Simulation time 315944739 ps
CPU time 0.78 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:15 PM PDT 24
Peak memory 201312 kb
Host smart-8d58693a-dc22-4e65-8d8b-427df8612880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944518550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.944518550
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3466273130
Short name T343
Test name
Test status
Simulation time 162156289585 ps
CPU time 201.21 seconds
Started Mar 26 12:27:01 PM PDT 24
Finished Mar 26 12:30:22 PM PDT 24
Peak memory 201936 kb
Host smart-ed5acd12-9a92-41af-9147-99ece41d53a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466273130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3466273130
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.922363377
Short name T325
Test name
Test status
Simulation time 496633024587 ps
CPU time 1211.53 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:48:20 PM PDT 24
Peak memory 201824 kb
Host smart-96da5ceb-a0e9-4e31-8453-2d6fe801bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922363377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.922363377
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.577949398
Short name T458
Test name
Test status
Simulation time 316959473169 ps
CPU time 95.11 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:28:53 PM PDT 24
Peak memory 201668 kb
Host smart-781dc812-5c44-4971-a320-9a7c0956302b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=577949398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.577949398
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1837193501
Short name T245
Test name
Test status
Simulation time 492411704917 ps
CPU time 1120.25 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:46:49 PM PDT 24
Peak memory 201396 kb
Host smart-c833b780-9076-4e66-8d20-7a19a963955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837193501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1837193501
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.688553294
Short name T597
Test name
Test status
Simulation time 485984436348 ps
CPU time 625.98 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:37:30 PM PDT 24
Peak memory 201904 kb
Host smart-60e86883-4d3c-465b-8b88-04eb90de8535
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=688553294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.688553294
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2019205122
Short name T673
Test name
Test status
Simulation time 647702291892 ps
CPU time 353.35 seconds
Started Mar 26 12:27:12 PM PDT 24
Finished Mar 26 12:33:06 PM PDT 24
Peak memory 201800 kb
Host smart-d695f6da-ab12-4ef7-ba01-4286a8cd0896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019205122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2019205122
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4020860083
Short name T436
Test name
Test status
Simulation time 193391075545 ps
CPU time 83.16 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:28:38 PM PDT 24
Peak memory 201796 kb
Host smart-f2ba83f1-e04d-4753-9dea-c0dbbb01e13b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020860083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4020860083
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.833754651
Short name T227
Test name
Test status
Simulation time 124537908438 ps
CPU time 564.03 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:36:37 PM PDT 24
Peak memory 202100 kb
Host smart-3150285b-5b19-477f-a56e-1870f987330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833754651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.833754651
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4276469521
Short name T607
Test name
Test status
Simulation time 23881212528 ps
CPU time 60 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:28:14 PM PDT 24
Peak memory 201540 kb
Host smart-aad55a61-89cf-4058-9083-5721f0858c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276469521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4276469521
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3598929507
Short name T725
Test name
Test status
Simulation time 3491819030 ps
CPU time 3.87 seconds
Started Mar 26 12:28:24 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201572 kb
Host smart-c69e6111-9042-484f-a5b1-d4737f301947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598929507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3598929507
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1615338288
Short name T735
Test name
Test status
Simulation time 6025618304 ps
CPU time 15 seconds
Started Mar 26 12:27:07 PM PDT 24
Finished Mar 26 12:27:22 PM PDT 24
Peak memory 201548 kb
Host smart-522268b1-d50b-4ba3-9359-1e0ce4df2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615338288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1615338288
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3515387115
Short name T322
Test name
Test status
Simulation time 627519819178 ps
CPU time 524.42 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:35:52 PM PDT 24
Peak memory 210244 kb
Host smart-3eb50ae6-6b89-443b-9795-911578c03526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515387115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3515387115
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.67159908
Short name T21
Test name
Test status
Simulation time 64128087245 ps
CPU time 100.95 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:28:47 PM PDT 24
Peak memory 218060 kb
Host smart-73830f87-d3f6-4479-b386-0aea4fb4339a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67159908 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.67159908
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2520730528
Short name T503
Test name
Test status
Simulation time 348839708 ps
CPU time 0.69 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:27:19 PM PDT 24
Peak memory 201404 kb
Host smart-bda0f87f-d8c7-4b66-8e8d-ea190d967fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520730528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2520730528
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1357939376
Short name T745
Test name
Test status
Simulation time 346100029404 ps
CPU time 805.17 seconds
Started Mar 26 12:27:25 PM PDT 24
Finished Mar 26 12:40:51 PM PDT 24
Peak memory 201824 kb
Host smart-7a6e8d7c-647a-4a2e-b3f6-e21118e68956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357939376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1357939376
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2424270094
Short name T141
Test name
Test status
Simulation time 484480237321 ps
CPU time 1044.63 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:45:46 PM PDT 24
Peak memory 201748 kb
Host smart-6addd6b2-cb68-4742-a71d-4f39fd24cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424270094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2424270094
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4155508724
Short name T588
Test name
Test status
Simulation time 327351581742 ps
CPU time 766.75 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:40:05 PM PDT 24
Peak memory 201688 kb
Host smart-adb62cb8-7987-4380-8579-4a2d87929ad9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155508724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4155508724
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2393952873
Short name T763
Test name
Test status
Simulation time 497241757874 ps
CPU time 1246.06 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:48:02 PM PDT 24
Peak memory 201692 kb
Host smart-3239313f-d02b-49d5-ac2c-f56518601821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393952873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2393952873
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3249960032
Short name T766
Test name
Test status
Simulation time 323579872336 ps
CPU time 194.09 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:30:25 PM PDT 24
Peak memory 201680 kb
Host smart-863b8ae2-daf9-416a-9527-63694713f4da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249960032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3249960032
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.257548141
Short name T292
Test name
Test status
Simulation time 383318321624 ps
CPU time 218.64 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:30:47 PM PDT 24
Peak memory 201816 kb
Host smart-2c43bd62-c022-4ef4-a924-52e4be65d53c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257548141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.257548141
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.274283541
Short name T443
Test name
Test status
Simulation time 405173744639 ps
CPU time 961.2 seconds
Started Mar 26 12:27:01 PM PDT 24
Finished Mar 26 12:43:03 PM PDT 24
Peak memory 201832 kb
Host smart-dfb89053-8b43-4258-a74c-b7873effa96b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274283541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.274283541
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3995107667
Short name T776
Test name
Test status
Simulation time 24000214286 ps
CPU time 12.38 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:27:20 PM PDT 24
Peak memory 201512 kb
Host smart-7e0e84b6-6ca1-4285-8c83-90fd772a5091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995107667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3995107667
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1164225509
Short name T709
Test name
Test status
Simulation time 4346708385 ps
CPU time 5.71 seconds
Started Mar 26 12:27:11 PM PDT 24
Finished Mar 26 12:27:16 PM PDT 24
Peak memory 201548 kb
Host smart-39f66fb7-47ea-41a0-b6fe-2396e617560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164225509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1164225509
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3567585969
Short name T439
Test name
Test status
Simulation time 5824165308 ps
CPU time 4.06 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:27:19 PM PDT 24
Peak memory 201512 kb
Host smart-4d083cc5-7ef8-461f-9435-e9866061e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567585969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3567585969
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.218876324
Short name T558
Test name
Test status
Simulation time 169770905526 ps
CPU time 378.31 seconds
Started Mar 26 12:27:02 PM PDT 24
Finished Mar 26 12:33:21 PM PDT 24
Peak memory 201720 kb
Host smart-5e82900e-f6fb-4d10-b31d-52b71244a368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218876324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
218876324
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3097880019
Short name T92
Test name
Test status
Simulation time 115836447888 ps
CPU time 179.45 seconds
Started Mar 26 12:26:58 PM PDT 24
Finished Mar 26 12:29:58 PM PDT 24
Peak memory 210288 kb
Host smart-bff01920-1d92-4153-9614-6d3ea90cb846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097880019 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3097880019
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1750615679
Short name T599
Test name
Test status
Simulation time 394979751 ps
CPU time 1.05 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:26:13 PM PDT 24
Peak memory 201432 kb
Host smart-f77d5dca-2fd8-42c3-a9e2-d2a6faf2d2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750615679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1750615679
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1632962128
Short name T347
Test name
Test status
Simulation time 328484552900 ps
CPU time 200.74 seconds
Started Mar 26 12:26:06 PM PDT 24
Finished Mar 26 12:29:27 PM PDT 24
Peak memory 200940 kb
Host smart-38a8ca86-1e83-41c9-ba1f-ba7d6ac7e786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632962128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1632962128
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3805888311
Short name T338
Test name
Test status
Simulation time 479961995079 ps
CPU time 579.75 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:38:02 PM PDT 24
Peak memory 201824 kb
Host smart-ac8cd731-5ccf-4afd-bc7b-047e92a45c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805888311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3805888311
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3808343458
Short name T753
Test name
Test status
Simulation time 488953092317 ps
CPU time 686.35 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:37:36 PM PDT 24
Peak memory 201736 kb
Host smart-34822afe-2ac9-474c-a66c-f55645fdddd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808343458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3808343458
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3611199728
Short name T738
Test name
Test status
Simulation time 327488388920 ps
CPU time 379.83 seconds
Started Mar 26 12:26:06 PM PDT 24
Finished Mar 26 12:32:26 PM PDT 24
Peak memory 201684 kb
Host smart-e856f229-68a2-49fb-b975-cd445ed61a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611199728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3611199728
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2978657415
Short name T115
Test name
Test status
Simulation time 325786659818 ps
CPU time 712.59 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:38:04 PM PDT 24
Peak memory 201680 kb
Host smart-d1057559-68c4-4399-bdeb-19915f3c6147
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978657415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2978657415
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3537524923
Short name T715
Test name
Test status
Simulation time 358944164710 ps
CPU time 155.79 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:29:33 PM PDT 24
Peak memory 201804 kb
Host smart-ff73a484-213e-49f8-aa93-e99b8b15db09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537524923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3537524923
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1728981667
Short name T384
Test name
Test status
Simulation time 203066327410 ps
CPU time 456.5 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:33:44 PM PDT 24
Peak memory 201512 kb
Host smart-7bb33562-6008-480a-a5b9-0660b10c9af5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728981667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1728981667
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2966985274
Short name T801
Test name
Test status
Simulation time 33644481150 ps
CPU time 20.62 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:26:32 PM PDT 24
Peak memory 201524 kb
Host smart-92c6bc8a-888f-4eb5-92bc-709859dd45ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966985274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2966985274
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3025266694
Short name T563
Test name
Test status
Simulation time 5308315687 ps
CPU time 3.92 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:26:13 PM PDT 24
Peak memory 201512 kb
Host smart-74c03ef2-e8d5-4d69-a12e-e5d23de49f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025266694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3025266694
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1920503740
Short name T211
Test name
Test status
Simulation time 6051927616 ps
CPU time 1.85 seconds
Started Mar 26 12:26:21 PM PDT 24
Finished Mar 26 12:26:23 PM PDT 24
Peak memory 201484 kb
Host smart-7cbbeaa4-f48b-46aa-9add-5b1dbb03bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920503740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1920503740
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.511843536
Short name T24
Test name
Test status
Simulation time 128366855119 ps
CPU time 73.96 seconds
Started Mar 26 12:26:04 PM PDT 24
Finished Mar 26 12:27:18 PM PDT 24
Peak memory 210048 kb
Host smart-851b3c5b-f9c0-4580-9cc1-4283192c7074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511843536 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.511843536
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1778612589
Short name T487
Test name
Test status
Simulation time 357733212 ps
CPU time 1.4 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:15 PM PDT 24
Peak memory 201484 kb
Host smart-d2a27293-019f-4aab-a181-a9e7d16449c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778612589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1778612589
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.430716380
Short name T402
Test name
Test status
Simulation time 165902789939 ps
CPU time 404.17 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:34:02 PM PDT 24
Peak memory 201664 kb
Host smart-e4d158a5-5f6a-4529-8cbe-8f4dc3033500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=430716380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.430716380
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3990815785
Short name T215
Test name
Test status
Simulation time 329924816065 ps
CPU time 173.08 seconds
Started Mar 26 12:27:18 PM PDT 24
Finished Mar 26 12:30:11 PM PDT 24
Peak memory 201824 kb
Host smart-a838ac4e-f42a-42fc-a675-4520015196f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990815785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3990815785
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.4031714465
Short name T454
Test name
Test status
Simulation time 161618267502 ps
CPU time 94.96 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:28:46 PM PDT 24
Peak memory 201692 kb
Host smart-c93b5bf9-dfc2-4a53-8e86-92c372b7df33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031714465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.4031714465
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2581359165
Short name T300
Test name
Test status
Simulation time 370904082882 ps
CPU time 236.05 seconds
Started Mar 26 12:27:17 PM PDT 24
Finished Mar 26 12:31:14 PM PDT 24
Peak memory 201704 kb
Host smart-73a70d8d-0218-4563-bc8e-ee56583e03e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581359165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2581359165
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4099566060
Short name T774
Test name
Test status
Simulation time 391779349284 ps
CPU time 913.66 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:43:22 PM PDT 24
Peak memory 201812 kb
Host smart-af59f7fb-a2ae-46ce-8799-77de90116fc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099566060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4099566060
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2119662455
Short name T232
Test name
Test status
Simulation time 120060123859 ps
CPU time 451.05 seconds
Started Mar 26 12:28:35 PM PDT 24
Finished Mar 26 12:36:07 PM PDT 24
Peak memory 201916 kb
Host smart-f90b86c1-971b-414c-bd61-5c3619257bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119662455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2119662455
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3165463844
Short name T797
Test name
Test status
Simulation time 34695495932 ps
CPU time 72.79 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:28:26 PM PDT 24
Peak memory 201536 kb
Host smart-963cefdd-02a1-490c-b659-e7ba5f441a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165463844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3165463844
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1202856525
Short name T422
Test name
Test status
Simulation time 5261839821 ps
CPU time 4.15 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:28:40 PM PDT 24
Peak memory 201340 kb
Host smart-ffb6dd34-685c-4767-8fff-63f372be425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202856525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1202856525
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1145701594
Short name T559
Test name
Test status
Simulation time 5961855657 ps
CPU time 14.14 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:28:23 PM PDT 24
Peak memory 201552 kb
Host smart-24bc123a-d5de-4973-b3f5-7b67546589c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145701594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1145701594
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1740006692
Short name T710
Test name
Test status
Simulation time 431058571063 ps
CPU time 1304.19 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:48:44 PM PDT 24
Peak memory 218844 kb
Host smart-2dae691e-4462-4756-ab03-1371726ffbf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740006692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1740006692
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1300206467
Short name T699
Test name
Test status
Simulation time 240593298865 ps
CPU time 218.03 seconds
Started Mar 26 12:27:10 PM PDT 24
Finished Mar 26 12:30:48 PM PDT 24
Peak memory 210368 kb
Host smart-4c50a0fb-17f2-4c87-a123-eb22954605c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300206467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1300206467
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2908736850
Short name T542
Test name
Test status
Simulation time 413111004 ps
CPU time 0.65 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:17 PM PDT 24
Peak memory 201380 kb
Host smart-39e3cfde-e83d-4b78-8947-3d0aada5995e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908736850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2908736850
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.133568038
Short name T624
Test name
Test status
Simulation time 159309441499 ps
CPU time 95.77 seconds
Started Mar 26 12:28:07 PM PDT 24
Finished Mar 26 12:29:43 PM PDT 24
Peak memory 201728 kb
Host smart-53703e68-c91c-4281-a3c3-cb67d4fd29e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133568038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.133568038
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4126840178
Short name T356
Test name
Test status
Simulation time 165961483962 ps
CPU time 25.22 seconds
Started Mar 26 12:27:58 PM PDT 24
Finished Mar 26 12:28:24 PM PDT 24
Peak memory 201724 kb
Host smart-4b55e11d-3ed0-4205-87db-d2134a16f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126840178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4126840178
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2921272039
Short name T432
Test name
Test status
Simulation time 161360875304 ps
CPU time 383.98 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:33:38 PM PDT 24
Peak memory 201704 kb
Host smart-e754f91e-8a85-4871-a8b1-8ac7afbdbf84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921272039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2921272039
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3700768070
Short name T612
Test name
Test status
Simulation time 165718008244 ps
CPU time 89.76 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:29:46 PM PDT 24
Peak memory 201696 kb
Host smart-f70e3acb-68a6-493b-8f5d-bf0a3a4b7a03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700768070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3700768070
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1221862037
Short name T243
Test name
Test status
Simulation time 357693669387 ps
CPU time 400.99 seconds
Started Mar 26 12:27:11 PM PDT 24
Finished Mar 26 12:33:52 PM PDT 24
Peak memory 201764 kb
Host smart-6f719bba-dd38-495f-9420-d9c130f309a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221862037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1221862037
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1917286841
Short name T640
Test name
Test status
Simulation time 393454221953 ps
CPU time 901.12 seconds
Started Mar 26 12:27:32 PM PDT 24
Finished Mar 26 12:42:33 PM PDT 24
Peak memory 202048 kb
Host smart-2b75f48d-a2ca-49ed-999f-5e4cbf8aea75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917286841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1917286841
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3195194166
Short name T53
Test name
Test status
Simulation time 126534650580 ps
CPU time 670.89 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:38:26 PM PDT 24
Peak memory 202024 kb
Host smart-d7ee0e80-0fdd-4639-a583-5aac9bafd67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195194166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3195194166
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3819927036
Short name T587
Test name
Test status
Simulation time 31641225223 ps
CPU time 76.64 seconds
Started Mar 26 12:27:11 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201480 kb
Host smart-199dfd50-574e-4b68-86a7-8640058b90c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819927036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3819927036
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.858532257
Short name T505
Test name
Test status
Simulation time 5555190514 ps
CPU time 4.76 seconds
Started Mar 26 12:27:12 PM PDT 24
Finished Mar 26 12:27:17 PM PDT 24
Peak memory 201544 kb
Host smart-878750be-fe00-4a79-af5b-3a16ef848981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858532257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.858532257
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2538797718
Short name T631
Test name
Test status
Simulation time 6104832394 ps
CPU time 4.31 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:27:12 PM PDT 24
Peak memory 201520 kb
Host smart-98f53a69-c6e4-4971-bcde-7790b33fa3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538797718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2538797718
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.348671903
Short name T17
Test name
Test status
Simulation time 151791270876 ps
CPU time 69.04 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:29:28 PM PDT 24
Peak memory 210464 kb
Host smart-0b357c28-9326-416c-837c-4cfaab6729c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348671903 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.348671903
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2928838321
Short name T641
Test name
Test status
Simulation time 438359651 ps
CPU time 1.56 seconds
Started Mar 26 12:27:16 PM PDT 24
Finished Mar 26 12:27:18 PM PDT 24
Peak memory 201380 kb
Host smart-49ef0a8f-5d71-4cde-bc73-c491fa1e4344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928838321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2928838321
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3748885349
Short name T195
Test name
Test status
Simulation time 170561510686 ps
CPU time 396.04 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:35:01 PM PDT 24
Peak memory 201828 kb
Host smart-fe1fe085-90f8-4633-a11c-9f383c39ee28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748885349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3748885349
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.972277147
Short name T265
Test name
Test status
Simulation time 488533434749 ps
CPU time 1139.97 seconds
Started Mar 26 12:27:19 PM PDT 24
Finished Mar 26 12:46:20 PM PDT 24
Peak memory 201512 kb
Host smart-cefbd006-7b87-4121-bcc4-d92e7c45b442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972277147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.972277147
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1235746363
Short name T550
Test name
Test status
Simulation time 493746006244 ps
CPU time 241.35 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:32:24 PM PDT 24
Peak memory 201768 kb
Host smart-79fd885d-7f8a-45ba-babe-dcb358ee0351
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235746363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1235746363
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2143265577
Short name T553
Test name
Test status
Simulation time 160338472903 ps
CPU time 48.04 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:29:06 PM PDT 24
Peak memory 201832 kb
Host smart-f2cf6f05-9416-4546-bf85-44c89b260056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143265577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2143265577
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3066393032
Short name T523
Test name
Test status
Simulation time 489502210454 ps
CPU time 1147.92 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:47:28 PM PDT 24
Peak memory 201704 kb
Host smart-9bef6cb4-1563-4f5c-b0bd-31b0209fd245
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066393032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3066393032
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.55487781
Short name T46
Test name
Test status
Simulation time 597952615293 ps
CPU time 1353.51 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:49:47 PM PDT 24
Peak memory 201704 kb
Host smart-74ad1764-f02a-427a-9e58-38dd6e8a8f0c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55487781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
dc_ctrl_filters_wakeup_fixed.55487781
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.790064533
Short name T732
Test name
Test status
Simulation time 126248721561 ps
CPU time 446.61 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:35:42 PM PDT 24
Peak memory 202024 kb
Host smart-8089c847-8def-42e6-8634-8b09636a8443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790064533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.790064533
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1934745541
Short name T718
Test name
Test status
Simulation time 40456430625 ps
CPU time 74.8 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:29:37 PM PDT 24
Peak memory 201516 kb
Host smart-73c7e544-0057-44ba-9b91-d455fe15969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934745541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1934745541
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.522705934
Short name T691
Test name
Test status
Simulation time 4323960288 ps
CPU time 9.99 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:24 PM PDT 24
Peak memory 201292 kb
Host smart-bdb16754-f284-475f-9da2-cce1d8816981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522705934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.522705934
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.322859294
Short name T440
Test name
Test status
Simulation time 5742118842 ps
CPU time 13.19 seconds
Started Mar 26 12:27:16 PM PDT 24
Finished Mar 26 12:27:29 PM PDT 24
Peak memory 201304 kb
Host smart-6b7190b7-03d9-4b02-bfd4-58628a90285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322859294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.322859294
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1277762394
Short name T313
Test name
Test status
Simulation time 276511858838 ps
CPU time 248.81 seconds
Started Mar 26 12:27:24 PM PDT 24
Finished Mar 26 12:31:33 PM PDT 24
Peak memory 210436 kb
Host smart-2287b552-abb8-4f6c-9fe3-845244f862ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277762394 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1277762394
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.972351613
Short name T445
Test name
Test status
Simulation time 358178885 ps
CPU time 0.8 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:28:23 PM PDT 24
Peak memory 201256 kb
Host smart-d4fb6582-7142-4cc2-9734-f58b49b56344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972351613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.972351613
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2239741797
Short name T246
Test name
Test status
Simulation time 339704659932 ps
CPU time 345.93 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:34:06 PM PDT 24
Peak memory 201704 kb
Host smart-ccb4fc61-d77a-4335-980d-99719c9dbf74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239741797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2239741797
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.935212086
Short name T197
Test name
Test status
Simulation time 164258947901 ps
CPU time 42.76 seconds
Started Mar 26 12:27:21 PM PDT 24
Finished Mar 26 12:28:04 PM PDT 24
Peak memory 201828 kb
Host smart-90859d74-158f-4064-ab09-698c8a145cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935212086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.935212086
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3637510132
Short name T501
Test name
Test status
Simulation time 490395278042 ps
CPU time 396.25 seconds
Started Mar 26 12:27:21 PM PDT 24
Finished Mar 26 12:33:58 PM PDT 24
Peak memory 201764 kb
Host smart-8e701a97-8a83-4ea7-9aff-775b17de8be3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637510132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3637510132
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2827314428
Short name T728
Test name
Test status
Simulation time 164259382512 ps
CPU time 53.45 seconds
Started Mar 26 12:27:21 PM PDT 24
Finished Mar 26 12:28:15 PM PDT 24
Peak memory 201788 kb
Host smart-d044f3a0-a2a5-434d-af9c-60ace32bdfd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827314428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2827314428
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.4219589793
Short name T527
Test name
Test status
Simulation time 529206653876 ps
CPU time 300.25 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:32:14 PM PDT 24
Peak memory 201612 kb
Host smart-89b9cf1b-16fa-4362-9574-cff26d01d8fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219589793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.4219589793
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3481582887
Short name T466
Test name
Test status
Simulation time 192607866397 ps
CPU time 98.81 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:29:53 PM PDT 24
Peak memory 201808 kb
Host smart-f95f3bed-45d9-4296-9217-e5c3dbc5f886
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481582887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3481582887
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.715750353
Short name T230
Test name
Test status
Simulation time 135518866654 ps
CPU time 429.76 seconds
Started Mar 26 12:27:17 PM PDT 24
Finished Mar 26 12:34:27 PM PDT 24
Peak memory 202104 kb
Host smart-01e62e1f-48e1-4ab3-99d6-a9b3b43632f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715750353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.715750353
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2827538927
Short name T546
Test name
Test status
Simulation time 38568669589 ps
CPU time 22.73 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:28:41 PM PDT 24
Peak memory 201532 kb
Host smart-fa115d1a-68fd-4e9e-8a9c-0ba8a639b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827538927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2827538927
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.275957777
Short name T489
Test name
Test status
Simulation time 3555679038 ps
CPU time 9.49 seconds
Started Mar 26 12:27:39 PM PDT 24
Finished Mar 26 12:27:49 PM PDT 24
Peak memory 201556 kb
Host smart-d00ada8e-b01a-4de5-9b5a-73f37cba1615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275957777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.275957777
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.706151701
Short name T208
Test name
Test status
Simulation time 5803325175 ps
CPU time 3.02 seconds
Started Mar 26 12:27:22 PM PDT 24
Finished Mar 26 12:27:25 PM PDT 24
Peak memory 201652 kb
Host smart-0a383d17-3885-4f46-a760-0f91f89a04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706151701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.706151701
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1805414666
Short name T791
Test name
Test status
Simulation time 382477037608 ps
CPU time 1411.99 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:51:53 PM PDT 24
Peak memory 210316 kb
Host smart-8cfa1adc-31a9-4642-b9dd-5c03d5622f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805414666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1805414666
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2421885234
Short name T16
Test name
Test status
Simulation time 25546432389 ps
CPU time 104.96 seconds
Started Mar 26 12:27:29 PM PDT 24
Finished Mar 26 12:29:14 PM PDT 24
Peak memory 210404 kb
Host smart-a77630cb-972e-4681-b956-b3b09294c717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421885234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2421885234
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.120220665
Short name T442
Test name
Test status
Simulation time 399174909 ps
CPU time 1.02 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:27:14 PM PDT 24
Peak memory 201412 kb
Host smart-0bfb76d2-c2f1-4542-8d51-e21d1b2ea5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120220665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.120220665
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2634752987
Short name T168
Test name
Test status
Simulation time 535149872558 ps
CPU time 227.11 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:32:10 PM PDT 24
Peak memory 201792 kb
Host smart-2a2af480-c1b5-46fb-a312-b348aa691776
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634752987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2634752987
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3146843597
Short name T345
Test name
Test status
Simulation time 183268615081 ps
CPU time 223.97 seconds
Started Mar 26 12:27:36 PM PDT 24
Finished Mar 26 12:31:20 PM PDT 24
Peak memory 201764 kb
Host smart-036da7a9-9706-4819-a1e6-76e61ac01f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146843597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3146843597
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2855195119
Short name T299
Test name
Test status
Simulation time 326571509049 ps
CPU time 749.59 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:39:44 PM PDT 24
Peak memory 201720 kb
Host smart-3cc8b5ab-a1cc-4e74-841d-f516a1e1912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855195119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2855195119
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.581940489
Short name T544
Test name
Test status
Simulation time 167079836913 ps
CPU time 102 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:29:48 PM PDT 24
Peak memory 201744 kb
Host smart-b6f14c82-6eff-4226-847d-c71b94d20a8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=581940489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.581940489
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3560350283
Short name T456
Test name
Test status
Simulation time 160553670637 ps
CPU time 387.48 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:34:53 PM PDT 24
Peak memory 201324 kb
Host smart-e3d22c59-c6aa-46b1-8cc1-1ab1c2ac09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560350283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3560350283
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3455414398
Short name T785
Test name
Test status
Simulation time 496085232005 ps
CPU time 300.48 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:33:21 PM PDT 24
Peak memory 201708 kb
Host smart-23bcc11e-fc1b-4ee9-b085-51d3f2ef88d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455414398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3455414398
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3988560449
Short name T733
Test name
Test status
Simulation time 362986713606 ps
CPU time 819.37 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:40:54 PM PDT 24
Peak memory 201736 kb
Host smart-8079d226-0c09-4e20-ae9d-b14ebdd7083f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988560449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3988560449
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.182938005
Short name T175
Test name
Test status
Simulation time 395499789299 ps
CPU time 198.94 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:31:41 PM PDT 24
Peak memory 201708 kb
Host smart-dbac3f89-f661-4520-894e-88e6d656de00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182938005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.182938005
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.785539087
Short name T495
Test name
Test status
Simulation time 40854928284 ps
CPU time 12.62 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:28:36 PM PDT 24
Peak memory 201560 kb
Host smart-ff027ee4-a646-4063-80ac-c0b1e44876d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785539087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.785539087
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2568870709
Short name T390
Test name
Test status
Simulation time 3801257169 ps
CPU time 9.48 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201540 kb
Host smart-30a936fe-c5cf-412d-976d-810615191c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568870709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2568870709
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3826798588
Short name T524
Test name
Test status
Simulation time 5761168488 ps
CPU time 14.97 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 201548 kb
Host smart-dc87eab4-b9f6-4415-b9a2-7e28f7f37bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826798588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3826798588
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4015645613
Short name T788
Test name
Test status
Simulation time 302576358923 ps
CPU time 1039.04 seconds
Started Mar 26 12:28:24 PM PDT 24
Finished Mar 26 12:45:44 PM PDT 24
Peak memory 210236 kb
Host smart-2aab5bb7-efcf-4f40-a60b-d7aabeaaf13d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015645613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4015645613
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3848277233
Short name T727
Test name
Test status
Simulation time 290321938240 ps
CPU time 74.8 seconds
Started Mar 26 12:27:46 PM PDT 24
Finished Mar 26 12:29:02 PM PDT 24
Peak memory 211904 kb
Host smart-91f37d09-7ad0-43d9-b726-86fbaba9053d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848277233 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3848277233
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.464360210
Short name T438
Test name
Test status
Simulation time 438673872 ps
CPU time 0.81 seconds
Started Mar 26 12:28:35 PM PDT 24
Finished Mar 26 12:28:37 PM PDT 24
Peak memory 201176 kb
Host smart-433cba3e-3d69-44da-abbf-69aa50886120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464360210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.464360210
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1854143414
Short name T286
Test name
Test status
Simulation time 214470345816 ps
CPU time 422.8 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:35:20 PM PDT 24
Peak memory 201784 kb
Host smart-57f6fd29-17da-4e94-b497-eae6bde9d402
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854143414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1854143414
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.398597295
Short name T611
Test name
Test status
Simulation time 181825169456 ps
CPU time 420.84 seconds
Started Mar 26 12:27:13 PM PDT 24
Finished Mar 26 12:34:14 PM PDT 24
Peak memory 202108 kb
Host smart-b19325a1-add8-4f11-b967-87f35e0b4a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398597295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.398597295
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4130287510
Short name T690
Test name
Test status
Simulation time 494972565287 ps
CPU time 307.77 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:32:23 PM PDT 24
Peak memory 201448 kb
Host smart-e7a78c97-d639-4bf0-9c00-5d0fd639ffbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130287510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4130287510
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4064778948
Short name T593
Test name
Test status
Simulation time 160519226804 ps
CPU time 51.17 seconds
Started Mar 26 12:27:43 PM PDT 24
Finished Mar 26 12:28:35 PM PDT 24
Peak memory 201712 kb
Host smart-7b3f570f-c2cb-45e0-96da-78a308fd6bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064778948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4064778948
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.407356080
Short name T411
Test name
Test status
Simulation time 337117251721 ps
CPU time 191.48 seconds
Started Mar 26 12:27:22 PM PDT 24
Finished Mar 26 12:30:34 PM PDT 24
Peak memory 201712 kb
Host smart-28f88b68-9ec1-4bb0-ad71-491c124928c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=407356080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.407356080
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3418130594
Short name T142
Test name
Test status
Simulation time 532731657568 ps
CPU time 1280.16 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:48:34 PM PDT 24
Peak memory 201772 kb
Host smart-abf5be88-9573-47c1-aec7-69c8d182f021
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418130594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3418130594
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.98355933
Short name T741
Test name
Test status
Simulation time 415734280312 ps
CPU time 243.75 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:32:18 PM PDT 24
Peak memory 202036 kb
Host smart-3f9a6e27-bf08-4e9d-9a40-7a6b8a5690ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98355933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.a
dc_ctrl_filters_wakeup_fixed.98355933
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1067003401
Short name T749
Test name
Test status
Simulation time 59071229948 ps
CPU time 263.44 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:33:00 PM PDT 24
Peak memory 202024 kb
Host smart-0b03c326-08cc-418c-b4cc-f511f7dca1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067003401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1067003401
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2879825032
Short name T451
Test name
Test status
Simulation time 32040879882 ps
CPU time 19.13 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:33 PM PDT 24
Peak memory 201492 kb
Host smart-ff7261a5-0cb8-4cc2-8afd-0317d00f980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879825032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2879825032
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3318634018
Short name T660
Test name
Test status
Simulation time 3731597923 ps
CPU time 2.8 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:28:20 PM PDT 24
Peak memory 201544 kb
Host smart-36730ccb-85e9-4cac-822b-f9c8063d086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318634018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3318634018
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3230673227
Short name T156
Test name
Test status
Simulation time 5539746037 ps
CPU time 14.87 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:28:33 PM PDT 24
Peak memory 201536 kb
Host smart-bdb9a187-816e-452e-8c69-63dffb379a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230673227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3230673227
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3031382166
Short name T426
Test name
Test status
Simulation time 131929448196 ps
CPU time 668.09 seconds
Started Mar 26 12:27:43 PM PDT 24
Finished Mar 26 12:38:52 PM PDT 24
Peak memory 210392 kb
Host smart-44428b26-6e7c-4911-ba75-5fe298fdb06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031382166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3031382166
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3323937876
Short name T686
Test name
Test status
Simulation time 511787790 ps
CPU time 1.72 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:28:16 PM PDT 24
Peak memory 201428 kb
Host smart-7f9bd37c-9ab8-472d-978f-d300208c19f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323937876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3323937876
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.935062224
Short name T186
Test name
Test status
Simulation time 498751414698 ps
CPU time 63.02 seconds
Started Mar 26 12:27:16 PM PDT 24
Finished Mar 26 12:28:19 PM PDT 24
Peak memory 201752 kb
Host smart-e6d29c02-838d-4e98-8078-77bc893a4703
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935062224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.935062224
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3346721591
Short name T50
Test name
Test status
Simulation time 517136563992 ps
CPU time 1138.29 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:47:26 PM PDT 24
Peak memory 200948 kb
Host smart-c9bd6349-59ab-45ae-81de-2f516ad63039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346721591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3346721591
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2964623930
Short name T723
Test name
Test status
Simulation time 164433713708 ps
CPU time 413.95 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:34:09 PM PDT 24
Peak memory 201772 kb
Host smart-92981ced-3c65-4538-a164-ff1b90571126
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964623930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2964623930
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1716306405
Short name T578
Test name
Test status
Simulation time 483246453419 ps
CPU time 1104.21 seconds
Started Mar 26 12:28:02 PM PDT 24
Finished Mar 26 12:46:27 PM PDT 24
Peak memory 201800 kb
Host smart-ef03f2e9-f02d-4af5-84db-a41b72dec59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716306405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1716306405
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2538329340
Short name T2
Test name
Test status
Simulation time 165230466328 ps
CPU time 115.75 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:29:10 PM PDT 24
Peak memory 201764 kb
Host smart-59f85034-7ea5-428f-89a5-f1ffc78c4dd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538329340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2538329340
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3834014098
Short name T180
Test name
Test status
Simulation time 165480194111 ps
CPU time 35.88 seconds
Started Mar 26 12:27:14 PM PDT 24
Finished Mar 26 12:27:50 PM PDT 24
Peak memory 201804 kb
Host smart-37dbb092-826a-4433-b170-aac7296d3bd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834014098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3834014098
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3115360716
Short name T161
Test name
Test status
Simulation time 399323300847 ps
CPU time 464.32 seconds
Started Mar 26 12:27:27 PM PDT 24
Finished Mar 26 12:35:11 PM PDT 24
Peak memory 201580 kb
Host smart-2dff9d92-36b5-4ca3-a590-333bc3eca854
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115360716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3115360716
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3383926271
Short name T3
Test name
Test status
Simulation time 102215193463 ps
CPU time 499.52 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:36:56 PM PDT 24
Peak memory 201900 kb
Host smart-f96bdbd3-6456-499c-984c-644c786d9e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383926271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3383926271
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.863060119
Short name T649
Test name
Test status
Simulation time 44216009338 ps
CPU time 14.14 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:27:29 PM PDT 24
Peak memory 201544 kb
Host smart-74997c3f-4dd5-4573-a19a-a8c9d8818502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863060119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.863060119
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2344303136
Short name T460
Test name
Test status
Simulation time 4204801590 ps
CPU time 3.34 seconds
Started Mar 26 12:28:37 PM PDT 24
Finished Mar 26 12:28:40 PM PDT 24
Peak memory 201520 kb
Host smart-0b62c647-ca0b-4e64-b460-381ba3dac76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344303136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2344303136
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1611625651
Short name T210
Test name
Test status
Simulation time 5892298262 ps
CPU time 15.66 seconds
Started Mar 26 12:27:15 PM PDT 24
Finished Mar 26 12:27:31 PM PDT 24
Peak memory 200752 kb
Host smart-5f55f8ad-e5fe-451b-8e93-5334db2a4430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611625651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1611625651
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4058711923
Short name T716
Test name
Test status
Simulation time 190348887219 ps
CPU time 440.08 seconds
Started Mar 26 12:27:57 PM PDT 24
Finished Mar 26 12:35:17 PM PDT 24
Peak memory 201764 kb
Host smart-1a959a43-c14f-4e80-b644-183e07b26ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058711923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4058711923
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.741132372
Short name T657
Test name
Test status
Simulation time 29202019594 ps
CPU time 72.38 seconds
Started Mar 26 12:27:17 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 211464 kb
Host smart-5d29eeb1-5406-46b0-8c8f-cad785a0a1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741132372 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.741132372
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2375139724
Short name T340
Test name
Test status
Simulation time 160689116258 ps
CPU time 303.4 seconds
Started Mar 26 12:28:04 PM PDT 24
Finished Mar 26 12:33:07 PM PDT 24
Peak memory 201820 kb
Host smart-3a22dc13-8cb4-4fcf-baba-70e5bbdbba89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375139724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2375139724
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3039641192
Short name T360
Test name
Test status
Simulation time 164433240351 ps
CPU time 400.41 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:36:16 PM PDT 24
Peak memory 201240 kb
Host smart-99acf602-6407-40df-8e5c-129318cc8184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039641192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3039641192
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3415565500
Short name T297
Test name
Test status
Simulation time 324243144724 ps
CPU time 190.79 seconds
Started Mar 26 12:28:51 PM PDT 24
Finished Mar 26 12:32:03 PM PDT 24
Peak memory 200176 kb
Host smart-2aca570c-0a1a-44ad-8497-89d7f1a0ca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415565500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3415565500
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3892379720
Short name T502
Test name
Test status
Simulation time 493255770069 ps
CPU time 599.08 seconds
Started Mar 26 12:27:50 PM PDT 24
Finished Mar 26 12:37:49 PM PDT 24
Peak memory 201692 kb
Host smart-bdea54dc-20a6-40c2-8cab-7705b281dcf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892379720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3892379720
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1652198345
Short name T354
Test name
Test status
Simulation time 488218203532 ps
CPU time 533.82 seconds
Started Mar 26 12:27:49 PM PDT 24
Finished Mar 26 12:36:43 PM PDT 24
Peak memory 201720 kb
Host smart-aedb334f-a0a8-45b6-bf4e-e9f56ba6ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652198345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1652198345
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.740000709
Short name T768
Test name
Test status
Simulation time 165618814017 ps
CPU time 364.95 seconds
Started Mar 26 12:27:34 PM PDT 24
Finished Mar 26 12:33:39 PM PDT 24
Peak memory 201672 kb
Host smart-2dd6c3d0-12a0-4e87-8e04-9ac4b1bb575b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740000709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.740000709
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.916991726
Short name T520
Test name
Test status
Simulation time 200426781254 ps
CPU time 469.98 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:36:02 PM PDT 24
Peak memory 201720 kb
Host smart-0e8574c4-8b34-4e79-92ec-3d59bb2ddbe4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916991726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.916991726
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2900897982
Short name T10
Test name
Test status
Simulation time 87027352152 ps
CPU time 337.65 seconds
Started Mar 26 12:27:40 PM PDT 24
Finished Mar 26 12:33:18 PM PDT 24
Peak memory 202024 kb
Host smart-2e4dbda4-2357-4305-b143-d65a6dacb0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900897982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2900897982
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4251944618
Short name T470
Test name
Test status
Simulation time 23639579898 ps
CPU time 55.41 seconds
Started Mar 26 12:28:37 PM PDT 24
Finished Mar 26 12:29:33 PM PDT 24
Peak memory 201556 kb
Host smart-b4fb7cbc-b884-4942-a698-1759471740b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251944618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4251944618
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.610459911
Short name T386
Test name
Test status
Simulation time 2855638561 ps
CPU time 2.29 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:28:30 PM PDT 24
Peak memory 201568 kb
Host smart-a65b14e9-5d25-4362-a4b4-1574af66c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610459911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.610459911
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.842302668
Short name T95
Test name
Test status
Simulation time 5923071431 ps
CPU time 13.14 seconds
Started Mar 26 12:27:53 PM PDT 24
Finished Mar 26 12:28:06 PM PDT 24
Peak memory 201568 kb
Host smart-3322ae46-ded5-4957-81d7-2e9ec1869291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842302668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.842302668
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3800875100
Short name T377
Test name
Test status
Simulation time 176723022701 ps
CPU time 843.91 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:42:27 PM PDT 24
Peak memory 202064 kb
Host smart-84141934-fb72-4c96-bbcc-d53db99d3f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800875100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3800875100
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1649255355
Short name T400
Test name
Test status
Simulation time 472033271 ps
CPU time 0.74 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:28:13 PM PDT 24
Peak memory 201440 kb
Host smart-dcb53172-504c-40fe-b2b1-3887279c2cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649255355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1649255355
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2566173976
Short name T637
Test name
Test status
Simulation time 186509226835 ps
CPU time 88.25 seconds
Started Mar 26 12:27:44 PM PDT 24
Finished Mar 26 12:29:13 PM PDT 24
Peak memory 201724 kb
Host smart-b504c980-aac2-4751-a9a8-ca9338cb04c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566173976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2566173976
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4235963617
Short name T555
Test name
Test status
Simulation time 328640704620 ps
CPU time 411.88 seconds
Started Mar 26 12:27:34 PM PDT 24
Finished Mar 26 12:34:26 PM PDT 24
Peak memory 201800 kb
Host smart-8b82da0b-ea93-4428-88c8-a14988e8909e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235963617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4235963617
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3557155588
Short name T43
Test name
Test status
Simulation time 331841925201 ps
CPU time 746.03 seconds
Started Mar 26 12:28:04 PM PDT 24
Finished Mar 26 12:40:31 PM PDT 24
Peak memory 201700 kb
Host smart-08750201-1723-48ff-a4d1-6193b83c51ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557155588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3557155588
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3198422101
Short name T262
Test name
Test status
Simulation time 168548579417 ps
CPU time 105.27 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:30:04 PM PDT 24
Peak memory 201704 kb
Host smart-9d857b1a-328c-4f93-9d14-2c884542f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198422101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3198422101
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2476910203
Short name T486
Test name
Test status
Simulation time 486272824516 ps
CPU time 1148.41 seconds
Started Mar 26 12:27:30 PM PDT 24
Finished Mar 26 12:46:39 PM PDT 24
Peak memory 201756 kb
Host smart-fb1944c2-8615-4127-9e93-3b07904b9e6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476910203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2476910203
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1891215995
Short name T216
Test name
Test status
Simulation time 217972481458 ps
CPU time 132.42 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:30:24 PM PDT 24
Peak memory 201736 kb
Host smart-47ef2704-c915-4468-b6cd-c40f690ef4cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891215995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1891215995
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2726276382
Short name T794
Test name
Test status
Simulation time 400590782185 ps
CPU time 952.35 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:44:57 PM PDT 24
Peak memory 201052 kb
Host smart-563db397-7497-4180-a62f-e3543bed91aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726276382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2726276382
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3754790332
Short name T685
Test name
Test status
Simulation time 112025095398 ps
CPU time 616.14 seconds
Started Mar 26 12:27:30 PM PDT 24
Finished Mar 26 12:37:47 PM PDT 24
Peak memory 202052 kb
Host smart-0d8f7a41-13ea-4a67-8115-be15d0f90249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754790332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3754790332
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1495151050
Short name T414
Test name
Test status
Simulation time 31253139345 ps
CPU time 17.58 seconds
Started Mar 26 12:28:04 PM PDT 24
Finished Mar 26 12:28:22 PM PDT 24
Peak memory 201532 kb
Host smart-5f2fad0f-2b0b-4c21-976b-aeda24b0f85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495151050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1495151050
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1806325722
Short name T529
Test name
Test status
Simulation time 4993969378 ps
CPU time 11.31 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:28:21 PM PDT 24
Peak memory 201512 kb
Host smart-409072a2-54e6-415a-a41a-847df82f7362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806325722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1806325722
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4284451650
Short name T704
Test name
Test status
Simulation time 6070079929 ps
CPU time 4.8 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:29:40 PM PDT 24
Peak memory 200836 kb
Host smart-9d74a595-9250-4f78-8c81-34e4ee485d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284451650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4284451650
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.600662299
Short name T355
Test name
Test status
Simulation time 489159157460 ps
CPU time 722.3 seconds
Started Mar 26 12:27:37 PM PDT 24
Finished Mar 26 12:39:40 PM PDT 24
Peak memory 201500 kb
Host smart-20ebbcc8-709c-4e79-ba25-7440ae196e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600662299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
600662299
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3851615862
Short name T63
Test name
Test status
Simulation time 95044945468 ps
CPU time 252.8 seconds
Started Mar 26 12:27:26 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 210376 kb
Host smart-7fc4bca0-e2cf-445e-8948-ff42fb77d82f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851615862 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3851615862
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1556094453
Short name T634
Test name
Test status
Simulation time 315929059 ps
CPU time 1.26 seconds
Started Mar 26 12:27:37 PM PDT 24
Finished Mar 26 12:27:39 PM PDT 24
Peak memory 201184 kb
Host smart-aafe71e1-7ffa-49a3-9566-aa4a948cbe40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556094453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1556094453
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.211253790
Short name T188
Test name
Test status
Simulation time 360658724899 ps
CPU time 190.29 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:32:45 PM PDT 24
Peak memory 201464 kb
Host smart-2ef1577e-3444-4b9b-91be-333343896ce9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211253790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.211253790
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3467657439
Short name T223
Test name
Test status
Simulation time 162988505364 ps
CPU time 399.57 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:34:54 PM PDT 24
Peak memory 201712 kb
Host smart-b8d404b8-45b3-4008-bb65-8c98a6a70526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467657439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3467657439
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.554207339
Short name T26
Test name
Test status
Simulation time 161291010051 ps
CPU time 377.47 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:34:29 PM PDT 24
Peak memory 201832 kb
Host smart-cc052832-e065-4344-a3e4-5d3a7f71ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554207339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.554207339
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3728333619
Short name T493
Test name
Test status
Simulation time 327494442508 ps
CPU time 762.79 seconds
Started Mar 26 12:27:26 PM PDT 24
Finished Mar 26 12:40:09 PM PDT 24
Peak memory 201792 kb
Host smart-922f4156-c43e-4262-a72d-757e650f2744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728333619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3728333619
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1614524530
Short name T575
Test name
Test status
Simulation time 161756808481 ps
CPU time 88.3 seconds
Started Mar 26 12:29:07 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 201712 kb
Host smart-9d17a198-328b-4473-bb93-e1143c4c02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614524530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1614524530
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.499151764
Short name T557
Test name
Test status
Simulation time 495624631705 ps
CPU time 1059.75 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:46:06 PM PDT 24
Peak memory 201704 kb
Host smart-83d974a0-3780-4d00-b21d-33a2d1433315
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499151764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.499151764
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3091276749
Short name T143
Test name
Test status
Simulation time 531865040473 ps
CPU time 567.5 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:37:40 PM PDT 24
Peak memory 201824 kb
Host smart-ef935b16-ea12-4cc2-a3b6-3ffa3dd095e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091276749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3091276749
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.958165051
Short name T499
Test name
Test status
Simulation time 593962807380 ps
CPU time 398.32 seconds
Started Mar 26 12:29:01 PM PDT 24
Finished Mar 26 12:35:40 PM PDT 24
Peak memory 201660 kb
Host smart-629beae3-8dc9-4672-8cef-9b7e4c5a5f7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958165051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.958165051
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1288155848
Short name T234
Test name
Test status
Simulation time 113093844785 ps
CPU time 507.52 seconds
Started Mar 26 12:27:40 PM PDT 24
Finished Mar 26 12:36:08 PM PDT 24
Peak memory 202008 kb
Host smart-3c4a30d9-1bd4-4363-82c3-2a2c02736527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288155848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1288155848
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3837995495
Short name T777
Test name
Test status
Simulation time 28842338430 ps
CPU time 67.03 seconds
Started Mar 26 12:27:52 PM PDT 24
Finished Mar 26 12:28:59 PM PDT 24
Peak memory 201504 kb
Host smart-2badd48a-ea2f-4935-b58d-c160ce1e6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837995495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3837995495
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3912975020
Short name T491
Test name
Test status
Simulation time 4895636965 ps
CPU time 3.66 seconds
Started Mar 26 12:27:55 PM PDT 24
Finished Mar 26 12:27:59 PM PDT 24
Peak memory 201548 kb
Host smart-93c552e0-1ea7-4540-9b18-55ff24cd9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912975020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3912975020
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.735554071
Short name T473
Test name
Test status
Simulation time 5584345875 ps
CPU time 14.31 seconds
Started Mar 26 12:28:51 PM PDT 24
Finished Mar 26 12:29:06 PM PDT 24
Peak memory 199696 kb
Host smart-9138c1b7-5821-4535-baf9-23df4f8c8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735554071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.735554071
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2788428881
Short name T789
Test name
Test status
Simulation time 526766793 ps
CPU time 1.17 seconds
Started Mar 26 12:27:01 PM PDT 24
Finished Mar 26 12:27:03 PM PDT 24
Peak memory 201380 kb
Host smart-5670d12c-56c8-4d37-b2e7-8d434e3d7abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788428881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2788428881
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2995502868
Short name T635
Test name
Test status
Simulation time 170440106761 ps
CPU time 195.01 seconds
Started Mar 26 12:26:09 PM PDT 24
Finished Mar 26 12:29:25 PM PDT 24
Peak memory 201792 kb
Host smart-6a905d3c-47b9-488e-817d-0618268b4eb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995502868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2995502868
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1637975305
Short name T363
Test name
Test status
Simulation time 501836628557 ps
CPU time 1170.95 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:45:39 PM PDT 24
Peak memory 201708 kb
Host smart-f8430197-6cf0-44bd-bd74-8ffeccd65923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637975305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1637975305
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3851301214
Short name T744
Test name
Test status
Simulation time 324890433493 ps
CPU time 752.62 seconds
Started Mar 26 12:26:10 PM PDT 24
Finished Mar 26 12:38:43 PM PDT 24
Peak memory 201812 kb
Host smart-21aa4f4c-b171-46e1-b04e-6b26600ef782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851301214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3851301214
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3811141171
Short name T671
Test name
Test status
Simulation time 490473348690 ps
CPU time 587.8 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:35:56 PM PDT 24
Peak memory 201676 kb
Host smart-753204d4-e1c7-4ec9-949a-562e25031cc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811141171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3811141171
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.74656329
Short name T149
Test name
Test status
Simulation time 169593251260 ps
CPU time 363.19 seconds
Started Mar 26 12:26:08 PM PDT 24
Finished Mar 26 12:32:11 PM PDT 24
Peak memory 201796 kb
Host smart-620f1520-84d7-4a2c-9951-050430070f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74656329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.74656329
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.354701676
Short name T680
Test name
Test status
Simulation time 493521756169 ps
CPU time 289.08 seconds
Started Mar 26 12:26:10 PM PDT 24
Finished Mar 26 12:30:59 PM PDT 24
Peak memory 201688 kb
Host smart-b841ba4b-379d-4273-bb4f-d454eabd0cd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=354701676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.354701676
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.609115387
Short name T448
Test name
Test status
Simulation time 606347553390 ps
CPU time 1479.4 seconds
Started Mar 26 12:26:34 PM PDT 24
Finished Mar 26 12:51:14 PM PDT 24
Peak memory 201772 kb
Host smart-01714266-6bc1-4b01-9d05-9289f402e1a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609115387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.609115387
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1857502029
Short name T380
Test name
Test status
Simulation time 117928789135 ps
CPU time 330.84 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:32:34 PM PDT 24
Peak memory 202112 kb
Host smart-4f127f65-738f-4d24-b4e4-e652809f15e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857502029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1857502029
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2961272208
Short name T477
Test name
Test status
Simulation time 42336785669 ps
CPU time 93.61 seconds
Started Mar 26 12:26:11 PM PDT 24
Finished Mar 26 12:27:45 PM PDT 24
Peak memory 201556 kb
Host smart-4701183b-7ee3-4c55-bfcc-5598c2041484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961272208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2961272208
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4261758636
Short name T534
Test name
Test status
Simulation time 4351381650 ps
CPU time 11.29 seconds
Started Mar 26 12:26:07 PM PDT 24
Finished Mar 26 12:26:19 PM PDT 24
Peak memory 201496 kb
Host smart-c4274075-bba3-4845-9a98-a18989102cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261758636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4261758636
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2934090553
Short name T69
Test name
Test status
Simulation time 8443062606 ps
CPU time 21.55 seconds
Started Mar 26 12:26:07 PM PDT 24
Finished Mar 26 12:26:29 PM PDT 24
Peak memory 217300 kb
Host smart-52ad6bf1-3629-443f-bc2c-38234510cce4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934090553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2934090553
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1753998540
Short name T515
Test name
Test status
Simulation time 6013434403 ps
CPU time 1.77 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:28:22 PM PDT 24
Peak memory 201552 kb
Host smart-0d62b6e0-5753-4b94-987e-2aea86fa2167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753998540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1753998540
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2815599141
Short name T743
Test name
Test status
Simulation time 290613303241 ps
CPU time 1047.79 seconds
Started Mar 26 12:26:42 PM PDT 24
Finished Mar 26 12:44:10 PM PDT 24
Peak memory 210308 kb
Host smart-05c16361-1904-4053-aba4-0057a9733563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815599141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2815599141
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1825587756
Short name T23
Test name
Test status
Simulation time 25853759590 ps
CPU time 58.89 seconds
Started Mar 26 12:26:07 PM PDT 24
Finished Mar 26 12:27:06 PM PDT 24
Peak memory 210388 kb
Host smart-9b273350-a6f9-40f3-ab44-b4945fae121e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825587756 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1825587756
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1712425612
Short name T15
Test name
Test status
Simulation time 311884072 ps
CPU time 1.27 seconds
Started Mar 26 12:27:35 PM PDT 24
Finished Mar 26 12:27:36 PM PDT 24
Peak memory 201424 kb
Host smart-60d96be2-f9f6-49c9-8a6d-5c501178534b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712425612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1712425612
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4060043799
Short name T266
Test name
Test status
Simulation time 482375417060 ps
CPU time 363.42 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:34:29 PM PDT 24
Peak memory 201736 kb
Host smart-563bff94-94da-46e2-944f-8a981dab689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060043799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4060043799
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1943444643
Short name T713
Test name
Test status
Simulation time 331600670630 ps
CPU time 189.35 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:31:19 PM PDT 24
Peak memory 201736 kb
Host smart-dc9a60a7-bb3f-427c-b9c0-c12a5eadc740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943444643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1943444643
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3277133261
Short name T103
Test name
Test status
Simulation time 166608148384 ps
CPU time 391.27 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:34:52 PM PDT 24
Peak memory 202080 kb
Host smart-10c4f42c-0f8d-41ef-aa9f-76b6689c2b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277133261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3277133261
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3548263490
Short name T661
Test name
Test status
Simulation time 323438964222 ps
CPU time 718.98 seconds
Started Mar 26 12:27:34 PM PDT 24
Finished Mar 26 12:39:33 PM PDT 24
Peak memory 201676 kb
Host smart-efc9eb02-6213-4b75-a491-e573b9a3a67f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548263490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3548263490
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.465324199
Short name T49
Test name
Test status
Simulation time 352277496170 ps
CPU time 818.61 seconds
Started Mar 26 12:28:35 PM PDT 24
Finished Mar 26 12:42:14 PM PDT 24
Peak memory 201504 kb
Host smart-ac5b7052-c72c-4487-a668-38b7ea0a1489
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465324199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.465324199
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2679930470
Short name T748
Test name
Test status
Simulation time 398395764223 ps
CPU time 233.63 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:32:13 PM PDT 24
Peak memory 201708 kb
Host smart-58b7fcb9-2b15-4247-93d0-76804d19fa1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679930470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2679930470
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.200934707
Short name T237
Test name
Test status
Simulation time 90645239653 ps
CPU time 348.18 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:34:02 PM PDT 24
Peak memory 202184 kb
Host smart-b0c5b98b-6501-4f65-a5ad-6d0af41d1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200934707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.200934707
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2129190475
Short name T29
Test name
Test status
Simulation time 35872322907 ps
CPU time 22.61 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:28:36 PM PDT 24
Peak memory 201512 kb
Host smart-1b76bd75-5432-441c-977f-aa9e2e996991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129190475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2129190475
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.882114373
Short name T656
Test name
Test status
Simulation time 3456679745 ps
CPU time 4.79 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:28:22 PM PDT 24
Peak memory 201548 kb
Host smart-d111bb9e-1ef2-4760-92fc-138b1c6fbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882114373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.882114373
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3008409403
Short name T754
Test name
Test status
Simulation time 5800773117 ps
CPU time 4.52 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:28:14 PM PDT 24
Peak memory 201536 kb
Host smart-77b4cf27-fd98-41b1-bf0f-145de33363ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008409403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3008409403
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.299215446
Short name T35
Test name
Test status
Simulation time 3583655306437 ps
CPU time 7923.67 seconds
Started Mar 26 12:27:45 PM PDT 24
Finished Mar 26 02:39:50 PM PDT 24
Peak memory 210292 kb
Host smart-38281af2-a5ab-4c40-9fd2-2bc1cdb5b23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299215446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
299215446
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4254276320
Short name T385
Test name
Test status
Simulation time 396702117 ps
CPU time 0.81 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:21 PM PDT 24
Peak memory 201432 kb
Host smart-c7a9ba88-66fd-4614-bed6-e2244333a6dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254276320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4254276320
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1584799027
Short name T167
Test name
Test status
Simulation time 170384459771 ps
CPU time 108.85 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 201720 kb
Host smart-55f2fd6f-c578-4c68-951b-b1ed41599f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584799027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1584799027
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2210518876
Short name T221
Test name
Test status
Simulation time 330132315293 ps
CPU time 151.61 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:31:36 PM PDT 24
Peak memory 201680 kb
Host smart-02208770-d252-49df-bed2-460b7c9aea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210518876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2210518876
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.694102348
Short name T44
Test name
Test status
Simulation time 324630365043 ps
CPU time 200.88 seconds
Started Mar 26 12:27:36 PM PDT 24
Finished Mar 26 12:30:57 PM PDT 24
Peak memory 201760 kb
Host smart-1846a65e-f3c6-4837-af10-e2cd857cb911
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=694102348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.694102348
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.13203657
Short name T213
Test name
Test status
Simulation time 495686448451 ps
CPU time 1117.35 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:46:54 PM PDT 24
Peak memory 201780 kb
Host smart-48843c45-70b5-479b-b072-9db0b1ec2e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13203657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.13203657
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.847477696
Short name T433
Test name
Test status
Simulation time 332759558161 ps
CPU time 423.15 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:36:29 PM PDT 24
Peak memory 200492 kb
Host smart-385e255e-e041-438e-9709-66f5bf10b68b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=847477696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.847477696
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2910991218
Short name T310
Test name
Test status
Simulation time 429522693221 ps
CPU time 216.31 seconds
Started Mar 26 12:28:51 PM PDT 24
Finished Mar 26 12:32:28 PM PDT 24
Peak memory 200520 kb
Host smart-6a1a343b-6e47-4f16-9e03-1d249232b1c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910991218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2910991218
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.287983324
Short name T584
Test name
Test status
Simulation time 198732055063 ps
CPU time 121.54 seconds
Started Mar 26 12:29:07 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 201696 kb
Host smart-31a4f900-a043-4a52-995a-54b461127999
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287983324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.287983324
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4178256621
Short name T664
Test name
Test status
Simulation time 102555892117 ps
CPU time 297 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:34:02 PM PDT 24
Peak memory 201348 kb
Host smart-b3727778-8512-44b0-a752-6104c2cde177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178256621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4178256621
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2161390094
Short name T388
Test name
Test status
Simulation time 35754846846 ps
CPU time 19.22 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:28:37 PM PDT 24
Peak memory 201612 kb
Host smart-c6a2cbd2-c1ff-42e7-bc4c-5e9522c125ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161390094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2161390094
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.970118630
Short name T676
Test name
Test status
Simulation time 4865136547 ps
CPU time 5.98 seconds
Started Mar 26 12:28:51 PM PDT 24
Finished Mar 26 12:28:58 PM PDT 24
Peak memory 199780 kb
Host smart-2d9369fd-6fc1-4b81-abe0-92f23f277020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970118630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.970118630
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.699087753
Short name T654
Test name
Test status
Simulation time 5986565657 ps
CPU time 15.77 seconds
Started Mar 26 12:27:26 PM PDT 24
Finished Mar 26 12:27:42 PM PDT 24
Peak memory 201504 kb
Host smart-35e337d6-61ca-4287-9a6c-81980589aabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699087753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.699087753
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3163403858
Short name T670
Test name
Test status
Simulation time 202074087092 ps
CPU time 443.92 seconds
Started Mar 26 12:29:25 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 200096 kb
Host smart-12cdbf49-15b2-43c8-81d1-aedc52cb14ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163403858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3163403858
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2661203026
Short name T291
Test name
Test status
Simulation time 314882752818 ps
CPU time 128.33 seconds
Started Mar 26 12:27:46 PM PDT 24
Finished Mar 26 12:29:55 PM PDT 24
Peak memory 210332 kb
Host smart-65b2b1af-d0e1-473b-a530-6f5915d11379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661203026 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2661203026
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3178470654
Short name T561
Test name
Test status
Simulation time 371280233 ps
CPU time 1.43 seconds
Started Mar 26 12:27:38 PM PDT 24
Finished Mar 26 12:27:39 PM PDT 24
Peak memory 201424 kb
Host smart-c99a446e-ed40-46b3-8c6a-44e83d5b9de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178470654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3178470654
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4276590523
Short name T146
Test name
Test status
Simulation time 353405539434 ps
CPU time 28.05 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:44 PM PDT 24
Peak memory 201672 kb
Host smart-1a2c1ea2-b15f-44af-b234-35455f75f65f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276590523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4276590523
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.305622656
Short name T596
Test name
Test status
Simulation time 163271129373 ps
CPU time 380.67 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:34:38 PM PDT 24
Peak memory 201780 kb
Host smart-346bab40-c273-46e1-ae13-55cdc6179120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305622656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.305622656
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2073103914
Short name T31
Test name
Test status
Simulation time 168322731882 ps
CPU time 254.5 seconds
Started Mar 26 12:27:48 PM PDT 24
Finished Mar 26 12:32:03 PM PDT 24
Peak memory 201768 kb
Host smart-02f0f23a-422f-40a6-a371-60e32b8c4f11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073103914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2073103914
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1320565285
Short name T329
Test name
Test status
Simulation time 331680481249 ps
CPU time 202 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:31:50 PM PDT 24
Peak memory 201708 kb
Host smart-c0176400-9049-4128-8fab-015cbf540e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320565285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1320565285
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2478540817
Short name T516
Test name
Test status
Simulation time 165749548898 ps
CPU time 385.27 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:34:43 PM PDT 24
Peak memory 201728 kb
Host smart-fd600cdf-d058-476f-82da-0ddd29ca2f39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478540817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2478540817
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3858829836
Short name T249
Test name
Test status
Simulation time 378899109634 ps
CPU time 142.26 seconds
Started Mar 26 12:27:41 PM PDT 24
Finished Mar 26 12:30:04 PM PDT 24
Peak memory 201812 kb
Host smart-ed5f2058-eacc-4b1c-a31e-7dba141e4dc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858829836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3858829836
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2083220857
Short name T513
Test name
Test status
Simulation time 411748042639 ps
CPU time 922.36 seconds
Started Mar 26 12:27:37 PM PDT 24
Finished Mar 26 12:43:00 PM PDT 24
Peak memory 201784 kb
Host smart-acd8bbd5-0291-4155-94ce-b726bafa2d30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083220857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2083220857
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.211665865
Short name T492
Test name
Test status
Simulation time 95826309542 ps
CPU time 352.38 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:34:03 PM PDT 24
Peak memory 202040 kb
Host smart-284d52a9-d30b-489d-ae49-cec338fe37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211665865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.211665865
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2994889301
Short name T580
Test name
Test status
Simulation time 41512311411 ps
CPU time 96.21 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:30:04 PM PDT 24
Peak memory 201520 kb
Host smart-ec3c82e8-ee9a-4bf4-86fa-a5f1d0f1fc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994889301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2994889301
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1580448696
Short name T194
Test name
Test status
Simulation time 3527245151 ps
CPU time 4.89 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201552 kb
Host smart-e7e43ebc-db30-4665-8647-ec4a3b35049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580448696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1580448696
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2772566161
Short name T389
Test name
Test status
Simulation time 5578015756 ps
CPU time 4.47 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:20 PM PDT 24
Peak memory 201512 kb
Host smart-462a43ea-685e-4468-9829-0c2af93097f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772566161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2772566161
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.519953235
Short name T702
Test name
Test status
Simulation time 448741847154 ps
CPU time 383.71 seconds
Started Mar 26 12:27:40 PM PDT 24
Finished Mar 26 12:34:04 PM PDT 24
Peak memory 210352 kb
Host smart-4e76e3b8-2cea-4c26-88b9-555d29ebfc4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519953235 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.519953235
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1692336006
Short name T415
Test name
Test status
Simulation time 487557234 ps
CPU time 0.89 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:28:02 PM PDT 24
Peak memory 201440 kb
Host smart-d7158088-6e82-41cc-87b2-e48326e6ec42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692336006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1692336006
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2500021791
Short name T331
Test name
Test status
Simulation time 364096016358 ps
CPU time 793.75 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:41:22 PM PDT 24
Peak memory 201684 kb
Host smart-dc642368-8af2-4659-8726-c2c309df18c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500021791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2500021791
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2647940005
Short name T779
Test name
Test status
Simulation time 344123110911 ps
CPU time 346.9 seconds
Started Mar 26 12:28:02 PM PDT 24
Finished Mar 26 12:33:49 PM PDT 24
Peak memory 201712 kb
Host smart-c5971cd3-0b2a-439a-871a-c6c90e5ccd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647940005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2647940005
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3294752809
Short name T506
Test name
Test status
Simulation time 323731476744 ps
CPU time 194.4 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:31:24 PM PDT 24
Peak memory 201724 kb
Host smart-0c4060bc-a239-46ce-8626-23125af07e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294752809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3294752809
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1987700688
Short name T571
Test name
Test status
Simulation time 323455943455 ps
CPU time 110.36 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:30:12 PM PDT 24
Peak memory 201708 kb
Host smart-e5fbb4f1-265f-4dbd-a665-63a1be372a16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987700688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1987700688
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.637904116
Short name T696
Test name
Test status
Simulation time 162737372274 ps
CPU time 61.93 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:29:04 PM PDT 24
Peak memory 201736 kb
Host smart-bfa91ef2-7ff4-4da5-ad3c-9a437124e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637904116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.637904116
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1525526521
Short name T163
Test name
Test status
Simulation time 320300194120 ps
CPU time 744.77 seconds
Started Mar 26 12:27:37 PM PDT 24
Finished Mar 26 12:40:02 PM PDT 24
Peak memory 201768 kb
Host smart-e2320fc0-785c-495d-8973-1399c8e63041
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525526521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1525526521
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4109124118
Short name T315
Test name
Test status
Simulation time 375739373869 ps
CPU time 225.87 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:32:04 PM PDT 24
Peak memory 201800 kb
Host smart-4ad81fa0-a562-4633-9746-640e9a1005ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109124118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4109124118
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1046066191
Short name T391
Test name
Test status
Simulation time 196568612750 ps
CPU time 463.25 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:36:09 PM PDT 24
Peak memory 201748 kb
Host smart-fc88f0cb-5bef-4c19-a785-890a8c5bd1eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046066191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1046066191
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1754322211
Short name T41
Test name
Test status
Simulation time 118552248751 ps
CPU time 446.2 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:35:43 PM PDT 24
Peak memory 202076 kb
Host smart-09dc5ea4-c943-40e4-ad06-1d58260b4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754322211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1754322211
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4119996220
Short name T756
Test name
Test status
Simulation time 45312374205 ps
CPU time 49.21 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:29:02 PM PDT 24
Peak memory 201544 kb
Host smart-737d6a72-0fb9-4f4a-98bd-b0b15eaf7ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119996220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4119996220
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1249618907
Short name T405
Test name
Test status
Simulation time 4140060702 ps
CPU time 11.07 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201552 kb
Host smart-109ecfe4-8db2-4e8a-92e2-5858d6a92db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249618907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1249618907
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.951194910
Short name T404
Test name
Test status
Simulation time 6025608018 ps
CPU time 13.5 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:28:40 PM PDT 24
Peak memory 201528 kb
Host smart-43303afd-cd33-40ed-ad4f-282649381cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951194910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.951194910
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.379273009
Short name T241
Test name
Test status
Simulation time 171823327456 ps
CPU time 416.74 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:35:12 PM PDT 24
Peak memory 201768 kb
Host smart-8e534fc4-34b5-4ce5-8363-5819b73d744f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379273009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
379273009
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3186909252
Short name T381
Test name
Test status
Simulation time 53081179933 ps
CPU time 155.35 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:30:48 PM PDT 24
Peak memory 210368 kb
Host smart-a7b44442-ff90-477c-90f3-3e6cc14c1d2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186909252 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3186909252
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3459498105
Short name T173
Test name
Test status
Simulation time 344133302 ps
CPU time 1.33 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:16 PM PDT 24
Peak memory 201420 kb
Host smart-05c55c9d-9cde-4777-90a4-0fd98891bc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459498105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3459498105
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3983137832
Short name T610
Test name
Test status
Simulation time 166847813183 ps
CPU time 85.58 seconds
Started Mar 26 12:27:58 PM PDT 24
Finished Mar 26 12:29:24 PM PDT 24
Peak memory 201696 kb
Host smart-87f1ff47-b90e-408c-b802-ac3f93f1e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983137832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3983137832
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1571651992
Short name T85
Test name
Test status
Simulation time 165967160315 ps
CPU time 345.33 seconds
Started Mar 26 12:27:50 PM PDT 24
Finished Mar 26 12:33:36 PM PDT 24
Peak memory 201784 kb
Host smart-fa04b2f9-4741-450a-82b1-a8b37037397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571651992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1571651992
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1285999152
Short name T452
Test name
Test status
Simulation time 499739358902 ps
CPU time 452.94 seconds
Started Mar 26 12:27:42 PM PDT 24
Finished Mar 26 12:35:15 PM PDT 24
Peak memory 201696 kb
Host smart-288621bc-108b-4ac7-9b85-c56652b62ac4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285999152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1285999152
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.746942577
Short name T90
Test name
Test status
Simulation time 164049055351 ps
CPU time 419.84 seconds
Started Mar 26 12:29:02 PM PDT 24
Finished Mar 26 12:36:02 PM PDT 24
Peak memory 201764 kb
Host smart-6cf51380-89dd-480c-ba55-dab5aea8449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746942577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.746942577
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1218477570
Short name T770
Test name
Test status
Simulation time 169129420600 ps
CPU time 86.78 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 201708 kb
Host smart-80485ab0-24e5-4cfd-a795-acd95f4b59cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218477570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1218477570
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4031600821
Short name T581
Test name
Test status
Simulation time 412433731558 ps
CPU time 495.08 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:36:16 PM PDT 24
Peak memory 201736 kb
Host smart-e64aa751-561d-4838-9465-475805f1c89f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031600821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4031600821
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2559045712
Short name T52
Test name
Test status
Simulation time 106375112946 ps
CPU time 368.19 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:34:31 PM PDT 24
Peak memory 202124 kb
Host smart-17cba41f-2dfb-45da-aea6-2b22261a36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559045712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2559045712
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1735310651
Short name T642
Test name
Test status
Simulation time 36090254960 ps
CPU time 77.55 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:29:27 PM PDT 24
Peak memory 201572 kb
Host smart-e9c4cfe3-2c26-4745-828c-acbbe65e9af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735310651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1735310651
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3558790337
Short name T522
Test name
Test status
Simulation time 4554244942 ps
CPU time 6.31 seconds
Started Mar 26 12:27:52 PM PDT 24
Finished Mar 26 12:27:58 PM PDT 24
Peak memory 201552 kb
Host smart-64a42e4a-3338-48e8-86b2-a333de3b7f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558790337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3558790337
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.90568105
Short name T751
Test name
Test status
Simulation time 6095969128 ps
CPU time 4.02 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:28:10 PM PDT 24
Peak memory 201528 kb
Host smart-a9e2a99f-dc23-4386-905d-513bf8a69d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90568105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.90568105
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1903049346
Short name T399
Test name
Test status
Simulation time 342505073 ps
CPU time 0.86 seconds
Started Mar 26 12:29:05 PM PDT 24
Finished Mar 26 12:29:06 PM PDT 24
Peak memory 201284 kb
Host smart-73f66662-199e-49fa-9e5b-8284137c8b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903049346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1903049346
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1176184461
Short name T279
Test name
Test status
Simulation time 493247955569 ps
CPU time 213.29 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:32:00 PM PDT 24
Peak memory 201696 kb
Host smart-3aa660ea-a72b-45f0-8ea8-2b1048408455
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176184461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1176184461
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2668814217
Short name T771
Test name
Test status
Simulation time 166598265111 ps
CPU time 65.95 seconds
Started Mar 26 12:27:48 PM PDT 24
Finished Mar 26 12:28:54 PM PDT 24
Peak memory 201816 kb
Host smart-dd57ee23-3362-4517-94d1-dd483b056bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668814217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2668814217
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2821574066
Short name T277
Test name
Test status
Simulation time 163364281731 ps
CPU time 92.17 seconds
Started Mar 26 12:29:03 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 201376 kb
Host smart-ffeabe5f-c63a-4236-911e-ffc801f0edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821574066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2821574066
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1830582519
Short name T176
Test name
Test status
Simulation time 487081955912 ps
CPU time 196.86 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:31:31 PM PDT 24
Peak memory 201672 kb
Host smart-404465aa-bd9c-4021-90f2-dce4e55782ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830582519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1830582519
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1444670314
Short name T726
Test name
Test status
Simulation time 324705285591 ps
CPU time 406.47 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:35:51 PM PDT 24
Peak memory 201400 kb
Host smart-6aa8113e-6f9a-45c0-ad3f-14a2141c23e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444670314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1444670314
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.913582760
Short name T706
Test name
Test status
Simulation time 488760621211 ps
CPU time 1068.97 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:46:08 PM PDT 24
Peak memory 201692 kb
Host smart-351efe83-8876-46e6-a7af-3bc8345ba7c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=913582760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.913582760
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.742421126
Short name T108
Test name
Test status
Simulation time 336550814492 ps
CPU time 193.91 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:31:20 PM PDT 24
Peak memory 201724 kb
Host smart-04b0da9c-465c-4788-a119-de5b266b5a10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742421126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.742421126
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2753208484
Short name T177
Test name
Test status
Simulation time 589952629109 ps
CPU time 333.8 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:33:53 PM PDT 24
Peak memory 201692 kb
Host smart-04529222-b1e4-44ec-b9b1-4709bd3c6d42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753208484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2753208484
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2125495514
Short name T526
Test name
Test status
Simulation time 23920601697 ps
CPU time 14.17 seconds
Started Mar 26 12:27:47 PM PDT 24
Finished Mar 26 12:28:01 PM PDT 24
Peak memory 201540 kb
Host smart-1e86aedf-9ec5-47da-b2e5-d71f841b52ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125495514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2125495514
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1572479569
Short name T413
Test name
Test status
Simulation time 3310617422 ps
CPU time 8.58 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:29:13 PM PDT 24
Peak memory 201220 kb
Host smart-59f5e320-1cb2-4272-8690-2de17b7f61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572479569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1572479569
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1245691048
Short name T9
Test name
Test status
Simulation time 5862255815 ps
CPU time 12.55 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:28:19 PM PDT 24
Peak memory 201536 kb
Host smart-a72fea7d-c389-41f2-80ee-d2f6a751a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245691048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1245691048
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2915697580
Short name T11
Test name
Test status
Simulation time 12497683394 ps
CPU time 28.42 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:29:33 PM PDT 24
Peak memory 201996 kb
Host smart-566a9700-a66c-4dfc-a314-26ff8fac450e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915697580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2915697580
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2052468220
Short name T207
Test name
Test status
Simulation time 470345433 ps
CPU time 0.92 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:28:12 PM PDT 24
Peak memory 201420 kb
Host smart-6a480ecc-5d2a-407f-81d5-4ab598b89924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052468220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2052468220
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2864239912
Short name T370
Test name
Test status
Simulation time 492254202751 ps
CPU time 272.11 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:32:58 PM PDT 24
Peak memory 201744 kb
Host smart-68307a44-381a-4b08-ac93-0233590c77b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864239912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2864239912
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3532278054
Short name T169
Test name
Test status
Simulation time 353813607755 ps
CPU time 202.66 seconds
Started Mar 26 12:28:04 PM PDT 24
Finished Mar 26 12:31:28 PM PDT 24
Peak memory 201800 kb
Host smart-b07602a8-026f-4441-bdd9-e916bf8b32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532278054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3532278054
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.799968067
Short name T383
Test name
Test status
Simulation time 166176032757 ps
CPU time 200 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:31:43 PM PDT 24
Peak memory 202036 kb
Host smart-5c557725-f65f-4095-b6c3-30a299f289a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=799968067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.799968067
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1493067498
Short name T317
Test name
Test status
Simulation time 328686731981 ps
CPU time 820.72 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:42:00 PM PDT 24
Peak memory 201792 kb
Host smart-e8836958-372a-4af7-a615-ca4a9d41db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493067498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1493067498
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1798475080
Short name T533
Test name
Test status
Simulation time 324418056326 ps
CPU time 809.47 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:41:44 PM PDT 24
Peak memory 201660 kb
Host smart-7fc1b7ee-2eea-42b8-9837-70ce89001c16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798475080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1798475080
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.790033797
Short name T269
Test name
Test status
Simulation time 592869341060 ps
CPU time 115.88 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:31:00 PM PDT 24
Peak memory 201376 kb
Host smart-1916a4da-0189-4d30-97d5-223f63ba7e39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790033797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.790033797
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3183743651
Short name T34
Test name
Test status
Simulation time 192293633735 ps
CPU time 451.13 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:35:48 PM PDT 24
Peak memory 201820 kb
Host smart-0d7765bd-0759-4638-89ce-d9a628aa08a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183743651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3183743651
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2940288154
Short name T719
Test name
Test status
Simulation time 71090723149 ps
CPU time 293.43 seconds
Started Mar 26 12:27:41 PM PDT 24
Finished Mar 26 12:32:35 PM PDT 24
Peak memory 201996 kb
Host smart-ea1ec1cf-6dd6-4572-b795-22e816436bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940288154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2940288154
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3071343654
Short name T425
Test name
Test status
Simulation time 23591355979 ps
CPU time 8.39 seconds
Started Mar 26 12:28:55 PM PDT 24
Finished Mar 26 12:29:04 PM PDT 24
Peak memory 200304 kb
Host smart-230f0bce-cc5a-4819-893f-36d9a9f8f123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071343654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3071343654
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2884058275
Short name T582
Test name
Test status
Simulation time 5193099577 ps
CPU time 3.86 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:20 PM PDT 24
Peak memory 201520 kb
Host smart-f91d7e13-0a53-41b1-959f-3c0842d37a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884058275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2884058275
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.49677492
Short name T566
Test name
Test status
Simulation time 5957333760 ps
CPU time 3.08 seconds
Started Mar 26 12:28:07 PM PDT 24
Finished Mar 26 12:28:10 PM PDT 24
Peak memory 201568 kb
Host smart-142753c6-16d0-4da4-a85f-4a5b0debc886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49677492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.49677492
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3825177434
Short name T358
Test name
Test status
Simulation time 504704497178 ps
CPU time 187.55 seconds
Started Mar 26 12:29:04 PM PDT 24
Finished Mar 26 12:32:11 PM PDT 24
Peak memory 201380 kb
Host smart-ed47aa0a-4e86-4d9e-b70d-e6a429376b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825177434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3825177434
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2159587048
Short name T260
Test name
Test status
Simulation time 152817368419 ps
CPU time 189.3 seconds
Started Mar 26 12:27:39 PM PDT 24
Finished Mar 26 12:30:49 PM PDT 24
Peak memory 218180 kb
Host smart-b53b9a3c-4ca3-4b94-ba52-9f8ea6afd5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159587048 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2159587048
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1974370194
Short name T564
Test name
Test status
Simulation time 463048954 ps
CPU time 0.86 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:20 PM PDT 24
Peak memory 201440 kb
Host smart-7ec65a6f-30e6-4a0f-84a7-d97748dd227a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974370194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1974370194
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1978808588
Short name T786
Test name
Test status
Simulation time 346499115746 ps
CPU time 449.99 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:35:40 PM PDT 24
Peak memory 201816 kb
Host smart-e0611f7d-bf76-4bd1-8d03-6810794e4a01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978808588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1978808588
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4217285581
Short name T137
Test name
Test status
Simulation time 164747668459 ps
CPU time 102.6 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:29:56 PM PDT 24
Peak memory 201476 kb
Host smart-f9b4e985-d602-4cc8-a4e4-e5b49e324ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217285581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4217285581
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3761484815
Short name T102
Test name
Test status
Simulation time 155554397913 ps
CPU time 305.42 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:33:15 PM PDT 24
Peak memory 201744 kb
Host smart-030ade1b-30db-4971-a552-a8c2a2bfd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761484815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3761484815
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1450088730
Short name T701
Test name
Test status
Simulation time 167222992268 ps
CPU time 42.44 seconds
Started Mar 26 12:28:55 PM PDT 24
Finished Mar 26 12:29:38 PM PDT 24
Peak memory 200488 kb
Host smart-853f6e8f-ca81-4349-a495-fbf965473e2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450088730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1450088730
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2783848033
Short name T617
Test name
Test status
Simulation time 485514392434 ps
CPU time 847.67 seconds
Started Mar 26 12:27:56 PM PDT 24
Finished Mar 26 12:42:05 PM PDT 24
Peak memory 201776 kb
Host smart-6c64c5b4-959d-482a-bcf1-4e6b7b436f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783848033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2783848033
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2033073569
Short name T504
Test name
Test status
Simulation time 168451715797 ps
CPU time 202.38 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:31:24 PM PDT 24
Peak memory 200944 kb
Host smart-35509581-52f1-4d69-a0fe-8f1ee2765688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033073569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2033073569
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2190225506
Short name T87
Test name
Test status
Simulation time 183676875606 ps
CPU time 198.17 seconds
Started Mar 26 12:27:42 PM PDT 24
Finished Mar 26 12:31:00 PM PDT 24
Peak memory 201800 kb
Host smart-ed8d5f21-19db-48df-8ef3-c7af8fb248f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190225506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2190225506
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3079309441
Short name T409
Test name
Test status
Simulation time 586762437138 ps
CPU time 1401.97 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:51:22 PM PDT 24
Peak memory 201728 kb
Host smart-f0d4a638-daf3-4968-9bf9-577e19cb8041
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079309441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3079309441
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3229140534
Short name T531
Test name
Test status
Simulation time 113728329427 ps
CPU time 560.11 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:37:41 PM PDT 24
Peak memory 202032 kb
Host smart-d9a0b8e7-373f-4575-ad1e-5ed71355d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229140534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3229140534
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2149628339
Short name T604
Test name
Test status
Simulation time 23934780987 ps
CPU time 53.69 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:29:16 PM PDT 24
Peak memory 201316 kb
Host smart-bbb90bf0-43cf-4238-8a6b-17e234bfd46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149628339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2149628339
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3601182495
Short name T632
Test name
Test status
Simulation time 5329088859 ps
CPU time 13.97 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:28:24 PM PDT 24
Peak memory 201476 kb
Host smart-9da295ff-d5a4-4683-a0d4-afab3cda02a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601182495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3601182495
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.307096419
Short name T605
Test name
Test status
Simulation time 5836717697 ps
CPU time 7.65 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:27 PM PDT 24
Peak memory 201324 kb
Host smart-df9e9fe8-d0f5-4085-a7d4-f96f10e5ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307096419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.307096419
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2794822322
Short name T761
Test name
Test status
Simulation time 324137694450 ps
CPU time 1075.52 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:46:17 PM PDT 24
Peak memory 202020 kb
Host smart-2fc12906-3ef0-4ea3-80d4-212c1790faac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794822322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2794822322
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4239820291
Short name T772
Test name
Test status
Simulation time 42196623939 ps
CPU time 23.04 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:28:49 PM PDT 24
Peak memory 201868 kb
Host smart-1f1ee3f3-1f95-463f-8d37-28a324c7523d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239820291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4239820291
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3150929662
Short name T609
Test name
Test status
Simulation time 465100470 ps
CPU time 1.7 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:28:25 PM PDT 24
Peak memory 201428 kb
Host smart-46ccad59-d9cf-41bf-93fd-380eec9a961b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150929662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3150929662
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3168821805
Short name T628
Test name
Test status
Simulation time 364279227024 ps
CPU time 154.97 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:30:54 PM PDT 24
Peak memory 201808 kb
Host smart-9c3feabb-b9d4-46ce-a617-0f45571f6c9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168821805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3168821805
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4149691427
Short name T159
Test name
Test status
Simulation time 165532995224 ps
CPU time 63.72 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:29:26 PM PDT 24
Peak memory 201712 kb
Host smart-3c3b2814-483b-4f82-9578-aabb08d4a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149691427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4149691427
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4115246504
Short name T362
Test name
Test status
Simulation time 493257290312 ps
CPU time 1200.52 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:48:13 PM PDT 24
Peak memory 201744 kb
Host smart-72e15c55-789a-41df-8dea-b070f7d15545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115246504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4115246504
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.270692253
Short name T152
Test name
Test status
Simulation time 163870430842 ps
CPU time 26.11 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:28:40 PM PDT 24
Peak memory 201716 kb
Host smart-22936b5e-156c-43a9-b8a7-77b6f985a370
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270692253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.270692253
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4102513703
Short name T606
Test name
Test status
Simulation time 489580206224 ps
CPU time 515.63 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:36:58 PM PDT 24
Peak memory 201752 kb
Host smart-66c0e735-2859-41d4-86ad-8dec76bfac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102513703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4102513703
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3229626623
Short name T556
Test name
Test status
Simulation time 330169464794 ps
CPU time 373.5 seconds
Started Mar 26 12:27:38 PM PDT 24
Finished Mar 26 12:33:52 PM PDT 24
Peak memory 201784 kb
Host smart-d7b704bd-9b77-44e7-bb67-bf5affa364f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229626623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3229626623
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.617583538
Short name T353
Test name
Test status
Simulation time 478183961785 ps
CPU time 579.95 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:38:06 PM PDT 24
Peak memory 201764 kb
Host smart-480fbb33-f461-4102-8095-36c781116689
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617583538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.617583538
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2540887241
Short name T162
Test name
Test status
Simulation time 393810091410 ps
CPU time 458.64 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:36:07 PM PDT 24
Peak memory 201800 kb
Host smart-1a618848-ef48-4838-9387-0e248b3e2225
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540887241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2540887241
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1771966755
Short name T775
Test name
Test status
Simulation time 94923736274 ps
CPU time 336.75 seconds
Started Mar 26 12:27:36 PM PDT 24
Finished Mar 26 12:33:13 PM PDT 24
Peak memory 202028 kb
Host smart-d85dd0ff-c9ef-4ce8-bb25-6776a978bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771966755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1771966755
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.626153347
Short name T525
Test name
Test status
Simulation time 39310115308 ps
CPU time 21.03 seconds
Started Mar 26 12:28:24 PM PDT 24
Finished Mar 26 12:28:46 PM PDT 24
Peak memory 201536 kb
Host smart-caa37ca9-29d5-4cb2-869d-442406986496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626153347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.626153347
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3136740502
Short name T552
Test name
Test status
Simulation time 3875439386 ps
CPU time 2.71 seconds
Started Mar 26 12:27:46 PM PDT 24
Finished Mar 26 12:27:49 PM PDT 24
Peak memory 201324 kb
Host smart-806809f4-04e9-45cf-8f4f-9112701e73bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136740502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3136740502
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4069041130
Short name T514
Test name
Test status
Simulation time 5731938837 ps
CPU time 4.59 seconds
Started Mar 26 12:27:39 PM PDT 24
Finished Mar 26 12:27:44 PM PDT 24
Peak memory 201532 kb
Host smart-7b94c4a7-ff1a-4a25-9145-886739e78941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069041130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4069041130
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3132225900
Short name T589
Test name
Test status
Simulation time 347298735 ps
CPU time 0.76 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:28:00 PM PDT 24
Peak memory 201428 kb
Host smart-21041be9-f3a4-4014-aabc-ddcccbf1b51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132225900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3132225900
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3012467878
Short name T372
Test name
Test status
Simulation time 503427532788 ps
CPU time 663.91 seconds
Started Mar 26 12:27:58 PM PDT 24
Finished Mar 26 12:39:02 PM PDT 24
Peak memory 201744 kb
Host smart-88f7c1da-1eb5-40d0-9d18-90e87cb1a627
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012467878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3012467878
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2780817837
Short name T209
Test name
Test status
Simulation time 163969668011 ps
CPU time 386.69 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:34:34 PM PDT 24
Peak memory 201508 kb
Host smart-235c7be0-15bc-4adc-aa9a-60e272cf9cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780817837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2780817837
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2035700964
Short name T665
Test name
Test status
Simulation time 167229425086 ps
CPU time 318.6 seconds
Started Mar 26 12:27:55 PM PDT 24
Finished Mar 26 12:33:13 PM PDT 24
Peak memory 201696 kb
Host smart-d4cebdc6-af9c-4c08-b72e-fa2fab81f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035700964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2035700964
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2075828456
Short name T416
Test name
Test status
Simulation time 320230095873 ps
CPU time 142.93 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:30:48 PM PDT 24
Peak memory 201796 kb
Host smart-b72ff45e-f84e-49c7-b3b9-97394ca5ff47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075828456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2075828456
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.456611729
Short name T469
Test name
Test status
Simulation time 160719057871 ps
CPU time 49.86 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:29:15 PM PDT 24
Peak memory 201872 kb
Host smart-3acc1132-1aa9-4da7-a643-96cf4d28ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456611729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.456611729
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.74341005
Short name T196
Test name
Test status
Simulation time 324581722932 ps
CPU time 407.88 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:35:13 PM PDT 24
Peak memory 201832 kb
Host smart-a5bac297-3d7d-4108-9e68-2b4b959123db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74341005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed
.74341005
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.391078798
Short name T444
Test name
Test status
Simulation time 598823989820 ps
CPU time 217.24 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:32:04 PM PDT 24
Peak memory 201700 kb
Host smart-1593544a-9185-4a99-a12a-2ea1d00331d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391078798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.391078798
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.985022640
Short name T600
Test name
Test status
Simulation time 118701551193 ps
CPU time 498.02 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:36:39 PM PDT 24
Peak memory 202036 kb
Host smart-f6b6515b-1a11-4034-b9a6-9d3c8d187777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985022640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.985022640
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3052644275
Short name T793
Test name
Test status
Simulation time 42763486895 ps
CPU time 46 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:29:09 PM PDT 24
Peak memory 201540 kb
Host smart-ea454b5d-4c31-4c1a-a27d-463825e162e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052644275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3052644275
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2971682379
Short name T790
Test name
Test status
Simulation time 3474602627 ps
CPU time 8.41 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:24 PM PDT 24
Peak memory 201516 kb
Host smart-31947c19-81e1-4108-b2c3-e2460933aa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971682379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2971682379
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.345043635
Short name T626
Test name
Test status
Simulation time 5809177614 ps
CPU time 7.41 seconds
Started Mar 26 12:28:07 PM PDT 24
Finished Mar 26 12:28:14 PM PDT 24
Peak memory 201524 kb
Host smart-bfd9d532-bc73-455f-91b9-0c7e5b83245f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345043635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.345043635
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1876813868
Short name T337
Test name
Test status
Simulation time 273119757175 ps
CPU time 142.04 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:30:39 PM PDT 24
Peak memory 201704 kb
Host smart-8feac799-af8b-4d4a-9468-9425bffd27ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876813868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1876813868
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.519385474
Short name T449
Test name
Test status
Simulation time 531264994 ps
CPU time 1.11 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:26:26 PM PDT 24
Peak memory 201404 kb
Host smart-4141da0a-42fe-497c-882b-f8a18bf091db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519385474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.519385474
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.144325662
Short name T321
Test name
Test status
Simulation time 335466232245 ps
CPU time 694.61 seconds
Started Mar 26 12:26:29 PM PDT 24
Finished Mar 26 12:38:04 PM PDT 24
Peak memory 201752 kb
Host smart-b953de7e-fca5-4125-a1f2-3d0414a895cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144325662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.144325662
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2372819126
Short name T282
Test name
Test status
Simulation time 320763621930 ps
CPU time 196.34 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:30:23 PM PDT 24
Peak memory 201704 kb
Host smart-4c4682a8-0aeb-4c0f-9ab2-ba3949982180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372819126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2372819126
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1963851524
Short name T342
Test name
Test status
Simulation time 163605870003 ps
CPU time 351.91 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:32:52 PM PDT 24
Peak memory 201760 kb
Host smart-d254c62b-844a-4c9d-b62c-3ae3cbe4f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963851524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1963851524
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4164449624
Short name T482
Test name
Test status
Simulation time 501218145258 ps
CPU time 198.62 seconds
Started Mar 26 12:26:41 PM PDT 24
Finished Mar 26 12:29:59 PM PDT 24
Peak memory 202040 kb
Host smart-9fc3e894-6a9d-4d6f-847a-ca9db55d9932
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164449624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4164449624
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4244213866
Short name T736
Test name
Test status
Simulation time 331192924856 ps
CPU time 386.68 seconds
Started Mar 26 12:26:36 PM PDT 24
Finished Mar 26 12:33:03 PM PDT 24
Peak memory 201860 kb
Host smart-9534b93c-5d95-4e0a-9829-14d2db3d40f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244213866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4244213866
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.489285669
Short name T782
Test name
Test status
Simulation time 339575804062 ps
CPU time 403.27 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:33:51 PM PDT 24
Peak memory 201852 kb
Host smart-5671aad8-a214-4565-a9d2-219625a6179d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489285669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.489285669
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.263017630
Short name T538
Test name
Test status
Simulation time 561857564247 ps
CPU time 631.2 seconds
Started Mar 26 12:27:08 PM PDT 24
Finished Mar 26 12:37:39 PM PDT 24
Peak memory 201752 kb
Host smart-f310d98a-1cf5-4e5a-a299-55cd52386221
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263017630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.263017630
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.203177948
Short name T459
Test name
Test status
Simulation time 604906204183 ps
CPU time 668.89 seconds
Started Mar 26 12:26:33 PM PDT 24
Finished Mar 26 12:37:43 PM PDT 24
Peak memory 201688 kb
Host smart-a4300632-2524-4666-8e2c-ff066f8a10a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203177948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.203177948
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1492726087
Short name T86
Test name
Test status
Simulation time 106371761976 ps
CPU time 573.07 seconds
Started Mar 26 12:27:41 PM PDT 24
Finished Mar 26 12:37:15 PM PDT 24
Peak memory 202072 kb
Host smart-8e2202e5-9976-4c51-99d9-db1ff20d9e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492726087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1492726087
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1305455606
Short name T172
Test name
Test status
Simulation time 42193828897 ps
CPU time 92.81 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:27:52 PM PDT 24
Peak memory 201336 kb
Host smart-5d93eb9d-43e2-47e0-b10e-441dc1f63748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305455606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1305455606
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1572770361
Short name T729
Test name
Test status
Simulation time 4798519502 ps
CPU time 3.26 seconds
Started Mar 26 12:26:56 PM PDT 24
Finished Mar 26 12:26:59 PM PDT 24
Peak memory 201548 kb
Host smart-fc969c2f-149c-4d66-8d72-1c40895c7eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572770361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1572770361
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1106979723
Short name T67
Test name
Test status
Simulation time 7750133147 ps
CPU time 18.6 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:28:41 PM PDT 24
Peak memory 218292 kb
Host smart-9a328a29-a660-47e0-897c-8734e0431c11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106979723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1106979723
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2280517352
Short name T174
Test name
Test status
Simulation time 5931782858 ps
CPU time 2.67 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:21 PM PDT 24
Peak memory 201484 kb
Host smart-cc7e03d9-6ba0-446c-b46c-d48130cac172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280517352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2280517352
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1029401327
Short name T98
Test name
Test status
Simulation time 168110703348 ps
CPU time 114.17 seconds
Started Mar 26 12:26:24 PM PDT 24
Finished Mar 26 12:28:19 PM PDT 24
Peak memory 210224 kb
Host smart-30762532-58e2-4cd2-83dc-1605b4b9d8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029401327 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1029401327
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2387682711
Short name T462
Test name
Test status
Simulation time 426275249 ps
CPU time 1.07 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:16 PM PDT 24
Peak memory 201428 kb
Host smart-1e4ec6ac-61ed-4ab3-9434-a2b8652f7aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387682711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2387682711
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1782230290
Short name T679
Test name
Test status
Simulation time 379414053222 ps
CPU time 876.75 seconds
Started Mar 26 12:28:29 PM PDT 24
Finished Mar 26 12:43:06 PM PDT 24
Peak memory 201812 kb
Host smart-cfe9942f-d1da-4a01-b7cc-0286dfdd7350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782230290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1782230290
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2004474912
Short name T453
Test name
Test status
Simulation time 493579218965 ps
CPU time 544.09 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:37:22 PM PDT 24
Peak memory 201500 kb
Host smart-bb322bbe-7cd5-4f40-8357-d654dd412716
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004474912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2004474912
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2625458813
Short name T200
Test name
Test status
Simulation time 322787189688 ps
CPU time 134.83 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:30:33 PM PDT 24
Peak memory 201820 kb
Host smart-23b3a614-37d6-4271-93f2-bdeef6988f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625458813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2625458813
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.722593890
Short name T408
Test name
Test status
Simulation time 487946497042 ps
CPU time 1008.27 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:45:10 PM PDT 24
Peak memory 201720 kb
Host smart-0bedfcd6-3cfc-4446-aeb3-85220634bece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722593890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.722593890
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.109485082
Short name T263
Test name
Test status
Simulation time 355142585306 ps
CPU time 843.1 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:42:21 PM PDT 24
Peak memory 201824 kb
Host smart-f30ee099-0675-4278-ac2c-8609f999d02b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109485082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.109485082
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3788662084
Short name T638
Test name
Test status
Simulation time 200957717683 ps
CPU time 239.62 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:32:26 PM PDT 24
Peak memory 201724 kb
Host smart-a9a3628f-ce40-4717-948c-88edf6481a64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788662084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3788662084
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.395178016
Short name T532
Test name
Test status
Simulation time 106004367620 ps
CPU time 379.16 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:34:42 PM PDT 24
Peak memory 202452 kb
Host smart-74a96b43-f08c-4690-8105-832d1c93d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395178016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.395178016
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1028557074
Short name T658
Test name
Test status
Simulation time 33051079646 ps
CPU time 77.65 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:29:11 PM PDT 24
Peak memory 201900 kb
Host smart-606f1c34-d495-4fec-ad36-208e8b3eb27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028557074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1028557074
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2620024421
Short name T703
Test name
Test status
Simulation time 3998935588 ps
CPU time 5.36 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:28:27 PM PDT 24
Peak memory 201532 kb
Host smart-7318124c-7bef-4241-ad07-598a7e0d8899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620024421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2620024421
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.837744848
Short name T30
Test name
Test status
Simulation time 5784814533 ps
CPU time 7.51 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:28:01 PM PDT 24
Peak memory 201548 kb
Host smart-ca290431-7d66-4263-8b09-351324dbec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837744848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.837744848
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.7310730
Short name T220
Test name
Test status
Simulation time 355963585164 ps
CPU time 434.75 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:35:44 PM PDT 24
Peak memory 201828 kb
Host smart-8a8c5ed4-c3a8-4b34-9735-c6a03f367a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7310730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.7310730
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.489108249
Short name T28
Test name
Test status
Simulation time 444763362 ps
CPU time 0.85 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:28:01 PM PDT 24
Peak memory 201416 kb
Host smart-0e477a2e-7d99-48e4-8578-446b6ebabb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489108249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.489108249
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2516361616
Short name T289
Test name
Test status
Simulation time 537939567730 ps
CPU time 1215.18 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:48:32 PM PDT 24
Peak memory 201840 kb
Host smart-f07af6f6-6b90-4629-8804-596c0843dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516361616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2516361616
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3916581251
Short name T359
Test name
Test status
Simulation time 331292197225 ps
CPU time 310.68 seconds
Started Mar 26 12:28:34 PM PDT 24
Finished Mar 26 12:33:45 PM PDT 24
Peak memory 201752 kb
Host smart-30b099c9-12aa-4a76-a40a-314ccc7fc3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916581251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3916581251
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.369627993
Short name T668
Test name
Test status
Simulation time 339223040189 ps
CPU time 190.73 seconds
Started Mar 26 12:27:59 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 201700 kb
Host smart-c98f2ffa-d414-4647-9e3d-b36fcd7bfe34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=369627993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.369627993
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1717791724
Short name T179
Test name
Test status
Simulation time 329317090080 ps
CPU time 801.09 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:41:46 PM PDT 24
Peak memory 201808 kb
Host smart-79cdc20c-c1de-4764-91a9-87de432a0541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717791724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1717791724
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2993289205
Short name T191
Test name
Test status
Simulation time 494107428948 ps
CPU time 295.21 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:33:21 PM PDT 24
Peak memory 201760 kb
Host smart-295a30de-caeb-4c61-90db-b2807afe31c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993289205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2993289205
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4076645053
Short name T352
Test name
Test status
Simulation time 391831528121 ps
CPU time 882.6 seconds
Started Mar 26 12:28:36 PM PDT 24
Finished Mar 26 12:43:19 PM PDT 24
Peak memory 201768 kb
Host smart-fc956435-62a9-4e9b-ac9c-e58e2cde6749
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076645053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4076645053
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.314674560
Short name T778
Test name
Test status
Simulation time 393148455751 ps
CPU time 954.35 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:44:05 PM PDT 24
Peak memory 201692 kb
Host smart-284fd962-395e-4ff2-b747-33c291f5e755
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314674560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.314674560
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3029209380
Short name T592
Test name
Test status
Simulation time 103836614879 ps
CPU time 593.64 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:38:20 PM PDT 24
Peak memory 202008 kb
Host smart-155baaca-59fc-4f09-a8dc-4283b134e4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029209380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3029209380
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.552090074
Short name T428
Test name
Test status
Simulation time 43058726425 ps
CPU time 7 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:28:33 PM PDT 24
Peak memory 201564 kb
Host smart-45fc634b-b6ea-4280-b70a-5680497fa00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552090074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.552090074
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3452921678
Short name T762
Test name
Test status
Simulation time 4888617514 ps
CPU time 11.68 seconds
Started Mar 26 12:29:33 PM PDT 24
Finished Mar 26 12:29:45 PM PDT 24
Peak memory 201292 kb
Host smart-31c44ba2-a563-4eda-a26b-597272b8ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452921678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3452921678
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1551722361
Short name T594
Test name
Test status
Simulation time 5695425995 ps
CPU time 3.34 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:28:04 PM PDT 24
Peak memory 201484 kb
Host smart-78e209e7-b81d-4cba-b677-765a07414d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551722361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1551722361
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.761682403
Short name T653
Test name
Test status
Simulation time 37584220259 ps
CPU time 22.88 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:39 PM PDT 24
Peak memory 210084 kb
Host smart-02307668-71d6-41fb-b6f4-2faa487c1c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761682403 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.761682403
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3254969168
Short name T705
Test name
Test status
Simulation time 390435131 ps
CPU time 1.54 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:18 PM PDT 24
Peak memory 201452 kb
Host smart-88eaabcd-acdf-4570-a68f-3fbef5ea1602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254969168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3254969168
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3500830605
Short name T303
Test name
Test status
Simulation time 487156826715 ps
CPU time 1039.42 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:45:40 PM PDT 24
Peak memory 201596 kb
Host smart-552fb798-e737-4195-8b3b-cd8ee150c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500830605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3500830605
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3728679821
Short name T722
Test name
Test status
Simulation time 330866661394 ps
CPU time 180.67 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:30:55 PM PDT 24
Peak memory 201820 kb
Host smart-72c259bf-52bd-4ae4-801d-a1dab219dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728679821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3728679821
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1137202850
Short name T614
Test name
Test status
Simulation time 328267692420 ps
CPU time 372.06 seconds
Started Mar 26 12:28:29 PM PDT 24
Finished Mar 26 12:34:41 PM PDT 24
Peak memory 201728 kb
Host smart-ad3ad74d-c324-4da5-90a1-05df8923ef4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137202850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1137202850
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3501069895
Short name T89
Test name
Test status
Simulation time 171133806653 ps
CPU time 188.64 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:31:32 PM PDT 24
Peak memory 201724 kb
Host smart-bc710bb4-51d1-4015-953a-c62bf71143d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501069895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3501069895
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.824848530
Short name T467
Test name
Test status
Simulation time 497822340343 ps
CPU time 295.58 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:33:19 PM PDT 24
Peak memory 201716 kb
Host smart-be950194-245a-4082-ba5c-40424281653d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824848530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.824848530
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2706149292
Short name T344
Test name
Test status
Simulation time 190343030325 ps
CPU time 197.87 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:32:53 PM PDT 24
Peak memory 201556 kb
Host smart-0b3afe90-f7a7-4e7a-bf1e-2751c50ee13d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706149292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2706149292
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1469898046
Short name T393
Test name
Test status
Simulation time 394427655764 ps
CPU time 552.54 seconds
Started Mar 26 12:28:35 PM PDT 24
Finished Mar 26 12:37:48 PM PDT 24
Peak memory 201812 kb
Host smart-64bc0656-6004-4b36-843e-830c84bcc383
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469898046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1469898046
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3147642230
Short name T694
Test name
Test status
Simulation time 92448351519 ps
CPU time 391.63 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:34:43 PM PDT 24
Peak memory 202088 kb
Host smart-367f057d-949b-4097-9111-422c91022e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147642230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3147642230
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2683150230
Short name T484
Test name
Test status
Simulation time 30806167403 ps
CPU time 71.63 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:29:38 PM PDT 24
Peak memory 201544 kb
Host smart-d374b517-1fdb-4845-a747-01dd6d66c883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683150230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2683150230
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.53875567
Short name T678
Test name
Test status
Simulation time 2973051960 ps
CPU time 2.43 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:28:25 PM PDT 24
Peak memory 201556 kb
Host smart-8edc8e15-8378-4153-80a6-f28079910413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53875567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.53875567
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3801789385
Short name T698
Test name
Test status
Simulation time 5752594722 ps
CPU time 7.96 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:28:34 PM PDT 24
Peak memory 201552 kb
Host smart-17de08f7-083c-4cec-b6a7-67e5b84b830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801789385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3801789385
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1480713547
Short name T255
Test name
Test status
Simulation time 43685996495 ps
CPU time 109.47 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:30:16 PM PDT 24
Peak memory 217484 kb
Host smart-4b7919fd-77ce-4caa-a7be-626d7487e13f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480713547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1480713547
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2069753854
Short name T431
Test name
Test status
Simulation time 512779109 ps
CPU time 1.41 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:28:16 PM PDT 24
Peak memory 201432 kb
Host smart-bbc3fd25-17ab-4cad-baa7-189ec6883db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069753854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2069753854
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2035298683
Short name T251
Test name
Test status
Simulation time 331923657750 ps
CPU time 814.65 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:41:52 PM PDT 24
Peak memory 201820 kb
Host smart-308855d8-c278-4179-adb5-89685a38501d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035298683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2035298683
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2779915267
Short name T113
Test name
Test status
Simulation time 330086454958 ps
CPU time 427.06 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:35:30 PM PDT 24
Peak memory 201720 kb
Host smart-9ed1bccd-8f9e-44ab-ac95-3ddffc606305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779915267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2779915267
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3761422665
Short name T652
Test name
Test status
Simulation time 162532468864 ps
CPU time 38.37 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:28:56 PM PDT 24
Peak memory 201704 kb
Host smart-90fef28a-5580-452b-930b-5c69557d3a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761422665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3761422665
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1819606432
Short name T274
Test name
Test status
Simulation time 490442388498 ps
CPU time 662.99 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:39:22 PM PDT 24
Peak memory 201752 kb
Host smart-b153c680-d0e9-43a9-97af-d06d0baebc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819606432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1819606432
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2285893060
Short name T13
Test name
Test status
Simulation time 326387747360 ps
CPU time 210.93 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:31:47 PM PDT 24
Peak memory 201688 kb
Host smart-d4f29a00-0da3-4f1a-a0a1-f3b8d6dcc87e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285893060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2285893060
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1483782732
Short name T140
Test name
Test status
Simulation time 200687616749 ps
CPU time 119.21 seconds
Started Mar 26 12:28:02 PM PDT 24
Finished Mar 26 12:30:02 PM PDT 24
Peak memory 201572 kb
Host smart-303932b2-6793-4361-9156-6950acf5acbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483782732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1483782732
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1950090329
Short name T392
Test name
Test status
Simulation time 200770166511 ps
CPU time 440.05 seconds
Started Mar 26 12:28:04 PM PDT 24
Finished Mar 26 12:35:24 PM PDT 24
Peak memory 201736 kb
Host smart-962a06ca-c8d9-4760-8b3e-41b4319d4190
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950090329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1950090329
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3283307725
Short name T655
Test name
Test status
Simulation time 102088891756 ps
CPU time 577.28 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:37:48 PM PDT 24
Peak memory 202056 kb
Host smart-314ca536-763a-4aab-a90d-ab2102874885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283307725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3283307725
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3677462767
Short name T483
Test name
Test status
Simulation time 25528856499 ps
CPU time 23.15 seconds
Started Mar 26 12:28:00 PM PDT 24
Finished Mar 26 12:28:23 PM PDT 24
Peak memory 201512 kb
Host smart-304eba93-4de1-447c-812b-f7b3cd4edb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677462767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3677462767
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4032351916
Short name T781
Test name
Test status
Simulation time 5546113299 ps
CPU time 6.74 seconds
Started Mar 26 12:28:06 PM PDT 24
Finished Mar 26 12:28:13 PM PDT 24
Peak memory 201536 kb
Host smart-0bfceb81-1459-4f47-917b-3b7f42506aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032351916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4032351916
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3497407773
Short name T734
Test name
Test status
Simulation time 6188359333 ps
CPU time 7.36 seconds
Started Mar 26 12:27:56 PM PDT 24
Finished Mar 26 12:28:04 PM PDT 24
Peak memory 201536 kb
Host smart-b8377298-6faf-47f0-895a-28a41855239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497407773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3497407773
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2695257716
Short name T219
Test name
Test status
Simulation time 182244883567 ps
CPU time 107.18 seconds
Started Mar 26 12:27:59 PM PDT 24
Finished Mar 26 12:29:46 PM PDT 24
Peak memory 201708 kb
Host smart-629af582-0ea4-4fbd-a2ad-accff3a86ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695257716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2695257716
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1569556870
Short name T36
Test name
Test status
Simulation time 137861111786 ps
CPU time 462.02 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:35:52 PM PDT 24
Peak memory 210484 kb
Host smart-98953e07-3e73-4b59-a791-40a7572793ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569556870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1569556870
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2276675803
Short name T674
Test name
Test status
Simulation time 426204189 ps
CPU time 1.12 seconds
Started Mar 26 12:28:12 PM PDT 24
Finished Mar 26 12:28:13 PM PDT 24
Peak memory 201456 kb
Host smart-7664aa46-cfc5-470e-950c-8729d43ef830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276675803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2276675803
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2314511264
Short name T643
Test name
Test status
Simulation time 333688329927 ps
CPU time 185.9 seconds
Started Mar 26 12:28:03 PM PDT 24
Finished Mar 26 12:31:09 PM PDT 24
Peak memory 201796 kb
Host smart-fdfa0c0b-63da-4422-9486-694a35ac9496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314511264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2314511264
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2572299817
Short name T248
Test name
Test status
Simulation time 346895915729 ps
CPU time 202.4 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:31:46 PM PDT 24
Peak memory 201708 kb
Host smart-9b94427b-c04d-464d-b90e-384b16f40aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572299817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2572299817
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3024306062
Short name T101
Test name
Test status
Simulation time 166496804423 ps
CPU time 421.02 seconds
Started Mar 26 12:27:58 PM PDT 24
Finished Mar 26 12:34:59 PM PDT 24
Peak memory 201820 kb
Host smart-ec1667de-d587-411d-844c-582e227493e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024306062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3024306062
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2186673970
Short name T590
Test name
Test status
Simulation time 324652724128 ps
CPU time 725.95 seconds
Started Mar 26 12:29:35 PM PDT 24
Finished Mar 26 12:41:41 PM PDT 24
Peak memory 201456 kb
Host smart-df328740-f96c-41c8-8c15-7a09b369ede3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186673970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2186673970
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.273864832
Short name T371
Test name
Test status
Simulation time 490525796692 ps
CPU time 269.81 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:32:43 PM PDT 24
Peak memory 201824 kb
Host smart-46027583-50ac-4bd7-be27-353fa9ec1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273864832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.273864832
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.497081731
Short name T429
Test name
Test status
Simulation time 165798183227 ps
CPU time 390.12 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:34:43 PM PDT 24
Peak memory 201764 kb
Host smart-3f2a02dd-8f01-4482-8536-054909869c2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=497081731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.497081731
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4169391240
Short name T418
Test name
Test status
Simulation time 603724268192 ps
CPU time 1356.08 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:50:51 PM PDT 24
Peak memory 201728 kb
Host smart-77f50dd7-cb6a-4790-8f27-a20b2b2c9cfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169391240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4169391240
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1952472010
Short name T378
Test name
Test status
Simulation time 91383728784 ps
CPU time 379.8 seconds
Started Mar 26 12:28:03 PM PDT 24
Finished Mar 26 12:34:23 PM PDT 24
Peak memory 202048 kb
Host smart-6bb5ff2d-666b-46cd-897b-a50da360c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952472010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1952472010
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3944324324
Short name T154
Test name
Test status
Simulation time 24737778476 ps
CPU time 58.06 seconds
Started Mar 26 12:28:01 PM PDT 24
Finished Mar 26 12:29:00 PM PDT 24
Peak memory 201544 kb
Host smart-feef43d1-af38-4ae5-ac17-c4e1863691f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944324324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3944324324
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3353423287
Short name T478
Test name
Test status
Simulation time 4321087321 ps
CPU time 3.36 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:19 PM PDT 24
Peak memory 201504 kb
Host smart-75742cb1-279e-4403-9304-eecf5abcfc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353423287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3353423287
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.270323576
Short name T465
Test name
Test status
Simulation time 6101650217 ps
CPU time 7.35 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:24 PM PDT 24
Peak memory 201544 kb
Host smart-6155a914-6b7b-4fe4-967c-2f5b6ad44c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270323576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.270323576
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1882974149
Short name T170
Test name
Test status
Simulation time 683468075422 ps
CPU time 412.51 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:35:06 PM PDT 24
Peak memory 201808 kb
Host smart-d1b23628-278c-41b3-aaee-17578a892c04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882974149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1882974149
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1182448457
Short name T648
Test name
Test status
Simulation time 376316716 ps
CPU time 1.05 seconds
Started Mar 26 12:28:11 PM PDT 24
Finished Mar 26 12:28:12 PM PDT 24
Peak memory 201440 kb
Host smart-6b8e20a2-a3f2-45cd-a404-3088335411a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182448457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1182448457
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2410447879
Short name T32
Test name
Test status
Simulation time 189673494041 ps
CPU time 418.59 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:35:12 PM PDT 24
Peak memory 201868 kb
Host smart-d3189d60-b0d5-4788-ae47-e860424d9ba3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410447879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2410447879
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2120083845
Short name T318
Test name
Test status
Simulation time 336452664975 ps
CPU time 444.77 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:35:45 PM PDT 24
Peak memory 201764 kb
Host smart-330ed2cc-4c6f-4cb0-b410-7f6c290c999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120083845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2120083845
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2326183762
Short name T166
Test name
Test status
Simulation time 331251753221 ps
CPU time 189.09 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:31:29 PM PDT 24
Peak memory 201728 kb
Host smart-9821f7f4-8e28-47e3-9af2-9da3e33926ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326183762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2326183762
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4273827323
Short name T683
Test name
Test status
Simulation time 162524671380 ps
CPU time 95.58 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 201832 kb
Host smart-acc80e89-338d-4d96-a57d-ca511164ca66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273827323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4273827323
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3721370806
Short name T540
Test name
Test status
Simulation time 162832698118 ps
CPU time 357.49 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:34:16 PM PDT 24
Peak memory 201680 kb
Host smart-70d3c7c9-986a-4a33-a00a-b990c83d755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721370806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3721370806
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1006451043
Short name T490
Test name
Test status
Simulation time 166369658001 ps
CPU time 41.68 seconds
Started Mar 26 12:27:59 PM PDT 24
Finished Mar 26 12:28:41 PM PDT 24
Peak memory 201812 kb
Host smart-a510d74d-858b-4b9c-b93a-c8fb523df3fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006451043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1006451043
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1928236326
Short name T496
Test name
Test status
Simulation time 414433337555 ps
CPU time 63.93 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:29:19 PM PDT 24
Peak memory 201684 kb
Host smart-30daee79-01dd-4009-8cd6-cbe034d17c3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928236326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1928236326
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3076785383
Short name T446
Test name
Test status
Simulation time 79068325786 ps
CPU time 428.42 seconds
Started Mar 26 12:27:57 PM PDT 24
Finished Mar 26 12:35:06 PM PDT 24
Peak memory 202056 kb
Host smart-adec7657-65f6-4160-966b-a9e3164dca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076785383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3076785383
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.483000613
Short name T647
Test name
Test status
Simulation time 43747949820 ps
CPU time 47.99 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:29:03 PM PDT 24
Peak memory 201304 kb
Host smart-61650a6b-6da3-41da-aa7f-fdbfa987c70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483000613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.483000613
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3914976615
Short name T417
Test name
Test status
Simulation time 4271317617 ps
CPU time 5.96 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:28:27 PM PDT 24
Peak memory 201300 kb
Host smart-2dc95d6d-4076-45e4-8bbd-f489bff7aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914976615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3914976615
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2906526805
Short name T105
Test name
Test status
Simulation time 5988514644 ps
CPU time 15.39 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:28:32 PM PDT 24
Peak memory 201548 kb
Host smart-fbebeb3d-1694-4ef6-aadd-4631c8f05c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906526805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2906526805
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2065743625
Short name T302
Test name
Test status
Simulation time 322198477470 ps
CPU time 1068.52 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:46:09 PM PDT 24
Peak memory 210220 kb
Host smart-7c55231e-0f95-4c78-babd-d61afcd2dbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065743625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2065743625
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.99494103
Short name T22
Test name
Test status
Simulation time 88393429237 ps
CPU time 47.6 seconds
Started Mar 26 12:28:09 PM PDT 24
Finished Mar 26 12:28:57 PM PDT 24
Peak memory 201800 kb
Host smart-a7785f5d-d498-4703-8a0e-3fb2f0a411a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99494103 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.99494103
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.518748328
Short name T549
Test name
Test status
Simulation time 493371948 ps
CPU time 1.82 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:28:17 PM PDT 24
Peak memory 201384 kb
Host smart-dcffc602-9ff3-439e-942b-b348f35e6aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518748328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.518748328
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.567272746
Short name T268
Test name
Test status
Simulation time 343731968381 ps
CPU time 822.3 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:41:57 PM PDT 24
Peak memory 201720 kb
Host smart-8f9a95f5-c9d8-49a0-8767-dcd9bd4d8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567272746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.567272746
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1865431719
Short name T708
Test name
Test status
Simulation time 162149228941 ps
CPU time 404.23 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:35:01 PM PDT 24
Peak memory 201776 kb
Host smart-1ef8fe67-f787-4539-b402-bc282bac6a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865431719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1865431719
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.703656182
Short name T783
Test name
Test status
Simulation time 169094738822 ps
CPU time 361.42 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:34:16 PM PDT 24
Peak memory 201744 kb
Host smart-42885a56-6ef8-4f49-97b3-0da44c2c7f08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=703656182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.703656182
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3706905018
Short name T278
Test name
Test status
Simulation time 165441363607 ps
CPU time 50.12 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:29:09 PM PDT 24
Peak memory 201524 kb
Host smart-919a66da-457f-40fe-aa9d-0300bce9c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706905018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3706905018
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3162773648
Short name T457
Test name
Test status
Simulation time 166644663314 ps
CPU time 74.62 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:29:35 PM PDT 24
Peak memory 201692 kb
Host smart-73207adf-540f-4093-bad0-86e81c3be4e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162773648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3162773648
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2647675567
Short name T622
Test name
Test status
Simulation time 406559514677 ps
CPU time 241.89 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:32:25 PM PDT 24
Peak memory 201792 kb
Host smart-f763d51c-d4e8-4366-b9ec-93a58f29d972
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647675567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2647675567
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4200790606
Short name T780
Test name
Test status
Simulation time 123630905478 ps
CPU time 601.3 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:38:27 PM PDT 24
Peak memory 201996 kb
Host smart-3aab6065-ea62-43a0-82f9-5509e15f6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200790606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4200790606
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3177629219
Short name T474
Test name
Test status
Simulation time 28949449585 ps
CPU time 63.63 seconds
Started Mar 26 12:28:08 PM PDT 24
Finished Mar 26 12:29:11 PM PDT 24
Peak memory 201524 kb
Host smart-34c246af-9b19-4026-a4ed-c07328e23b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177629219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3177629219
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3452858667
Short name T720
Test name
Test status
Simulation time 3403995729 ps
CPU time 4.75 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:20 PM PDT 24
Peak memory 201540 kb
Host smart-dbeef46e-c51a-4787-9dca-173859da7d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452858667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3452858667
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.30345813
Short name T396
Test name
Test status
Simulation time 5930403597 ps
CPU time 14.96 seconds
Started Mar 26 12:28:24 PM PDT 24
Finished Mar 26 12:28:39 PM PDT 24
Peak memory 201636 kb
Host smart-3b97f696-1931-4ad3-8830-564359c4a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30345813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.30345813
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2081472880
Short name T224
Test name
Test status
Simulation time 335465422946 ps
CPU time 202.59 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:31:36 PM PDT 24
Peak memory 201700 kb
Host smart-8c88f1d0-9d89-46b9-ad7b-dcfe3f9d5674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081472880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2081472880
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3102091593
Short name T798
Test name
Test status
Simulation time 282126089184 ps
CPU time 194.81 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:31:30 PM PDT 24
Peak memory 210344 kb
Host smart-374db307-d5dd-469d-931b-4310ec33a04e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102091593 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3102091593
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.4078519998
Short name T551
Test name
Test status
Simulation time 479553897 ps
CPU time 1.75 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:28:17 PM PDT 24
Peak memory 201440 kb
Host smart-6d89b875-9753-42cb-95d9-2687c7997a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078519998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.4078519998
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2321910043
Short name T225
Test name
Test status
Simulation time 521173457203 ps
CPU time 128.92 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:30:28 PM PDT 24
Peak memory 201656 kb
Host smart-474e89df-84cf-419c-bc60-abdee3598c73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321910043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2321910043
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.288835883
Short name T203
Test name
Test status
Simulation time 340306769776 ps
CPU time 227.36 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:32:09 PM PDT 24
Peak memory 201720 kb
Host smart-082cb415-1bbb-4e62-8843-370bea662ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288835883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.288835883
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2286373155
Short name T570
Test name
Test status
Simulation time 331231373498 ps
CPU time 375.93 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:34:29 PM PDT 24
Peak memory 202072 kb
Host smart-1661dcfd-15ba-4221-81c1-f85520c5218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286373155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2286373155
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4188758202
Short name T412
Test name
Test status
Simulation time 166392436378 ps
CPU time 194.34 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:31:24 PM PDT 24
Peak memory 201760 kb
Host smart-e4e99b76-706a-48bd-a98c-50de0a1b9bb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188758202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4188758202
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2658075349
Short name T750
Test name
Test status
Simulation time 324344458796 ps
CPU time 202.78 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:31:39 PM PDT 24
Peak memory 201720 kb
Host smart-3fc71dd1-50a9-41b8-b282-3e4e7c87dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658075349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2658075349
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3852107299
Short name T410
Test name
Test status
Simulation time 323946208169 ps
CPU time 197.86 seconds
Started Mar 26 12:27:58 PM PDT 24
Finished Mar 26 12:31:16 PM PDT 24
Peak memory 201692 kb
Host smart-40fd4f2f-27a3-491d-88cf-c51239171978
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852107299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3852107299
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.278651850
Short name T721
Test name
Test status
Simulation time 520607635359 ps
CPU time 307.47 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:33:28 PM PDT 24
Peak memory 201716 kb
Host smart-f0091170-145d-4741-a2af-9b9614c36113
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278651850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.278651850
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2198112950
Short name T799
Test name
Test status
Simulation time 415129986215 ps
CPU time 262.64 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:32:36 PM PDT 24
Peak memory 201724 kb
Host smart-fcdd5149-c7ab-4b9b-8891-c8b94533cb2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198112950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2198112950
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3803765900
Short name T485
Test name
Test status
Simulation time 122706121869 ps
CPU time 497.15 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:36:37 PM PDT 24
Peak memory 202100 kb
Host smart-4726de47-011a-4947-8bc8-44d70a71f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803765900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3803765900
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2640751022
Short name T395
Test name
Test status
Simulation time 22929704355 ps
CPU time 13.25 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:28:37 PM PDT 24
Peak memory 201468 kb
Host smart-0a8ac9c2-f968-4ef9-a70c-a9c2c9f5bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640751022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2640751022
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1591014888
Short name T511
Test name
Test status
Simulation time 4765757280 ps
CPU time 5.73 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:28:26 PM PDT 24
Peak memory 201536 kb
Host smart-d35276ff-5ebc-492d-a0e7-0d25d63575c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591014888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1591014888
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1303011042
Short name T765
Test name
Test status
Simulation time 6018457211 ps
CPU time 8.35 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:28 PM PDT 24
Peak memory 201524 kb
Host smart-75369bd6-397a-4c1e-b85a-9bb1715faf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303011042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1303011042
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.26906456
Short name T252
Test name
Test status
Simulation time 543677247097 ps
CPU time 1187.4 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:48:07 PM PDT 24
Peak memory 201828 kb
Host smart-5eccf7c4-6864-43f8-8d4b-f08e6545a398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26906456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.26906456
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3837566679
Short name T14
Test name
Test status
Simulation time 397116211 ps
CPU time 1.47 seconds
Started Mar 26 12:28:27 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 201432 kb
Host smart-ee09e4e6-c510-41bb-8ec1-65aa6ca47c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837566679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3837566679
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3086546026
Short name T314
Test name
Test status
Simulation time 492948729273 ps
CPU time 1059.41 seconds
Started Mar 26 12:28:15 PM PDT 24
Finished Mar 26 12:45:55 PM PDT 24
Peak memory 201776 kb
Host smart-6dba2a24-72d4-44e7-ac2e-a63f1eae3e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086546026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3086546026
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2135052419
Short name T662
Test name
Test status
Simulation time 329999541593 ps
CPU time 194.92 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:31:38 PM PDT 24
Peak memory 201660 kb
Host smart-f09c6371-55c1-45a0-8de8-93bff65a8a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135052419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2135052419
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2756146971
Short name T616
Test name
Test status
Simulation time 324580481882 ps
CPU time 181.48 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:31:21 PM PDT 24
Peak memory 201708 kb
Host smart-997c631a-b1ec-4282-9b3b-9b18e1711423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756146971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2756146971
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2747520393
Short name T568
Test name
Test status
Simulation time 325267925150 ps
CPU time 122.75 seconds
Started Mar 26 12:28:26 PM PDT 24
Finished Mar 26 12:30:29 PM PDT 24
Peak memory 201704 kb
Host smart-e306194a-7e43-4575-a4b2-635e5ffa73f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747520393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2747520393
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.280888328
Short name T800
Test name
Test status
Simulation time 184681685063 ps
CPU time 429.36 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:35:28 PM PDT 24
Peak memory 201844 kb
Host smart-e3506778-b85b-436c-bde5-93fc049d4ad0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280888328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.280888328
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4039806979
Short name T602
Test name
Test status
Simulation time 188851870953 ps
CPU time 111.59 seconds
Started Mar 26 12:28:14 PM PDT 24
Finished Mar 26 12:30:06 PM PDT 24
Peak memory 201496 kb
Host smart-c5e25dc5-2483-4a31-8991-7d1b233aee98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039806979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4039806979
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2493968807
Short name T681
Test name
Test status
Simulation time 85894821651 ps
CPU time 357.26 seconds
Started Mar 26 12:28:18 PM PDT 24
Finished Mar 26 12:34:15 PM PDT 24
Peak memory 202024 kb
Host smart-a860e6bf-cb87-4d31-8015-1262b6edf7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493968807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2493968807
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2880518012
Short name T530
Test name
Test status
Simulation time 31896786507 ps
CPU time 40.41 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:29:00 PM PDT 24
Peak memory 201552 kb
Host smart-c1c16812-ba87-4655-b283-35d9ed1e5199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880518012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2880518012
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3259474111
Short name T730
Test name
Test status
Simulation time 5242841849 ps
CPU time 3.6 seconds
Started Mar 26 12:28:13 PM PDT 24
Finished Mar 26 12:28:18 PM PDT 24
Peak memory 201532 kb
Host smart-356657eb-05dc-46c3-820a-d70f7f21b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259474111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3259474111
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1810218461
Short name T576
Test name
Test status
Simulation time 5763578423 ps
CPU time 7.31 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:26 PM PDT 24
Peak memory 201568 kb
Host smart-11e2b825-d1a5-47b3-8542-605a102b1b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810218461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1810218461
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1835078035
Short name T572
Test name
Test status
Simulation time 241890962738 ps
CPU time 134.28 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:30:35 PM PDT 24
Peak memory 201784 kb
Host smart-afc822cd-4ca7-47e9-a3d3-5f6afed2609c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835078035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1835078035
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2129507569
Short name T689
Test name
Test status
Simulation time 318507169 ps
CPU time 0.98 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:28:23 PM PDT 24
Peak memory 201432 kb
Host smart-965e06b5-6fb9-431f-b366-65b79c10cbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129507569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2129507569
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3569305189
Short name T659
Test name
Test status
Simulation time 162605832662 ps
CPU time 265.72 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:32:48 PM PDT 24
Peak memory 201796 kb
Host smart-a30ff7a7-95fe-46e2-9b90-643602129b22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569305189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3569305189
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2780446815
Short name T711
Test name
Test status
Simulation time 494598977410 ps
CPU time 1127.11 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:47:09 PM PDT 24
Peak memory 202156 kb
Host smart-ec8e6772-b36b-49bd-878b-e250542331c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780446815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2780446815
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1631940598
Short name T199
Test name
Test status
Simulation time 496950557871 ps
CPU time 603.04 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:38:26 PM PDT 24
Peak memory 201804 kb
Host smart-9b94971f-b507-448c-b404-d357c8261866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631940598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1631940598
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1613546128
Short name T595
Test name
Test status
Simulation time 162783780277 ps
CPU time 102.28 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:30:10 PM PDT 24
Peak memory 201728 kb
Host smart-1278b516-439c-4680-9617-d24cd2e59536
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613546128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1613546128
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.950875651
Short name T1
Test name
Test status
Simulation time 486415005089 ps
CPU time 571.72 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:37:52 PM PDT 24
Peak memory 201812 kb
Host smart-b27c0256-ac5d-4d90-9f55-3a1f244cc8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950875651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.950875651
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1065904057
Short name T528
Test name
Test status
Simulation time 497237477871 ps
CPU time 590.99 seconds
Started Mar 26 12:28:16 PM PDT 24
Finished Mar 26 12:38:07 PM PDT 24
Peak memory 201744 kb
Host smart-f1f4e231-bc0e-4228-aaba-b2959d550a18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065904057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1065904057
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2529087697
Short name T294
Test name
Test status
Simulation time 396088688945 ps
CPU time 904.49 seconds
Started Mar 26 12:28:20 PM PDT 24
Finished Mar 26 12:43:24 PM PDT 24
Peak memory 201780 kb
Host smart-45459042-3a25-4186-a1a8-372615add9a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529087697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2529087697
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.776954313
Short name T684
Test name
Test status
Simulation time 198670539663 ps
CPU time 378.46 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:34:40 PM PDT 24
Peak memory 201692 kb
Host smart-217137c1-6c0f-42be-9112-62585a3dec0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776954313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.776954313
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4021326162
Short name T212
Test name
Test status
Simulation time 107101019030 ps
CPU time 374.4 seconds
Started Mar 26 12:28:28 PM PDT 24
Finished Mar 26 12:34:43 PM PDT 24
Peak memory 202124 kb
Host smart-08a171ae-b69a-4085-b18d-6b6300dcc87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021326162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4021326162
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1387407845
Short name T562
Test name
Test status
Simulation time 24650673360 ps
CPU time 9.72 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 201512 kb
Host smart-e94642e7-696a-48bc-a0d0-e2bfd202d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387407845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1387407845
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3264550098
Short name T494
Test name
Test status
Simulation time 5051305817 ps
CPU time 12.42 seconds
Started Mar 26 12:28:25 PM PDT 24
Finished Mar 26 12:28:38 PM PDT 24
Peak memory 201084 kb
Host smart-19e818cb-9907-47f6-9546-259a43b9d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264550098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3264550098
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1043183250
Short name T687
Test name
Test status
Simulation time 5678754367 ps
CPU time 15.86 seconds
Started Mar 26 12:28:24 PM PDT 24
Finished Mar 26 12:28:40 PM PDT 24
Peak memory 201504 kb
Host smart-38820ffc-7ff7-4f2a-bbf1-3dc57934b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043183250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1043183250
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3927589357
Short name T585
Test name
Test status
Simulation time 165902030441 ps
CPU time 288.63 seconds
Started Mar 26 12:28:21 PM PDT 24
Finished Mar 26 12:33:10 PM PDT 24
Peak memory 201708 kb
Host smart-81999f34-2446-4562-92c5-688c665614aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927589357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3927589357
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3259373340
Short name T280
Test name
Test status
Simulation time 151658742747 ps
CPU time 146.33 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:30:49 PM PDT 24
Peak memory 210468 kb
Host smart-1d411f97-2122-4bfa-a8b7-2299eb96932e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259373340 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3259373340
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3352718868
Short name T517
Test name
Test status
Simulation time 536489226 ps
CPU time 0.93 seconds
Started Mar 26 12:26:27 PM PDT 24
Finished Mar 26 12:26:28 PM PDT 24
Peak memory 200980 kb
Host smart-8abac4bb-c179-4572-8207-628b9d326254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352718868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3352718868
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1044965911
Short name T147
Test name
Test status
Simulation time 541682681845 ps
CPU time 721.89 seconds
Started Mar 26 12:27:12 PM PDT 24
Finished Mar 26 12:39:14 PM PDT 24
Peak memory 201752 kb
Host smart-12035c53-55e4-4386-b48d-4658b1e7a2d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044965911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1044965911
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1426076458
Short name T724
Test name
Test status
Simulation time 206557927560 ps
CPU time 231.79 seconds
Started Mar 26 12:27:32 PM PDT 24
Finished Mar 26 12:31:25 PM PDT 24
Peak memory 200140 kb
Host smart-a94b315c-c847-4606-9e2f-47f57dec30ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426076458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1426076458
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1542296190
Short name T365
Test name
Test status
Simulation time 330457392179 ps
CPU time 222.84 seconds
Started Mar 26 12:26:21 PM PDT 24
Finished Mar 26 12:30:04 PM PDT 24
Peak memory 201716 kb
Host smart-2d9d3201-160e-4450-b264-56035eca7d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542296190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1542296190
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1350978413
Short name T663
Test name
Test status
Simulation time 164074475660 ps
CPU time 410.03 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:35:09 PM PDT 24
Peak memory 201704 kb
Host smart-d0167bf7-b7bd-4132-ba62-9bd6afa81f20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350978413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1350978413
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.185047542
Short name T615
Test name
Test status
Simulation time 161811270130 ps
CPU time 368.4 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:32:30 PM PDT 24
Peak memory 201716 kb
Host smart-a8d17f22-e95c-486d-a18f-c488502a95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185047542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.185047542
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2566924004
Short name T116
Test name
Test status
Simulation time 328559091919 ps
CPU time 749.18 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:38:54 PM PDT 24
Peak memory 201804 kb
Host smart-49679e1b-bd29-4e95-be69-3125c06bb50f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566924004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2566924004
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2160049628
Short name T521
Test name
Test status
Simulation time 353627508543 ps
CPU time 350.04 seconds
Started Mar 26 12:26:25 PM PDT 24
Finished Mar 26 12:32:15 PM PDT 24
Peak memory 201788 kb
Host smart-758d7ae7-3b14-4cb1-9fd8-c9be8f602ae6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160049628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2160049628
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2788410664
Short name T601
Test name
Test status
Simulation time 413413452717 ps
CPU time 935.06 seconds
Started Mar 26 12:26:27 PM PDT 24
Finished Mar 26 12:42:02 PM PDT 24
Peak memory 201352 kb
Host smart-089d7e29-807d-4894-ad58-a2b0fe62f8a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788410664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2788410664
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3527348444
Short name T695
Test name
Test status
Simulation time 117740383705 ps
CPU time 414.57 seconds
Started Mar 26 12:28:22 PM PDT 24
Finished Mar 26 12:35:17 PM PDT 24
Peak memory 202104 kb
Host smart-45d74ae4-2caa-4767-9c33-e3f224701f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527348444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3527348444
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3611852312
Short name T700
Test name
Test status
Simulation time 30255045708 ps
CPU time 68.54 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:27:33 PM PDT 24
Peak memory 201484 kb
Host smart-be3e48ef-6f1d-47db-a0b9-6cf1298b8007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611852312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3611852312
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1443282285
Short name T430
Test name
Test status
Simulation time 2797912425 ps
CPU time 6.67 seconds
Started Mar 26 12:26:27 PM PDT 24
Finished Mar 26 12:26:34 PM PDT 24
Peak memory 201528 kb
Host smart-d2f1ccb0-efad-4868-bb09-d3884e5f9b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443282285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1443282285
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2118674758
Short name T633
Test name
Test status
Simulation time 5891216744 ps
CPU time 8.05 seconds
Started Mar 26 12:26:43 PM PDT 24
Finished Mar 26 12:26:51 PM PDT 24
Peak memory 201540 kb
Host smart-0b0b9126-9305-47e0-bd33-65c2f5d7f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118674758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2118674758
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3058494646
Short name T731
Test name
Test status
Simulation time 338967486808 ps
CPU time 195.74 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:30:00 PM PDT 24
Peak memory 201724 kb
Host smart-04e49a65-6b16-4bbc-9d9a-050af645d3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058494646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3058494646
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.442445837
Short name T226
Test name
Test status
Simulation time 350625361509 ps
CPU time 196.75 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:30:02 PM PDT 24
Peak memory 210332 kb
Host smart-bae42fe5-5068-4f56-891b-7d5703df2b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442445837 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.442445837
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2392769253
Short name T192
Test name
Test status
Simulation time 344127980 ps
CPU time 0.77 seconds
Started Mar 26 12:27:59 PM PDT 24
Finished Mar 26 12:27:59 PM PDT 24
Peak memory 201208 kb
Host smart-e9c1b8ba-fb4f-4f76-84ab-3963c7502c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392769253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2392769253
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3565876251
Short name T646
Test name
Test status
Simulation time 163886350020 ps
CPU time 420.25 seconds
Started Mar 26 12:27:51 PM PDT 24
Finished Mar 26 12:34:52 PM PDT 24
Peak memory 201508 kb
Host smart-9f9014ee-acb4-4dd5-b66d-c74510df6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565876251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3565876251
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.797063956
Short name T183
Test name
Test status
Simulation time 492569042771 ps
CPU time 1180.9 seconds
Started Mar 26 12:26:53 PM PDT 24
Finished Mar 26 12:46:34 PM PDT 24
Peak memory 201688 kb
Host smart-9f95e483-c78c-46b4-be9e-8c9a7993a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797063956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.797063956
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2727278122
Short name T109
Test name
Test status
Simulation time 160384934457 ps
CPU time 101.05 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:28:26 PM PDT 24
Peak memory 201704 kb
Host smart-19fe612d-39b0-436d-a8bf-4772540ca8f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727278122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2727278122
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3484699157
Short name T752
Test name
Test status
Simulation time 334358345869 ps
CPU time 203.4 seconds
Started Mar 26 12:27:37 PM PDT 24
Finished Mar 26 12:31:01 PM PDT 24
Peak memory 201660 kb
Host smart-eaf0fb12-3e8d-4e2a-a81e-1c357b632cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484699157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3484699157
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3191948473
Short name T27
Test name
Test status
Simulation time 480903715106 ps
CPU time 1099.46 seconds
Started Mar 26 12:26:16 PM PDT 24
Finished Mar 26 12:44:36 PM PDT 24
Peak memory 201652 kb
Host smart-f1251192-871c-460f-83a2-b222655e1938
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191948473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3191948473
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1707000142
Short name T190
Test name
Test status
Simulation time 173992661901 ps
CPU time 101.16 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:28:26 PM PDT 24
Peak memory 201812 kb
Host smart-55397ae4-da3d-4086-83ea-9013eeb5ba47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707000142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1707000142
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3596430703
Short name T475
Test name
Test status
Simulation time 383678815630 ps
CPU time 868.06 seconds
Started Mar 26 12:26:22 PM PDT 24
Finished Mar 26 12:40:51 PM PDT 24
Peak memory 201776 kb
Host smart-389fdf1b-e782-4062-88ca-c18558bd1842
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596430703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3596430703
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.881908236
Short name T55
Test name
Test status
Simulation time 86645540794 ps
CPU time 470.6 seconds
Started Mar 26 12:26:34 PM PDT 24
Finished Mar 26 12:34:25 PM PDT 24
Peak memory 202188 kb
Host smart-bc11ef25-cb7d-48eb-8237-2ef3c406a5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881908236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.881908236
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2804857287
Short name T672
Test name
Test status
Simulation time 37797074063 ps
CPU time 82.19 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:28:02 PM PDT 24
Peak memory 201508 kb
Host smart-e6d897e0-1319-4219-abfb-ce02a26d30b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804857287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2804857287
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1659507154
Short name T675
Test name
Test status
Simulation time 3689822380 ps
CPU time 9.52 seconds
Started Mar 26 12:26:27 PM PDT 24
Finished Mar 26 12:26:37 PM PDT 24
Peak memory 201500 kb
Host smart-0f26ee80-f47a-489a-8fb2-2906500d02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659507154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1659507154
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2123479526
Short name T682
Test name
Test status
Simulation time 5817480683 ps
CPU time 5.04 seconds
Started Mar 26 12:26:19 PM PDT 24
Finished Mar 26 12:26:24 PM PDT 24
Peak memory 201304 kb
Host smart-31b72c3a-4d61-465d-8551-8b8aff868601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123479526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2123479526
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.664810813
Short name T618
Test name
Test status
Simulation time 1030468930504 ps
CPU time 1456.52 seconds
Started Mar 26 12:28:19 PM PDT 24
Finished Mar 26 12:52:36 PM PDT 24
Peak memory 210220 kb
Host smart-a8344056-7504-4241-b01f-ef9e4333334f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664810813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.664810813
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2070646114
Short name T629
Test name
Test status
Simulation time 627805953377 ps
CPU time 516.94 seconds
Started Mar 26 12:26:27 PM PDT 24
Finished Mar 26 12:35:04 PM PDT 24
Peak memory 210400 kb
Host smart-00da57be-ce92-4d35-9361-551d34a21285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070646114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2070646114
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2465976878
Short name T497
Test name
Test status
Simulation time 404175919 ps
CPU time 1.47 seconds
Started Mar 26 12:27:05 PM PDT 24
Finished Mar 26 12:27:07 PM PDT 24
Peak memory 201388 kb
Host smart-c66b1522-ff65-45bb-87e0-e75dd30abb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465976878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2465976878
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3099811712
Short name T336
Test name
Test status
Simulation time 182518106630 ps
CPU time 427.91 seconds
Started Mar 26 12:26:37 PM PDT 24
Finished Mar 26 12:33:45 PM PDT 24
Peak memory 201732 kb
Host smart-53c6ba17-7b6e-4288-a255-49f22aac39cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099811712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3099811712
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2216495680
Short name T308
Test name
Test status
Simulation time 490797580890 ps
CPU time 1215.32 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:48:32 PM PDT 24
Peak memory 201728 kb
Host smart-3d270b5f-87f4-48f3-9123-d0151359e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216495680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2216495680
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3079346295
Short name T461
Test name
Test status
Simulation time 164059457101 ps
CPU time 100.36 seconds
Started Mar 26 12:27:44 PM PDT 24
Finished Mar 26 12:29:25 PM PDT 24
Peak memory 200652 kb
Host smart-4d5d39af-3f7b-48e9-b03a-e17e521004fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079346295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3079346295
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3927858981
Short name T198
Test name
Test status
Simulation time 324777833211 ps
CPU time 53.22 seconds
Started Mar 26 12:27:43 PM PDT 24
Finished Mar 26 12:28:37 PM PDT 24
Peak memory 201660 kb
Host smart-30639a52-b761-4c02-94a5-bfd60c003190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927858981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3927858981
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2391938858
Short name T455
Test name
Test status
Simulation time 492387434516 ps
CPU time 582.56 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:37:37 PM PDT 24
Peak memory 201500 kb
Host smart-81964e98-0134-4bf6-afd4-1024777e79b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391938858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2391938858
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3130785594
Short name T619
Test name
Test status
Simulation time 197642701236 ps
CPU time 227.23 seconds
Started Mar 26 12:26:45 PM PDT 24
Finished Mar 26 12:30:32 PM PDT 24
Peak memory 201932 kb
Host smart-6d3ad13c-5db7-4f40-ac2f-fda14cbe3dc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130785594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3130785594
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2411903161
Short name T620
Test name
Test status
Simulation time 583692203632 ps
CPU time 677.95 seconds
Started Mar 26 12:27:04 PM PDT 24
Finished Mar 26 12:38:22 PM PDT 24
Peak memory 201836 kb
Host smart-7b17e8be-a7cf-437d-9979-e3a88d84e7a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411903161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2411903161
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2522231822
Short name T178
Test name
Test status
Simulation time 125672281103 ps
CPU time 542.29 seconds
Started Mar 26 12:27:51 PM PDT 24
Finished Mar 26 12:36:54 PM PDT 24
Peak memory 202072 kb
Host smart-f6691331-478b-4e8c-ac63-e6e0c61de168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522231822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2522231822
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.769966334
Short name T507
Test name
Test status
Simulation time 25824488771 ps
CPU time 30.65 seconds
Started Mar 26 12:27:42 PM PDT 24
Finished Mar 26 12:28:13 PM PDT 24
Peak memory 201300 kb
Host smart-ed3d57bd-515e-4ad6-9e5a-c6c551b709a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769966334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.769966334
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3742872848
Short name T463
Test name
Test status
Simulation time 3218566682 ps
CPU time 7.58 seconds
Started Mar 26 12:26:34 PM PDT 24
Finished Mar 26 12:26:42 PM PDT 24
Peak memory 201552 kb
Host smart-ecacc207-a568-46b5-b9b6-af435560c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742872848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3742872848
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3674948395
Short name T472
Test name
Test status
Simulation time 5752116269 ps
CPU time 4.02 seconds
Started Mar 26 12:26:40 PM PDT 24
Finished Mar 26 12:26:44 PM PDT 24
Peak memory 201516 kb
Host smart-07a27bb4-b1d3-4846-99e0-d16972117310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674948395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3674948395
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.123497173
Short name T319
Test name
Test status
Simulation time 52648411345 ps
CPU time 191.02 seconds
Started Mar 26 12:27:03 PM PDT 24
Finished Mar 26 12:30:15 PM PDT 24
Peak memory 210372 kb
Host smart-7306f5f5-10fd-4eb4-8da0-f4456e651a37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123497173 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.123497173
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3906809800
Short name T401
Test name
Test status
Simulation time 516576474 ps
CPU time 1.78 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:26:46 PM PDT 24
Peak memory 201380 kb
Host smart-f75090c0-de8b-42c7-bafb-5da84284621f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906809800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3906809800
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3768371458
Short name T357
Test name
Test status
Simulation time 181400540814 ps
CPU time 114.28 seconds
Started Mar 26 12:28:17 PM PDT 24
Finished Mar 26 12:30:11 PM PDT 24
Peak memory 201676 kb
Host smart-68c1118d-729e-4e60-bcb4-c30d8b39f627
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768371458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3768371458
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3831633872
Short name T488
Test name
Test status
Simulation time 329609348873 ps
CPU time 801.04 seconds
Started Mar 26 12:27:29 PM PDT 24
Finished Mar 26 12:40:50 PM PDT 24
Peak memory 201844 kb
Host smart-f39a1a7c-3c7e-4ea6-9750-e643e0997887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831633872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3831633872
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.761993237
Short name T579
Test name
Test status
Simulation time 168110812923 ps
CPU time 81.76 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:27:46 PM PDT 24
Peak memory 201916 kb
Host smart-3218aed9-5782-47a3-91ea-9714662f4f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761993237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.761993237
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3274910678
Short name T669
Test name
Test status
Simulation time 165543701312 ps
CPU time 180.84 seconds
Started Mar 26 12:26:26 PM PDT 24
Finished Mar 26 12:29:27 PM PDT 24
Peak memory 201676 kb
Host smart-b2a57ac7-ceac-4fa3-b45e-654a526f0029
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274910678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3274910678
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2032777091
Short name T795
Test name
Test status
Simulation time 161697173353 ps
CPU time 175.53 seconds
Started Mar 26 12:26:28 PM PDT 24
Finished Mar 26 12:29:23 PM PDT 24
Peak memory 201772 kb
Host smart-ebebc5fa-8264-4fa9-be34-f093176b1261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032777091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2032777091
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1874395575
Short name T755
Test name
Test status
Simulation time 484422516915 ps
CPU time 1064.83 seconds
Started Mar 26 12:27:05 PM PDT 24
Finished Mar 26 12:44:50 PM PDT 24
Peak memory 201768 kb
Host smart-9701fa55-6ee0-4fed-92e4-66e2cb952900
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874395575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1874395575
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.917371471
Short name T586
Test name
Test status
Simulation time 548067781705 ps
CPU time 981.76 seconds
Started Mar 26 12:27:53 PM PDT 24
Finished Mar 26 12:44:15 PM PDT 24
Peak memory 201696 kb
Host smart-b10b7554-3e88-4748-ae67-fa199c36055c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917371471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.917371471
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.720792607
Short name T394
Test name
Test status
Simulation time 215130485613 ps
CPU time 496.93 seconds
Started Mar 26 12:26:59 PM PDT 24
Finished Mar 26 12:35:16 PM PDT 24
Peak memory 201732 kb
Host smart-1cb1c575-4573-49d4-8898-cc941e5e329b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720792607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.720792607
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2205604445
Short name T382
Test name
Test status
Simulation time 81706833244 ps
CPU time 438.3 seconds
Started Mar 26 12:27:51 PM PDT 24
Finished Mar 26 12:35:10 PM PDT 24
Peak memory 201896 kb
Host smart-4f11a151-5d27-43db-9064-af47da5aba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205604445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2205604445
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3873060735
Short name T153
Test name
Test status
Simulation time 23996488294 ps
CPU time 27.86 seconds
Started Mar 26 12:26:50 PM PDT 24
Finished Mar 26 12:27:18 PM PDT 24
Peak memory 201644 kb
Host smart-ca76910c-21f3-4a0c-b3ee-c315b10551ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873060735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3873060735
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1705115246
Short name T623
Test name
Test status
Simulation time 4713600661 ps
CPU time 11.74 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:28:06 PM PDT 24
Peak memory 201324 kb
Host smart-4383efd6-6319-4469-a375-e6a97d64272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705115246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1705115246
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3804833956
Short name T767
Test name
Test status
Simulation time 5984981494 ps
CPU time 4.18 seconds
Started Mar 26 12:26:23 PM PDT 24
Finished Mar 26 12:26:27 PM PDT 24
Peak memory 201652 kb
Host smart-48cc82a2-2fac-42d9-89f7-044c2b01b489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804833956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3804833956
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3351959006
Short name T548
Test name
Test status
Simulation time 164300751794 ps
CPU time 98.96 seconds
Started Mar 26 12:28:10 PM PDT 24
Finished Mar 26 12:29:49 PM PDT 24
Peak memory 201800 kb
Host smart-4130f18d-3385-4155-9f1b-072ab15968aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351959006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3351959006
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3216296642
Short name T757
Test name
Test status
Simulation time 65061917788 ps
CPU time 38.18 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:27:22 PM PDT 24
Peak memory 201924 kb
Host smart-b3b91fb6-6b69-4031-adbb-83cb20d22ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216296642 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3216296642
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.964864075
Short name T419
Test name
Test status
Simulation time 372424024 ps
CPU time 1 seconds
Started Mar 26 12:26:35 PM PDT 24
Finished Mar 26 12:26:36 PM PDT 24
Peak memory 201404 kb
Host smart-cf63cfbd-b25e-4b3b-97a1-5e2efedb660c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964864075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.964864075
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1718699904
Short name T202
Test name
Test status
Simulation time 500388715908 ps
CPU time 105.4 seconds
Started Mar 26 12:26:44 PM PDT 24
Finished Mar 26 12:28:29 PM PDT 24
Peak memory 201724 kb
Host smart-c8cd4f92-01dc-4916-b48f-269d23814718
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718699904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1718699904
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1414776216
Short name T256
Test name
Test status
Simulation time 161195313893 ps
CPU time 347.15 seconds
Started Mar 26 12:27:07 PM PDT 24
Finished Mar 26 12:32:54 PM PDT 24
Peak memory 201720 kb
Host smart-5062ebce-04a6-405a-8f6d-f3df49b2739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414776216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1414776216
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.377730911
Short name T480
Test name
Test status
Simulation time 160138124204 ps
CPU time 96.47 seconds
Started Mar 26 12:26:26 PM PDT 24
Finished Mar 26 12:28:03 PM PDT 24
Peak memory 201832 kb
Host smart-94281cd4-58bc-411a-a461-f2389fd5014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377730911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.377730911
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3111525632
Short name T510
Test name
Test status
Simulation time 331517951446 ps
CPU time 69.59 seconds
Started Mar 26 12:27:48 PM PDT 24
Finished Mar 26 12:28:58 PM PDT 24
Peak memory 201652 kb
Host smart-ea560211-f359-4861-9401-87941d9fad39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111525632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3111525632
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3825256947
Short name T250
Test name
Test status
Simulation time 328079350951 ps
CPU time 196.37 seconds
Started Mar 26 12:27:54 PM PDT 24
Finished Mar 26 12:31:10 PM PDT 24
Peak memory 201564 kb
Host smart-fbd6fc11-f2e8-4ad6-b327-e3c7a085fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825256947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3825256947
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1574760496
Short name T535
Test name
Test status
Simulation time 334046162311 ps
CPU time 795.42 seconds
Started Mar 26 12:28:23 PM PDT 24
Finished Mar 26 12:41:39 PM PDT 24
Peak memory 201820 kb
Host smart-4473896d-cb13-4866-9292-03731e863eef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574760496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1574760496
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1554822525
Short name T697
Test name
Test status
Simulation time 184102799708 ps
CPU time 434 seconds
Started Mar 26 12:27:44 PM PDT 24
Finished Mar 26 12:34:59 PM PDT 24
Peak memory 200804 kb
Host smart-a7bfc0e1-3283-4ae4-a70b-890842b3f9de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554822525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1554822525
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2486160136
Short name T573
Test name
Test status
Simulation time 401691908315 ps
CPU time 431.07 seconds
Started Mar 26 12:27:32 PM PDT 24
Finished Mar 26 12:34:44 PM PDT 24
Peak memory 200056 kb
Host smart-abafcb4a-8862-4d0a-9c35-c9a2fa1fa928
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486160136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2486160136
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3302348048
Short name T651
Test name
Test status
Simulation time 96527274590 ps
CPU time 395.7 seconds
Started Mar 26 12:27:53 PM PDT 24
Finished Mar 26 12:34:29 PM PDT 24
Peak memory 201800 kb
Host smart-bbac6734-5d1d-461a-a6dd-96e0da2f0b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302348048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3302348048
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1660667165
Short name T476
Test name
Test status
Simulation time 42311643807 ps
CPU time 16.96 seconds
Started Mar 26 12:27:40 PM PDT 24
Finished Mar 26 12:27:58 PM PDT 24
Peak memory 200712 kb
Host smart-57fc3c1d-2002-4535-b5b9-1713192a6320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660667165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1660667165
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.147582283
Short name T94
Test name
Test status
Simulation time 5662984051 ps
CPU time 8.44 seconds
Started Mar 26 12:27:51 PM PDT 24
Finished Mar 26 12:28:00 PM PDT 24
Peak memory 201320 kb
Host smart-eb52777d-4744-4183-8e27-513efabad2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147582283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.147582283
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.664714617
Short name T627
Test name
Test status
Simulation time 6032253480 ps
CPU time 4.48 seconds
Started Mar 26 12:27:06 PM PDT 24
Finished Mar 26 12:27:10 PM PDT 24
Peak memory 201552 kb
Host smart-aa260ddb-73c7-4cf1-ab91-7b6b0db96cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664714617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.664714617
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1622376384
Short name T792
Test name
Test status
Simulation time 170343830182 ps
CPU time 62.1 seconds
Started Mar 26 12:27:32 PM PDT 24
Finished Mar 26 12:28:35 PM PDT 24
Peak memory 200616 kb
Host smart-94eceda1-14f0-4824-88ae-4a93b1aab1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622376384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1622376384
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2273632563
Short name T350
Test name
Test status
Simulation time 88852361133 ps
CPU time 229.14 seconds
Started Mar 26 12:27:51 PM PDT 24
Finished Mar 26 12:31:40 PM PDT 24
Peak memory 218324 kb
Host smart-d3285d51-5dc3-4182-9cd5-cf6a0c8cd2c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273632563 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2273632563
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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