Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6869	1			T2	20		T3	6		T5	79
testmodes[AdcCtrlTestmodeNormal]	5477	1			T1	1		T2	2		T3	6
testmodes[AdcCtrlTestmodeLowpower]	5466	1			T2	15		T5	91		T6	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3745	1			T2	19		T3	2		T5	32
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1699	1			T3	4		T5	28		T8	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1298	1			T2	1		T5	18		T8	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1749	1			T3	3		T5	22		T8	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2074	1			T2	1		T3	2		T4	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1328	1			T5	23		T8	17		T45	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1265	1			T5	25		T8	14		T9	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1353	1			T2	1		T5	17		T8	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2602	1			T2	14		T5	49		T6	16