Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22694

1

T1

1

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3448

1

T2

40

T7

5

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20265

1

T2

35

T3

12

T5

235

auto[1]

5877

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T225	5		T183	18		T226	2
values[0]	34	1			T199	1		T227	11		T228	7
values[1]	613	1			T2	24		T7	11		T133	1
values[2]	763	1			T134	8		T131	16		T65	19
values[3]	797	1			T51	7		T134	5		T56	3
values[4]	786	1			T133	12		T142	11		T32	22
values[5]	2694	1			T1	1		T2	16		T4	18
values[6]	599	1			T9	6		T51	8		T140	2
values[7]	817	1			T50	1		T133	11		T141	10
values[8]	927	1			T54	12		T15	2		T48	1
values[9]	1228	1			T12	1		T50	8		T140	1
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	794	1			T2	24		T7	11		T133	1
values[1]	866	1			T134	8		T131	21		T177	3
values[2]	819	1			T133	12		T134	5		T56	3
values[3]	2878	1			T1	1		T4	18		T10	30
values[4]	601	1			T2	16		T51	8		T54	7
values[5]	514	1			T7	24		T9	6		T140	1
values[6]	854	1			T50	1		T133	11		T141	10
values[7]	908	1			T50	8		T54	12		T15	2
values[8]	731	1			T12	1		T56	5		T25	14
values[9]	316	1			T140	1		T229	8		T230	18
minimum	16861	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	4		T131	7		T154	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	12		T7	1		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T131	10		T177	3		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T134	1		T166	1		T138	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T56	3		T171	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T133	1		T134	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T1	1		T4	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T51	7		T32	12		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T54	7		T140	1		T35	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	8		T51	8		T28	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	7		T28	3		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	4		T140	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T145	2		T186	19		T231	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	1		T133	1		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T54	12		T135	12		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T50	8		T15	2		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T25	14		T138	11		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T56	5		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T230	18		T234	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T140	1		T229	3		T174	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16737	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	2		T131	8		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	12		T7	4		T65	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T131	11		T144	14		T186	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T134	7		T166	10		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T145	8		T138	5		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T133	11		T134	4		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T4	16		T10	27		T11	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T32	10		T80	5		T167	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T35	11		T42	11		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	8		T28	7		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	17		T28	1		T32	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T9	2		T31	8		T33	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T145	22		T186	13		T231	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T133	10		T32	6		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T135	11		T144	9		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T18	7		T149	2		T179	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T138	2		T188	9		T237	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T27	4		T238	12		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T235	11		T24	2		T239	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T229	5		T174	12		T240	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	1		T183	10		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T199	1		T227	11		T228	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	4		T131	10		T154	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T2	12		T7	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T131	7		T144	12		T186	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T134	1		T65	10		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T56	3		T177	3		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T51	7		T134	1		T137	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	1		T177	9		T48	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T133	1		T32	12		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T1	1		T4	2		T7	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	8		T28	11		T53	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T140	1		T35	9		T42	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	4		T51	8		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	3		T32	7		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	1		T133	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T54	12		T135	12		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	2		T48	1		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T25	14		T138	11		T109	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T12	1		T50	8		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T225	4		T183	8		T226	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	2		T131	10		T154	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	12		T7	4		T196	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	9		T144	14		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	7		T65	9		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T145	8		T204	11		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T134	4		T137	13		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T142	10		T144	11		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	11		T32	10		T80	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T4	16		T7	17		T10	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	8		T28	7		T53	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	11		T42	11		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	2		T33	11		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	1		T32	4		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T133	10		T31	8		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T135	11		T144	9		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T49	13		T151	2		T179	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T138	2		T188	9		T237	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T27	4		T238	12		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	3		T131	9		T154	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	13		T7	5		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T131	13		T177	1		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	8		T166	11		T138	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	1		T171	1		T145	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T133	12		T134	5		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T1	1		T4	18		T10	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T51	1		T32	11		T80	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T54	1		T140	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	9		T51	1		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	18		T28	2		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	4		T140	1		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T145	24		T186	14		T231	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	1		T133	11		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T54	1		T135	12		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T50	1		T15	1		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T25	1		T138	3		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T56	1		T27	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T230	1		T234	1		T235	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	1		T229	6		T174	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	3		T131	6		T154	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	11		T65	9		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T131	8		T177	2		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T138	14		T106	12		T173	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T56	2		T138	5		T243	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T136	9		T137	14		T166	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T55	13		T38	26		T25	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	6		T32	11		T167	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T54	6		T35	8		T42	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	7		T51	7		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	6		T28	2		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	2		T33	12		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T186	18		T231	1		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T141	9		T32	14		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T54	11		T135	11		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T50	7		T15	1		T18	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T25	13		T138	10		T179	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T56	4		T238	11		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T230	17		T245	3		T239	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T229	2		T240	4		T246	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T247	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T225	5		T183	9		T226	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T199	1		T227	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	3		T131	12		T154	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	13		T7	5		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	10		T144	15		T186	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	8		T65	10		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	1		T177	1		T145	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T51	1		T134	5		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T142	11		T177	1		T48	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	12		T32	11		T80	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	1		T4	18		T7	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	9		T28	9		T53	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T140	1		T35	12		T42	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	4		T51	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T28	2		T32	5		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T50	1		T133	11		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T54	1		T135	12		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	1		T48	1		T49	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T25	1		T138	3		T109	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T12	1		T50	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T183	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T227	10		T228	6		T241	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	3		T131	8		T154	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T2	11		T157	2		T216	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T131	6		T144	11		T186	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	9		T138	14		T248	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T56	2		T177	2		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T51	6		T137	14		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T177	8		T48	1		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T32	11		T136	9		T166	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T7	6		T54	6		T55	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	7		T28	9		T53	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	8		T42	12		T200	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	2		T51	7		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	2		T32	6		T249	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T141	9		T32	14		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T54	11		T135	11		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T151	5		T179	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T25	13		T138	10		T109	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T50	7		T56	4		T238	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22603

1

T1

1

T2

75

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3539

1

T7

30

T9

6

T50

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20157

1

T2

35

T3

12

T5

235

auto[1]

5985

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	120	1			T250	3		T230	18		T227	11
values[1]	716	1			T9	6		T51	15		T133	12
values[2]	698	1			T12	1		T142	3		T32	22
values[3]	706	1			T7	6		T154	7		T49	40
values[4]	588	1			T140	2		T35	20		T33	23
values[5]	854	1			T134	8		T42	24		T131	5
values[6]	813	1			T2	16		T54	12		T131	16
values[7]	650	1			T7	24		T133	11		T131	15
values[8]	737	1			T50	8		T140	1		T56	5
values[9]	3401	1			T1	1		T2	24		T4	18
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1042	1			T9	6		T51	15		T133	12
values[1]	755	1			T7	6		T12	1		T56	3
values[2]	627	1			T140	1		T177	12		T154	7
values[3]	666	1			T134	8		T140	1		T35	20
values[4]	738	1			T42	24		T131	16		T141	10
values[5]	798	1			T2	16		T54	12		T131	15
values[6]	3003	1			T1	1		T4	18		T7	24
values[7]	486	1			T140	1		T31	9		T49	1
values[8]	958	1			T2	24		T7	5		T50	1
values[9]	198	1			T33	2		T136	12		T173	29
minimum	16871	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T51	15		T133	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T9	4		T142	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T48	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	4		T56	3		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T177	9		T154	5		T49	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T140	1		T177	3		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T134	1		T35	9		T28	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T140	1		T131	3		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T141	10		T48	7		T238	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	13		T131	7		T25	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	8		T54	12		T131	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T236	1		T186	19		T105	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T1	1		T4	2		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	7		T133	1		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T140	1		T49	1		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T31	1		T229	3		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	12		T7	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T50	1		T133	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T136	10		T173	14		T179	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T33	1		T173	4		T251	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16736	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	11		T142	2		T149	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T9	2		T142	10		T27	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T80	5		T65	9		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	2		T49	13		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	2		T49	19		T65	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T136	11		T155	14		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T134	7		T35	11		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	2		T33	10		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T238	12		T236	14		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T42	11		T131	9		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	8		T131	8		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T236	12		T186	13		T105	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T4	16		T10	27		T11	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	17		T133	10		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T144	14		T17	2		T200	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T31	8		T229	5		T249	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	12		T7	4		T134	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T33	1		T135	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T136	2		T173	11		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T33	1		T251	16		T253	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T250	3		T254	10		T161	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T230	18		T227	11		T255	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	15		T133	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	4		T56	3		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	1		T142	1		T177	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T32	12		T177	3		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T154	5		T49	21		T65	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	4		T136	10		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	9		T166	18		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	2		T33	13		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T134	1		T141	10		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T42	13		T131	3		T144	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T2	8		T54	12		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T131	7		T25	16		T186	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	7		T49	1		T109	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	7		T133	1		T32	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T50	8		T140	1		T56	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	14		T229	3		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T1	1		T2	12		T4	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T50	1		T133	1		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T254	11		T161	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T255	1		T257	13		T258	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T133	11		T207	5		T240	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	2		T142	10		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T142	2		T80	5		T65	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T32	10		T49	13		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T154	2		T49	19		T65	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	2		T136	11		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	11		T166	8		T259	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T33	10		T167	1		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T134	7		T28	1		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T42	11		T131	2		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	8		T236	14		T106	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T131	9		T186	13		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T131	8		T187	11		T196	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	17		T133	10		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	7		T144	14		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T229	5		T108	17		T249	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T2	12		T4	16		T7	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T31	8		T33	2		T135	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3