Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22548

1

T1

1

T2

51

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T2

24

T7

29

T50

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20031

1

T2

75

T3

12

T5

235

auto[1]

6111

1

T1

1

T4

18

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T2	16		T136	21		T137	1
values[0]	50	1			T162	16		T308	18		T313	15
values[1]	578	1			T7	24		T50	1		T134	8
values[2]	886	1			T51	8		T142	11		T28	4
values[3]	598	1			T9	6		T134	5		T140	1
values[4]	643	1			T54	7		T25	14		T48	7
values[5]	663	1			T7	6		T133	1		T28	18
values[6]	810	1			T2	24		T54	12		T32	22
values[7]	655	1			T7	5		T12	1		T133	11
values[8]	3089	1			T1	1		T4	18		T10	30
values[9]	1058	1			T51	7		T56	3		T141	10
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T7	24		T134	8		T140	2
values[1]	785	1			T51	8		T142	11		T31	9
values[2]	650	1			T9	6		T134	5		T140	1
values[3]	591	1			T54	7		T25	14		T48	8
values[4]	713	1			T7	6		T133	1		T28	18
values[5]	840	1			T2	24		T7	5		T54	12
values[6]	2920	1			T1	1		T4	18		T10	30
values[7]	825	1			T133	12		T35	20		T15	2
values[8]	942	1			T51	7		T56	3		T141	10
values[9]	124	1			T2	16		T33	2		T177	3
minimum	17067	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	10		T25	16		T65	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	7		T134	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T51	8		T32	7		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T142	1		T31	1		T33	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	4		T134	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T151	7		T230	13		T260	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T25	14		T135	12		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T54	7		T48	8		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	4		T154	5		T173	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	1		T28	11		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T131	7		T177	9		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	12		T7	1		T54	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T1	1		T4	2		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T42	13		T142	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	9		T27	1		T32	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T133	1		T15	2		T238	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T51	7		T56	3		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T16	3		T167	1		T53	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T2	8		T19	4		T246	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T33	1		T177	3		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16798	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T50	1		T199	1		T159	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T131	10		T65	9		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	17		T134	7		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T32	4		T136	12		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T142	10		T31	8		T33	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T134	4		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	7		T174	9		T160	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T135	11		T17	2		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	13		T144	11		T106	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	2		T154	2		T173	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	7		T248	10		T216	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T131	9		T136	2		T186	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	12		T7	4		T32	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T4	16		T10	27		T11	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	11		T142	2		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	11		T27	4		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T133	11		T238	12		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T65	3		T136	11		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T167	1		T105	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T2	8		T19	4		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T33	1		T282	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T159	2		T315	1		T162	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T2	8		T136	10		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T137	1		T53	2		T105	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T313	1		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T162	10		T308	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T131	10		T25	16		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	7		T50	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	8		T32	7		T65	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T142	1		T28	3		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	4		T134	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T33	1		T18	11		T251	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	14		T49	1		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T54	7		T48	7		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	4		T135	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T133	1		T28	11		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T177	9		T154	5		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	12		T54	12		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T133	1		T131	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T56	5		T42	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T1	1		T4	2		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T133	1		T238	12		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T51	7		T56	3		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T15	2		T33	1		T177	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	8		T136	11		T225	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T105	8		T151	11		T316	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T313	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T162	6		T308	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	10		T145	11		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	17		T134	7		T80	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T32	4		T65	9		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T142	10		T28	1		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	2		T134	4		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	1		T18	7		T251	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	2		T155	11		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T49	13		T106	12		T108	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T135	11		T149	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	7		T144	11		T200	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T154	2		T136	2		T186	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	12		T32	10		T49	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	10		T131	9		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	4		T42	11		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T4	16		T10	27		T11	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T133	11		T238	12		T166	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	6		T65	3		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T33	1		T16	1		T236	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	12		T25	1		T65	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	18		T134	8		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	1		T32	5		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T142	11		T31	9		T33	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	4		T134	5		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T151	8		T230	1		T260	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	1		T135	12		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T54	1		T48	7		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	3		T154	3		T173	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T133	1		T28	9		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T131	10		T177	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	13		T7	5		T54	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T1	1		T4	18		T10	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T42	12		T142	3		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	12		T27	5		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T133	12		T15	1		T238	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T51	1		T56	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T16	3		T167	2		T53	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T2	9		T19	5		T246	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T33	2		T177	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16914	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T50	1		T199	1		T159	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T131	8		T25	15		T65	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	6		T28	2		T229	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T51	7		T32	6		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	12		T186	10		T18	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	2		T144	11		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T151	6		T230	12		T260	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	13		T135	11		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T54	6		T48	1		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	3		T154	4		T173	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	9		T248	2		T216	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	6		T177	8		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	11		T54	11		T56	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T50	7		T55	13		T38	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	12		T25	3		T138	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	8		T32	14		T224	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T238	11		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T51	6		T56	2		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T16	1		T105	5		T172	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T2	7		T19	3		T246	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T177	2		T311	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T252	8		T249	5		T261	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T159	4		T162	9		T317	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	9		T136	12		T225	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T137	1		T53	2		T105	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T313	15		T314	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T162	7		T308	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	12		T25	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	18		T50	1		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	1		T32	5		T65	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T142	11		T28	2		T31	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	4		T134	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	2		T18	10		T251	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	1		T49	1		T17	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T54	1		T48	6		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	3		T135	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	1		T28	9		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T177	1		T154	3		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	13		T54	1		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T133	11		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	5		T56	1		T42	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T1	1		T4	18		T10	30
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T133	12		T238	13		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T51	1		T56	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	1		T33	2		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T2	7		T136	9		T158	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T105	5		T151	12		T230	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T162	9		T308	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T131	8		T25	15		T252	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T7	6		T229	2		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T51	7		T32	6		T65	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	2		T33	12		T167	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	2		T144	11		T53	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	8		T251	12		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T25	13		T17	1		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T54	6		T48	1		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	3		T135	11		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T28	9		T144	3		T200	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T177	8		T154	4		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	11		T54	11		T32	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T131	6		T200	16		T206	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T56	4		T42	12		T25	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T50	7		T55	13		T35	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T238	11		T166	17		T109	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T51	6		T56	2		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	1		T177	2		T16	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2