Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22385

1

T1

1

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3757

1

T2

40

T7

6

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20231

1

T2

51

T3

12

T5

235

auto[1]

5911

1

T1

1

T2

24

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	350	1			T25	4		T172	18		T204	31
values[0]	62	1			T274	30		T318	13		T303	19
values[1]	768	1			T7	6		T50	8		T54	12
values[2]	760	1			T140	1		T15	2		T32	21
values[3]	797	1			T134	8		T54	7		T140	1
values[4]	730	1			T7	24		T9	6		T140	1
values[5]	3062	1			T1	1		T2	40		T4	18
values[6]	625	1			T12	1		T51	15		T133	11
values[7]	929	1			T56	5		T33	2		T80	6
values[8]	431	1			T133	1		T177	9		T65	27
values[9]	769	1			T7	5		T50	1		T56	3
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T7	6		T54	12		T35	20
values[1]	681	1			T140	2		T15	2		T135	23
values[2]	913	1			T134	8		T54	7		T131	21
values[3]	2861	1			T1	1		T2	16		T4	18
values[4]	706	1			T2	24		T12	1		T133	23
values[5]	719	1			T51	15		T134	5		T27	5
values[6]	844	1			T133	1		T56	5		T33	2
values[7]	433	1			T131	15		T177	9		T65	19
values[8]	914	1			T7	5		T50	1		T56	3
values[9]	105	1			T204	31		T206	16		T276	19
minimum	17233	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	9		T177	3		T138	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	4		T54	12		T32	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	2		T135	12		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	2		T266	11		T188	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T54	7		T131	3		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T134	1		T131	7		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T1	1		T4	2		T7	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	8		T140	1		T42	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	2		T49	2		T186	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	12		T12	1		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T51	15		T136	15		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	1		T27	1		T28	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T56	5		T144	12		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	1		T33	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T177	9		T136	10		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T131	7		T65	10		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T56	3		T25	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T50	1		T142	1		T25	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T204	15		T276	15		T275	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T206	9		T272	7		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16828	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T108	14		T150	11		T93	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	11		T138	2		T53	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	2		T32	6		T173	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T135	11		T238	12		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T266	10		T188	8		T205	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T131	2		T31	8		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	7		T131	9		T142	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T4	16		T7	17		T9	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	8		T42	11		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T133	21		T49	13		T186	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	12		T16	1		T18	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	12		T17	2		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T134	4		T27	4		T28	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T144	14		T236	12		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T33	1		T65	3		T167	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	2		T155	14		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T131	8		T65	9		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	4		T154	2		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T142	2		T229	5		T166	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T204	16		T276	4		T320	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T206	7		T272	4		T319	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T15	1		T32	10		T49	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T108	17		T150	12		T321	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T25	4		T172	10		T204	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T179	8		T206	9		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T274	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T318	13		T303	19		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	8		T35	9		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	4		T54	12		T108	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	2		T135	12		T138	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T140	1		T32	15		T173	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T54	7		T131	3		T238	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T134	1		T140	1		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	7		T9	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T140	1		T42	13		T131	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T1	1		T4	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	20		T141	10		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T51	15		T133	1		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T134	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T56	5		T144	12		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T33	1		T80	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T177	9		T136	10		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T133	1		T65	15		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	1		T56	3		T25	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T50	1		T131	7		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T172	8		T204	16		T299	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T179	14		T206	7		T322	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T274	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	11		T32	10		T49	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	2		T108	17		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T135	11		T138	2		T259	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T32	6		T173	11		T266	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T131	2		T238	12		T186	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	7		T33	11		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	17		T9	2		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T42	11		T131	9		T142	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T4	16		T10	27		T11	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	20		T28	7		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	10		T49	13		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T134	4		T27	4		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T144	14		T236	12		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	1		T80	5		T167	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T136	2		T155	14		T205	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T65	12		T136	11		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	4		T154	2		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T131	8		T142	2		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T35	12		T177	1		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	3		T54	1		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T15	1		T135	12		T238	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	2		T266	11		T188	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T54	1		T131	3		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T134	8		T131	10		T142	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T1	1		T4	18		T7	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	9		T140	1		T42	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T133	23		T49	15		T186	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	13		T12	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T51	2		T136	13		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	5		T27	5		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T56	1		T144	15		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T133	1		T33	2		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T177	1		T136	3		T155	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	9		T65	10		T136	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	5		T56	1		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T50	1		T142	3		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T204	17		T276	5		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T206	8		T272	8		T319	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T108	18		T150	13		T93	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	8		T177	2		T138	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	3		T54	11		T32	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	1		T135	11		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T266	10		T188	13		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T54	6		T131	2		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T131	6		T33	12		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T7	6		T9	2		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	7		T42	12		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T186	21		T109	10		T151	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	11		T141	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T51	13		T136	14		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	11		T187	4		T173	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T56	4		T144	11		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T65	4		T167	8		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T177	8		T136	9		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T131	6		T65	9		T136	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	2		T25	18		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T25	13		T229	2		T166	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T204	14		T276	14		T275	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T206	8		T272	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T50	7		T32	11		T49	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T108	13		T150	10		T321	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T25	1		T172	9		T204	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T179	15		T206	8		T322	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T274	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T318	1		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T50	1		T35	12		T32	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	3		T54	1		T108	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T135	12		T138	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T140	1		T32	7		T173	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T54	1		T131	3		T238	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T134	8		T140	1		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	18		T9	4		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	1		T42	12		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T1	1		T4	18		T10	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	22		T141	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T51	2		T133	11		T49	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	1		T134	5		T27	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T56	1		T144	15		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T33	2		T80	6		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T177	1		T136	3		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T133	1		T65	14		T136	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	5		T56	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T50	1		T131	9		T142	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T25	3		T172	9		T204	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	7		T206	8		T272	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T274	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T318	12		T303	18		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T50	7		T35	8		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	3		T54	11		T108	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	1		T135	11		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T32	14		T173	13		T266	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T54	6		T131	2		T238	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T33	12		T137	14		T252	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	6		T9	2		T249	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T42	12		T131	6		T109	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T55	13		T38	26		T30	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	18		T141	9		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	13		T136	14		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T28	2		T187	4		T173	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T56	4		T144	11		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T167	8		T156	14		T204	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T177	8		T136	9		T248	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T65	13		T136	9		T246	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T56	2		T25	15		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T131	6		T25	13		T229	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2