Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22418

1

T1

1

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3724

1

T2

40

T7

35

T50

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20212

1

T2

75

T3

12

T5

227

auto[1]

5930

1

T1

1

T4

18

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	642	1			T5	8		T8	1		T45	1
values[0]	101	1			T138	13		T199	1		T151	8
values[1]	937	1			T2	24		T7	24		T134	5
values[2]	2886	1			T1	1		T2	16		T4	18
values[3]	674	1			T140	1		T35	20		T236	13
values[4]	802	1			T9	6		T50	1		T51	8
values[5]	769	1			T134	8		T131	20		T141	10
values[6]	628	1			T54	7		T131	16		T25	14
values[7]	724	1			T42	24		T142	3		T25	16
values[8]	549	1			T133	11		T142	11		T15	2
values[9]	965	1			T7	5		T133	12		T25	4
minimum	16465	1			T2	35		T3	12		T5	227

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	805	1			T2	24		T12	1		T28	4
values[1]	2938	1			T1	1		T2	16		T4	18
values[2]	830	1			T9	6		T51	8		T35	20
values[3]	709	1			T50	1		T133	1		T134	8
values[4]	754	1			T131	15		T141	10		T28	18
values[5]	647	1			T54	7		T131	16		T25	14
values[6]	656	1			T42	24		T142	3		T15	2
values[7]	573	1			T133	11		T142	11		T232	1
values[8]	905	1			T7	5		T133	12		T54	12
values[9]	135	1			T16	4		T53	24		T157	14
minimum	17190	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T33	1		T80	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	12		T28	3		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T1	1		T4	2		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	8		T7	4		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	4		T51	8		T35	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T236	1		T145	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T133	1		T134	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T50	1		T140	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T131	7		T28	11		T32	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T141	10		T32	12		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T145	1		T149	1		T157	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T54	7		T131	7		T25	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	13		T49	1		T144	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	1		T15	2		T25	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T133	1		T142	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T242	3		T251	13		T249	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T133	1		T56	3		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T54	12		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T16	3		T157	3		T316	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T53	10		T292	18		T323	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16820	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T7	7		T134	1		T18	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	1		T80	5		T65	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	12		T28	1		T236	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T4	16		T10	27		T11	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	8		T7	2		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	2		T35	11		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T236	12		T145	8		T204	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	7		T131	2		T33	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T238	12		T49	13		T136	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T131	8		T28	7		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	10		T229	5		T137	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T145	11		T149	7		T157	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	9		T49	19		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T42	11		T144	20		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T142	2		T27	4		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T133	10		T142	10		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T242	1		T251	16		T249	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T133	11		T167	1		T186	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	4		T136	2		T155	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T16	1		T157	11		T316	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T53	14		T324	2		T320	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	1		T31	8		T49	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	17		T134	4		T18	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	491	1			T5	8		T8	1		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T54	12		T292	18		T176	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T138	11		T199	1		T151	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T306	23		T325	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T31	1		T33	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	12		T7	7		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T1	1		T4	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	8		T7	4		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T35	9		T145	1		T252	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	1		T236	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	4		T51	8		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T50	1		T140	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T134	1		T131	10		T28	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T141	10		T229	3		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	15		T145	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	7		T131	7		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	13		T49	1		T144	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T142	1		T25	16		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	1		T142	1		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	2		T135	12		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T133	1		T177	12		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	1		T25	4		T136	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16341	1			T2	35		T3	12		T5	227
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T16	1		T179	13		T161	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T326	12		T320	1		T258	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T138	2		T151	2		T206	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T306	20		T325	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T31	8		T33	1		T80	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	12		T7	17		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T4	16		T10	27		T11	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	8		T7	2		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	11		T145	11		T252	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T236	12		T204	16		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	2		T33	10		T186	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T238	12		T49	13		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T134	7		T131	10		T28	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T229	5		T137	13		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T32	6		T145	11		T149	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T131	9		T32	10		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	11		T144	11		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T142	2		T27	4		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T133	10		T142	10		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T135	11		T242	1		T251	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T133	11		T136	12		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	4		T136	2		T155	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T33	2		T80	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	13		T28	2		T236	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	1		T4	18		T10	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	9		T7	3		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	4		T51	1		T35	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T236	13		T145	9		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	1		T134	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T50	1		T140	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	9		T28	9		T32	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T141	1		T32	11		T229	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T145	12		T149	8		T157	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T54	1		T131	10		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T42	12		T49	1		T144	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	3		T15	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	11		T142	11		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T242	3		T251	17		T249	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T133	12		T56	1		T177	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	5		T54	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T16	3		T157	12		T316	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T53	19		T292	1		T323	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16924	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	18		T134	5		T18	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T65	9		T167	8		T138	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	11		T28	2		T156	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T50	7		T51	6		T55	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	7		T7	3		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	2		T51	7		T35	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T204	14		T216	5		T160	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T56	4		T131	2		T33	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T238	11		T136	9		T200	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T131	6		T28	9		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	9		T32	11		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T157	11		T267	2		T307	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	6		T131	6		T25	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T42	12		T144	5		T198	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T25	15		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T136	14		T173	3		T267	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T242	1		T251	12		T249	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T56	2		T177	10		T186	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	11		T25	3		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T16	1		T157	2		T286	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T53	5		T292	17		T324	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T151	5		T206	7		T304	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T7	6		T18	8		T327	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T5	8		T8	1		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T54	1		T292	1		T176	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T138	3		T199	1		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T306	21		T325	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T31	9		T33	2		T80	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T2	13		T7	18		T134	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T1	1		T4	18		T10	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	9		T7	3		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T35	12		T145	12		T252	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T140	1		T236	13		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	4		T51	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	1		T140	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T134	8		T131	12		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T141	1		T229	6		T137	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	7		T145	12		T149	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T54	1		T131	10		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	12		T49	1		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T142	3		T25	1		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	11		T142	11		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T135	12		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T133	12		T177	2		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	5		T25	1		T136	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T2	35		T3	12		T5	227
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T56	2		T16	1		T262	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T54	11		T292	17		T176	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T138	10		T151	5		T206	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T306	22		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	9		T138	5		T224	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	11		T7	6		T28	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T50	7		T51	6		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	7		T7	3		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	8		T252	8		T150	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T204	14		T216	5		T160	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	2		T51	7		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T238	11		T136	9		T179	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T131	8		T28	9		T154	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	9		T229	2		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T32	14		T204	4		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T54	6		T131	6		T25	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T42	12		T144	3		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	15		T49	19		T65	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T144	2		T198	16		T173	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	1		T135	11		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T177	10		T136	14		T186	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T25	3		T136	9		T138	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2