Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22512

1

T1

1

T2

75

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3630

1

T7

24

T9

6

T50

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20098

1

T2

35

T3

12

T5

235

auto[1]

6044

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T50	1		T133	1		T54	7
values[0]	103	1			T51	8		T250	3		T230	18
values[1]	703	1			T9	6		T51	7		T133	12
values[2]	722	1			T12	1		T56	3		T142	3
values[3]	712	1			T7	6		T140	1		T154	7
values[4]	582	1			T134	8		T140	1		T35	20
values[5]	800	1			T42	24		T131	5		T28	4
values[6]	884	1			T2	16		T54	12		T131	31
values[7]	648	1			T7	24		T133	11		T25	14
values[8]	679	1			T50	8		T140	1		T56	5
values[9]	3162	1			T1	1		T2	24		T4	18
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	762	1			T9	6		T133	12		T142	14
values[1]	769	1			T7	6		T12	1		T56	3
values[2]	609	1			T140	1		T177	9		T154	7
values[3]	634	1			T134	8		T140	1		T35	20
values[4]	724	1			T42	24		T131	16		T141	10
values[5]	845	1			T2	16		T54	12		T131	15
values[6]	3011	1			T1	1		T4	18		T7	24
values[7]	478	1			T50	8		T140	1		T31	9
values[8]	999	1			T2	24		T7	5		T50	1
values[9]	168	1			T33	2		T136	12		T173	25
minimum	17143	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	1		T142	1		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	4		T142	1		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	4		T12	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	3		T177	3		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T177	9		T154	5		T65	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T140	1		T136	10		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	1		T35	9		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T140	1		T131	3		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T141	10		T28	3		T48	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T42	13		T131	7		T195	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	8		T131	7		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T54	12		T25	16		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	1		T4	2		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	7		T133	1		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T50	8		T140	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T31	1		T229	3		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T2	12		T7	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T50	1		T33	1		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T136	10		T173	14		T179	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T33	1		T251	13		T158	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16791	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T32	7		T137	15		T262	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T133	11		T142	2		T27	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	2		T142	10		T32	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	2		T80	5		T49	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T49	13		T145	8		T186	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T154	2		T65	3		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T136	11		T155	14		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T134	7		T35	11		T138	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T131	2		T33	10		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T28	1		T238	12		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T42	11		T131	9		T195	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	8		T131	8		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T236	12		T186	13		T105	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T4	16		T10	27		T11	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	17		T133	10		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T17	2		T200	8		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	8		T229	5		T249	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	12		T7	4		T134	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T33	1		T135	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T136	2		T173	11		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T33	1		T251	16		T253	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T32	4		T137	13		T20	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T133	1		T54	7		T199	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T50	1		T33	1		T136	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T51	8		T250	3		T254	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T230	18		T227	11		T257	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	7		T133	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	4		T142	1		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	1		T142	1		T177	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	3		T32	12		T177	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	4		T154	5		T49	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	1		T136	10		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T134	1		T35	9		T166	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	1		T33	13		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T28	3		T48	7		T238	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T42	13		T131	3		T144	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	8		T131	7		T141	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	12		T131	7		T25	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	1		T109	11		T187	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	7		T133	1		T25	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	8		T140	1		T56	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T229	3		T232	1		T167	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T1	1		T2	12		T4	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T31	1		T33	1		T135	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T179	13		T315	1		T96	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T33	1		T136	12		T225	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T254	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T257	13		T258	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T133	11		T27	4		T207	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	2		T142	10		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	2		T80	5		T65	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	10		T49	13		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	2		T154	2		T49	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T136	11		T155	14		T18	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	7		T35	11		T166	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T33	10		T167	1		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	1		T238	12		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T42	11		T131	2		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	8		T131	8		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	9		T186	13		T105	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T187	11		T196	11		T328	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	17		T133	10		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T28	7		T17	2		T200	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T229	5		T167	9		T108	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T2	12		T4	16		T7	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T31	8		T33	1		T135	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	12		T142	3		T27	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T9	4		T142	11		T32	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	3		T12	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T56	1		T177	1		T49	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T177	1		T154	3		T65	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	1		T136	12		T155	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T134	8		T35	12		T138	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	1		T131	3		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T141	1		T28	2		T48	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T42	12		T131	10		T195	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	9		T131	9		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T54	1		T25	1		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T1	1		T4	18		T10	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	18		T133	11		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T50	1		T140	1		T17	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	9		T229	6		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	13		T7	5		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T50	1		T33	2		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T136	3		T173	12		T179	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T33	2		T251	17		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16897	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	5		T137	14		T262	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T179	7		T260	3		T202	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	2		T32	11		T156	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T49	19		T65	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T56	2		T177	2		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T177	8		T154	4		T65	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T136	9		T188	13		T151	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	8		T138	10		T293	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T131	2		T33	12		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	9		T28	2		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	12		T131	6		T231	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	7		T131	6		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	11		T25	15		T186	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T55	13		T56	4		T38	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	6		T25	13		T32	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T50	7		T17	1		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T229	2		T109	16		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	11		T54	6		T25	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T135	11		T16	1		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T136	9		T173	13		T179	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T251	12		T158	12		T253	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T51	13		T240	10		T159	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T32	6		T137	14		T262	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T133	1		T54	1		T199	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T50	1		T33	2		T136	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T51	1		T250	3		T254	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T230	1		T227	1		T257	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T51	1		T133	12		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T9	4		T142	11		T32	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T142	3		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T56	1		T32	11		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	3		T154	3		T49	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	1		T136	12		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T134	8		T35	12		T166	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	1		T33	11		T167	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T28	2		T48	6		T238	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	12		T131	3		T144	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	9		T131	9		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T54	1		T131	10		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	1		T109	1		T187	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	18		T133	11		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	1		T140	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T229	6		T232	1		T167	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T1	1		T2	13		T4	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T31	9		T33	2		T135	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T54	6		T179	20		T283	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T136	14		T173	3		T243	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T51	7		T254	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T230	17		T227	10		T257	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T51	6		T240	10		T159	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	2		T32	6		T137	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T177	8		T65	9		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	2		T32	11		T177	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	3		T154	4		T49	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T136	9		T18	8		T188	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T35	8		T166	17		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T33	12		T151	5		T264	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T28	2		T48	1		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T42	12		T131	2		T144	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	7		T131	6		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	11		T131	6		T25	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T109	10		T187	10		T267	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	6		T25	13		T32	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T50	7		T56	4		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T229	2		T167	12		T108	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	11		T55	13		T38	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T135	11		T16	1		T144	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2