Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22664

1

T1

1

T2

59

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3478

1

T2

16

T7

35

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19822

1

T2

35

T3

12

T5

235

auto[1]

6320

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	225	1			T133	1		T54	12		T144	12
values[0]	58	1			T109	17		T207	9		T228	7
values[1]	589	1			T2	16		T134	5		T15	2
values[2]	2847	1			T1	1		T2	24		T4	18
values[3]	608	1			T7	5		T56	8		T35	20
values[4]	732	1			T50	1		T133	12		T25	14
values[5]	595	1			T9	6		T140	2		T49	1
values[6]	1028	1			T134	8		T42	24		T131	5
values[7]	773	1			T133	11		T154	7		T135	23
values[8]	696	1			T7	6		T51	8		T141	10
values[9]	1132	1			T7	24		T12	1		T50	8
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	726	1			T2	16		T51	7		T54	7
values[1]	2804	1			T1	1		T2	24		T4	18
values[2]	607	1			T56	8		T35	20		T142	3
values[3]	716	1			T9	6		T50	1		T133	12
values[4]	890	1			T140	1		T42	24		T131	5
values[5]	893	1			T134	8		T32	22		T154	7
values[6]	815	1			T7	6		T133	11		T135	23
values[7]	662	1			T51	8		T141	10		T25	4
values[8]	908	1			T7	24		T12	1		T50	8
values[9]	156	1			T54	12		T144	12		T262	13
minimum	16965	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T54	7		T15	2		T32	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	8		T51	7		T28	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T1	1		T2	12		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	1		T33	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T56	5		T142	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T56	3		T35	9		T32	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	1		T133	1		T25	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	4		T140	1		T28	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	13		T49	1		T65	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T140	1		T131	3		T65	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T154	5		T144	12		T224	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T134	1		T32	12		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T135	12		T49	21		T166	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	4		T133	1		T236	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	8		T141	10		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	1		T155	1		T186	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	1		T50	8		T229	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	7		T133	1		T131	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T262	13		T204	5		T158	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T54	12		T144	3		T240	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16783	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T134	1		T232	1		T207	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T32	4		T33	10		T238	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	8		T28	7		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T2	12		T4	16		T10	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T7	4		T33	1		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T142	2		T27	4		T149	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	11		T32	6		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T133	11		T187	21		T284	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	2		T28	1		T166	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T42	11		T65	3		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T131	2		T65	9		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T154	2		T144	14		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	7		T32	10		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T135	11		T49	19		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	2		T133	10		T236	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T31	8		T49	13		T196	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	14		T186	11		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T229	5		T136	13		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	17		T131	8		T80	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T204	11		T254	11		T314	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T144	9		T240	14		T329	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T134	4		T207	8		T286	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T262	13		T204	5		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T133	1		T54	12		T144	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T109	17		T294	1		T285	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T207	1		T228	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	2		T32	7		T33	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	8		T134	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T1	1		T2	12		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	7		T33	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T56	5		T142	2		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T56	3		T35	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	1		T133	1		T25	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	3		T148	1		T53	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	1		T65	5		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	4		T140	2		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T42	13		T144	12		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T134	1		T131	3		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T154	5		T135	12		T166	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T133	1		T236	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T51	8		T141	10		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	4		T48	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T12	1		T50	8		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T7	7		T131	7		T80	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T204	11		T254	11		T330	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T144	9		T240	14		T20	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T294	12		T285	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T207	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T32	4		T33	10		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	8		T134	4		T28	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T2	12		T4	16		T10	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T33	1		T145	11		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T142	12		T27	4		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	4		T35	11		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T133	11		T187	21		T246	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	1		T53	14		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T65	3		T17	2		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	2		T166	10		T204	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T42	11		T144	14		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	7		T131	2		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	2		T135	11		T166	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T133	10		T236	14		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	32		T167	9		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	2		T236	12		T186	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T31	8		T229	5		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T7	17		T131	8		T80	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T54	1		T15	1		T32	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	9		T51	1		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T1	1		T2	13		T4	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T7	5		T33	2		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	1		T142	3		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T56	1		T35	12		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	1		T133	12		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T9	4		T140	1		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T42	12		T49	1		T65	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T140	1		T131	3		T65	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T154	3		T144	15		T224	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T134	8		T32	11		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T135	12		T49	21		T166	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	3		T133	11		T236	28
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T51	1		T141	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	1		T155	15		T186	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	1		T50	1		T229	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	18		T133	1		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T262	1		T204	12		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T54	1		T144	10		T240	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16889	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T134	5		T232	1		T207	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T54	6		T15	1		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	7		T51	6		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	11		T55	13		T38	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T201	7		T302	8		T331	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	4		T156	14		T109	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T56	2		T35	8		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T25	13		T187	14		T289	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	2		T28	2		T53	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T42	12		T65	4		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T131	2		T65	9		T137	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T154	4		T144	11		T224	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T32	11		T136	14		T167	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T135	11		T49	19		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	3		T198	13		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T51	7		T141	9		T25	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T186	10		T179	20		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	7		T229	2		T136	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	6		T131	6		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T262	12		T204	4		T158	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T54	11		T144	2		T240	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T186	18		T332	12		T303	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	4		T283	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T262	1		T204	12		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T133	1		T54	1		T144	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T109	1		T294	13		T285	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T207	9		T228	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	1		T32	5		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	9		T134	5		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T1	1		T2	13		T4	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T51	1		T33	2		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	1		T142	14		T27	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	5		T56	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T133	12		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	2		T148	1		T53	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T65	4		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	4		T140	2		T166	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T42	12		T144	15		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T134	8		T131	3		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T154	3		T135	12		T166	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T133	11		T236	15		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	1		T141	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	3		T48	1		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T12	1		T50	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T7	18		T131	9		T80	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T262	12		T204	4		T254	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T54	11		T144	2		T240	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T109	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T228	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	1		T32	6		T33	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	7		T28	9		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T2	11		T54	6		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T51	6		T150	10		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T56	4		T16	1		T109	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	2		T35	8		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	13		T156	14		T187	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T28	2		T53	5		T248	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T65	4		T17	1		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	2		T204	24		T201	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T42	12		T144	11		T138	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T131	2		T32	11		T65	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T154	4		T135	11		T166	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T167	8		T198	13		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T51	7		T141	9		T25	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	3		T186	10		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T50	7		T229	2		T136	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	6		T131	6		T138	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2