Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19911

1

T2

35

T3

12

T5

235

auto[ADC_CTRL_FILTER_COND_OUT]

6231

1

T1

1

T2

40

T4

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19869

1

T2

51

T3

12

T5

235

auto[1]

6273

1

T1

1

T2

24

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T35	20		T236	15		T138	24
values[0]	65	1			T131	5		T200	25		T333	2
values[1]	535	1			T2	24		T9	6		T50	1
values[2]	870	1			T2	16		T7	5		T51	7
values[3]	722	1			T134	5		T140	1		T131	16
values[4]	723	1			T54	12		T140	2		T131	15
values[5]	686	1			T133	12		T28	4		T32	21
values[6]	827	1			T12	1		T50	8		T51	8
values[7]	757	1			T7	24		T56	5		T25	14
values[8]	714	1			T7	6		T133	12		T54	7
values[9]	3141	1			T1	1		T4	18		T10	30
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	586	1			T7	5		T9	6		T134	8
values[1]	3069	1			T1	1		T2	16		T4	18
values[2]	752	1			T134	5		T131	31		T141	10
values[3]	649	1			T133	12		T54	12		T140	2
values[4]	752	1			T32	21		T136	21		T138	11
values[5]	821	1			T7	24		T12	1		T50	8
values[6]	795	1			T133	12		T56	5		T25	14
values[7]	650	1			T7	6		T54	7		T32	22
values[8]	847	1			T35	20		T25	20		T48	7
values[9]	137	1			T56	3		T49	40		T109	17
minimum	17084	1			T2	59		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T131	3		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	4		T134	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	7		T15	2		T186	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1598	1			T1	1		T2	8		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	14		T141	10		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T134	1		T186	11		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T54	12		T27	1		T28	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	1		T140	2		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T32	15		T136	10		T198	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T138	6		T173	14		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T7	7		T12	1		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T42	13		T135	12		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	1		T56	5		T25	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T133	1		T238	12		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	4		T262	13		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	7		T32	12		T138	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	7		T236	1		T256	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	9		T25	20		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T56	3		T158	3		T100	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T49	21		T109	17		T250	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16776	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	12		T178	1		T260	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T7	4		T131	2		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	2		T134	7		T142	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T186	10		T106	12		T259	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1146	1			T2	8		T4	16		T10	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T131	17		T142	2		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T134	4		T186	11		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T27	4		T28	1		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T133	11		T33	10		T167	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	6		T136	11		T188	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T138	5		T173	11		T237	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	17		T229	5		T145	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T42	11		T135	11		T155	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T133	10		T108	17		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T238	12		T49	13		T137	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	2		T293	13		T286	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T32	10		T138	2		T186	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T236	14		T196	11		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	11		T236	12		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T283	11		T253	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T49	19		T279	5		T334	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	1		T31	8		T49	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T2	12		T240	10		T288	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T236	1		T196	1		T158	19
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T35	9		T138	15		T109	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T131	3		T333	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T200	17		T295	3		T296	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T50	1		T31	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	12		T9	4		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T51	7		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	8		T142	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T131	7		T141	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T134	1		T140	1		T186	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T54	12		T131	7		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T140	2		T33	13		T177	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T28	3		T32	15		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	1		T167	1		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	1		T50	8		T51	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T42	13		T155	1		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	7		T56	5		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T135	12		T238	12		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	4		T133	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	1		T54	7		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T56	3		T48	7		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1540	1			T1	1		T4	2		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T236	14		T196	11		T329	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T35	11		T138	9		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T131	2		T333	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T200	8		T295	4		T296	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T31	8		T33	1		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	12		T9	2		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	4		T16	1		T65	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	8		T142	10		T28	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T131	9		T142	2		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	4		T186	11		T204	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T131	8		T27	4		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T33	10		T172	8		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T28	1		T32	6		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T133	11		T167	1		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T145	19		T167	9		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T42	11		T155	14		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	17		T229	5		T167	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T135	11		T238	12		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	2		T133	10		T108	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	10		T138	2		T186	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T242	1		T251	16		T248	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1098	1			T4	16		T10	27		T11	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	5		T131	3		T33	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	4		T134	8		T142	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	1		T15	1		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1503	1			T1	1		T2	9		T4	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	19		T141	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T134	5		T186	12		T149	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	1		T27	5		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T133	12		T140	2		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	7		T136	12		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T138	6		T173	12		T237	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	18		T12	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	12		T135	12		T155	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T133	11		T56	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T133	1		T238	13		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T262	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T54	1		T32	11		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T48	6		T236	15		T256	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	12		T25	2		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T56	1		T158	1		T100	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T49	21		T109	1		T250	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16909	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T2	13		T178	1		T260	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T131	2		T177	8		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T144	14		T166	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T51	6		T15	1		T186	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1241	1			T2	7		T55	13		T38	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	12		T141	9		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T186	10		T204	4		T188	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T54	11		T28	2		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	12		T177	2		T172	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	14		T136	9		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	5		T173	13		T246	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	6		T50	7		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T42	12		T135	11		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T56	4		T25	13		T108	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T238	11		T137	14		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	3		T262	12		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	6		T32	11		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	1		T242	1		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	8		T25	18		T138	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T56	2		T158	2		T283	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T49	19		T109	16		T279	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T246	6		T276	14		T182	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T2	11		T260	9		T240	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T236	15		T196	12		T158	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T35	12		T138	10		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T131	3		T333	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T200	9		T295	5		T296	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T50	1		T31	9		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	13		T9	4		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	5		T51	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T2	9		T142	11		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	10		T141	1		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	5		T140	1		T186	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T54	1		T131	9		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T140	2		T33	11		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	2		T32	7		T136	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T133	12		T167	2		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T50	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	12		T155	15		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	18		T56	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T135	12		T238	13		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	3		T133	11		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	1		T54	1		T32	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T56	1		T48	6		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1442	1			T1	1		T4	18		T10	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T158	17		T320	10		T226	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T35	8		T138	14		T109	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T131	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T200	16		T295	2		T296	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T177	8		T200	7		T249	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	11		T9	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	6		T15	1		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	7		T28	9		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T131	6		T141	9		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T186	10		T262	16		T204	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T54	11		T131	6		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T33	12		T177	2		T172	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T28	2		T32	14		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T138	5		T230	1		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	7		T51	7		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	12		T156	14		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	6		T56	4		T25	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T135	11		T238	11		T137	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	3		T108	13		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	6		T32	11		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T56	2		T48	1		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1196	1			T55	13		T38	26		T25	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2