Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T51	2		T133	12		T142	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T9	4		T142	11		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T48	1		T80	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	3		T56	1		T49	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T177	1		T154	3		T49	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	1		T177	1		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T134	8		T35	12		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	1		T131	3		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T141	1		T48	6		T238	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	12		T131	10		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	9		T54	1		T131	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T236	13		T186	14		T105	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1405	1			T1	1		T4	18		T10	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	18		T133	11		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T140	1		T49	1		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	9		T229	6		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	13		T7	5		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T50	1		T133	1		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T136	3		T173	12		T179	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T33	2		T173	1		T251	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T227	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T51	13		T179	7		T260	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	2		T32	17		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T65	9		T252	8		T261	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	3		T56	2		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T177	8		T154	4		T49	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T177	2		T136	9		T188	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	8		T28	2		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	2		T33	12		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	9		T48	1		T238	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	12		T131	6		T25	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	7		T54	11		T131	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T186	18		T105	5		T198	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T50	7		T55	13		T56	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	6		T25	13		T32	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T144	11		T17	1		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T229	2		T109	16		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	11		T54	6		T25	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T135	11		T16	1		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T136	9		T173	13		T179	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T173	3		T251	12		T158	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T250	3		T254	12		T161	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T230	1		T227	1		T255	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T51	2		T133	12		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	4		T56	1		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T142	3		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T32	11		T177	1		T49	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T154	3		T49	21		T65	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	3		T136	12		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T35	12		T166	9		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T140	2		T33	11		T167	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T134	8		T141	1		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T42	12		T131	3		T144	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	9		T54	1		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	10		T25	1		T186	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	9		T49	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	18		T133	11		T32	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T50	1		T140	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	1		T229	6		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1443	1			T1	1		T2	13		T4	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T50	1		T133	1		T31	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T254	9		T161	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T230	17		T227	10		T255	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T51	13		T240	10		T263	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	2		T56	2		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T177	8		T65	9		T252	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	11		T177	2		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T154	4		T49	19		T65	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	3		T136	9		T18	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	8		T166	17		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T33	12		T151	5		T264	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T141	9		T28	2		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	12		T131	2		T144	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	7		T54	11		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	6		T25	15		T186	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T131	6		T109	10		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	6		T32	14		T167	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	7		T56	4		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T25	13		T229	2		T108	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	11		T54	6		T55	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T135	11		T16	1		T144	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2