Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22363

1

T1

1

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3779

1

T2

40

T7

6

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20250

1

T2

51

T3

12

T5

235

auto[1]

5892

1

T1

1

T2

24

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T269	1		-	-		-	-
values[0]	119	1			T7	6		T108	31		T234	1
values[1]	700	1			T50	8		T54	12		T35	20
values[2]	775	1			T15	2		T32	21		T135	23
values[3]	737	1			T134	8		T54	7		T140	2
values[4]	877	1			T7	24		T9	6		T140	1
values[5]	2937	1			T1	1		T2	40		T4	18
values[6]	634	1			T12	1		T51	8		T133	11
values[7]	937	1			T51	7		T56	5		T33	2
values[8]	468	1			T133	1		T177	9		T65	27
values[9]	1098	1			T7	5		T50	1		T56	3
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1063	1			T7	6		T50	8		T54	12
values[1]	766	1			T140	2		T15	2		T33	23
values[2]	794	1			T134	8		T54	7		T140	1
values[3]	2934	1			T1	1		T2	16		T4	18
values[4]	715	1			T2	24		T12	1		T133	23
values[5]	808	1			T51	15		T27	5		T28	18
values[6]	738	1			T133	1		T56	5		T28	4
values[7]	419	1			T131	15		T177	9		T136	33
values[8]	842	1			T56	3		T142	3		T25	34
values[9]	200	1			T7	5		T50	1		T145	12
minimum	16863	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T50	8		T35	9		T32	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T7	4		T54	12		T32	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	2		T135	12		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T140	2		T33	13		T266	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T54	7		T131	3		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T134	1		T140	1		T131	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T1	1		T4	2		T7	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	8		T42	13		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T133	2		T49	2		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	12		T12	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T51	15		T17	3		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T27	1		T28	11		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T56	5		T144	12		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T133	1		T28	3		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T177	9		T136	10		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T131	7		T136	10		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T56	3		T25	20		T154	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T142	1		T25	14		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T7	1		T145	1		T204	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T50	1		T206	9		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16736	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T159	1		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T35	11		T32	10		T49	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	2		T32	6		T108	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T135	11		T238	12		T186	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	10		T266	10		T188	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	2		T224	14		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	7		T131	9		T142	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T4	16		T7	17		T9	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	8		T42	11		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	21		T49	13		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	12		T134	4		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	2		T138	9		T106	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	4		T28	7		T80	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	14		T236	12		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T28	1		T33	1		T65	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	2		T155	14		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	8		T136	11		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T154	2		T144	11		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T142	2		T65	9		T229	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T7	4		T145	11		T204	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T206	7		T272	4		T273	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T159	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T234	1		T34	9		T274	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T7	4		T108	14		T275	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	8		T35	9		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T54	12		T150	11		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	2		T135	12		T238	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	15		T173	14		T259	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T54	7		T131	3		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T134	1		T140	2		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	7		T9	4		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T140	1		T42	13		T131	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	1		T4	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	20		T28	11		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T51	8		T133	1		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T134	1		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T51	7		T56	5		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T33	1		T80	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T177	9		T136	10		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T133	1		T65	15		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	1		T56	3		T25	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T50	1		T131	7		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T34	4		T274	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T7	2		T108	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	11		T32	10		T49	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	12		T237	4		T157	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	11		T238	12		T138	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T32	6		T173	11		T259	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T131	2		T186	13		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T134	7		T33	11		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	17		T9	2		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T42	11		T131	9		T142	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T4	16		T10	27		T11	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	20		T28	7		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T133	10		T49	13		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T134	4		T27	4		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T144	14		T236	12		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	1		T80	5		T167	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T136	2		T155	14		T205	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T65	12		T136	11		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	4		T154	2		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T131	8		T142	2		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T50	1		T35	12		T32	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	3		T54	1		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	1		T135	12		T238	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T140	2		T33	11		T266	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T54	1		T131	3		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T134	8		T140	1		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T1	1		T4	18		T7	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	9		T42	12		T144	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T133	23		T49	15		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	13		T12	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T51	2		T17	4		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T27	5		T28	9		T80	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T56	1		T144	15		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T133	1		T28	2		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T177	1		T136	3		T155	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	9		T136	12		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T56	1		T25	2		T154	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T142	3		T25	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T7	5		T145	12		T204	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T50	1		T206	8		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T159	2		T271	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T50	7		T35	8		T32	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	3		T54	11		T32	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T135	11		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	12		T266	10		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	6		T131	2		T224	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T131	6		T137	14		T252	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T7	6		T9	2		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	7		T42	12		T144	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	14		T186	11		T109	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	11		T141	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	13		T17	1		T138	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	9		T186	10		T187	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T56	4		T144	11		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	2		T65	4		T167	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T177	8		T136	9		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T131	6		T136	9		T246	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T56	2		T25	18		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T25	13		T65	9		T229	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T204	14		T175	8		T276	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T206	8		T272	3		T273	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T234	1		T34	10		T274	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T7	3		T108	18		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	1		T35	12		T32	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	1		T150	13		T237	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	1		T135	12		T238	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T32	7		T173	12		T259	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T54	1		T131	3		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	8		T140	2		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	18		T9	4		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T140	1		T42	12		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	1		T4	18		T10	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	22		T28	9		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T51	1		T133	11		T49	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	1		T134	5		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T51	1		T56	1		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T33	2		T80	6		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T177	1		T136	3		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T133	1		T65	14		T136	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T7	5		T56	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T50	1		T131	9		T142	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T34	3		T274	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T7	3		T108	13		T275	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	7		T35	8		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	11		T150	10		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T135	11		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T32	14		T173	13		T188	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T54	6		T131	2		T186	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T33	12		T137	14		T252	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	6		T9	2		T249	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T42	12		T131	6		T109	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T55	13		T38	26		T30	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	18		T28	9		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T51	7		T136	14		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T141	9		T28	2		T187	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	6		T56	4		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T167	8		T156	14		T204	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T177	8		T136	9		T248	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	13		T136	9		T246	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T56	2		T25	18		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T131	6		T25	13		T229	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2