Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22243

1

T1

1

T2

59

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3899

1

T2

16

T9

6

T50

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19973

1

T2

75

T3

12

T5

235

auto[1]

6169

1

T1

1

T4

18

T9

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T256	1		T21	4		T277	5
values[0]	66	1			T278	13		T34	13		T279	14
values[1]	676	1			T134	5		T28	4		T177	9
values[2]	731	1			T51	7		T133	12		T35	20
values[3]	790	1			T9	6		T131	16		T32	22
values[4]	2945	1			T1	1		T4	18		T7	6
values[5]	858	1			T2	16		T50	1		T140	1
values[6]	597	1			T133	1		T56	3		T131	15
values[7]	665	1			T7	24		T12	1		T154	7
values[8]	620	1			T133	11		T54	7		T140	1
values[9]	1323	1			T2	24		T7	5		T50	8
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	966	1			T134	5		T142	11		T25	14
values[1]	740	1			T51	7		T133	12		T35	20
values[2]	732	1			T9	6		T238	24		T16	4
values[3]	3011	1			T1	1		T2	16		T4	18
values[4]	798	1			T50	1		T140	1		T131	15
values[5]	613	1			T12	1		T133	1		T56	3
values[6]	761	1			T7	24		T140	1		T25	4
values[7]	564	1			T133	11		T177	3		T48	1
values[8]	851	1			T2	24		T7	5		T50	8
values[9]	247	1			T140	1		T42	24		T186	22
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T134	1		T25	14		T28	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T142	1		T136	10		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T133	1		T35	9		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T51	7		T131	7		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T238	12		T16	3		T65	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	4		T49	1		T224	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	1		T4	2		T7	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	8		T54	12		T25	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T131	7		T141	10		T33	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T50	1		T140	1		T136	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T133	1		T56	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	1		T17	3		T198	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	7		T154	5		T135	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T140	1		T25	4		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	1		T136	10		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T133	1		T177	3		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	12		T7	1		T54	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T50	8		T134	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T186	12		T265	1		T280	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	1		T42	13		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T134	4		T28	1		T155	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	10		T136	2		T236	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T133	11		T35	11		T80	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T131	9		T28	7		T32	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T238	12		T16	1		T65	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	2		T224	14		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T4	16		T7	2		T10	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	8		T33	1		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T131	8		T33	11		T266	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T136	12		T53	14		T204	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T31	8		T206	7		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T145	11		T17	2		T207	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	17		T154	2		T135	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T105	8		T200	8		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T136	11		T167	1		T248	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T133	10		T236	14		T196	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	12		T7	4		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	7		T142	2		T49	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T186	10		T280	5		T162	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T42	11		T188	8		T225	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T21	3		T277	1		T281	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T278	7		T34	9		T279	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T134	1		T28	3		T177	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T138	15		T252	9		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T133	1		T35	9		T25	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	7		T142	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T80	1		T238	12		T65	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	4		T131	7		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T1	1		T4	2		T7	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T54	12		T25	16		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T141	10		T33	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	8		T50	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T133	1		T56	3		T131	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T145	1		T17	3		T53	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	7		T12	1		T154	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T232	1		T53	2		T256	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T54	7		T48	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	1		T140	1		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	12		T7	1		T56	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	472	1			T50	8		T134	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T21	1		T277	4		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T278	6		T34	4		T279	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T134	4		T28	1		T167	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T138	9		T252	2		T249	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T133	11		T35	11		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T142	10		T28	7		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T80	5		T238	12		T65	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	2		T131	9		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T4	16		T7	2		T10	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T33	1		T49	13		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T33	1		T266	10		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	8		T136	12		T204	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	8		T31	8		T33	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	11		T17	2		T53	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	17		T154	2		T186	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T200	8		T150	14		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T135	11		T186	11		T205	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	10		T236	14		T237	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	12		T7	4		T27	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T134	7		T42	11		T142	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T134	5		T25	1		T28	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T142	11		T136	3		T236	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T133	12		T35	12		T80	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T51	1		T131	10		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T238	13		T16	3		T65	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	4		T49	1		T224	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T1	1		T4	18		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	9		T54	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	9		T141	1		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T50	1		T140	1		T136	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T133	1		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	12		T17	4		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	18		T154	3		T135	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T140	1		T25	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	1		T136	12		T167	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T133	11		T177	1		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	13		T7	5		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T50	1		T134	8		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T186	11		T265	1		T280	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T140	1		T42	12		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	13		T28	2		T177	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T136	9		T167	12		T138	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	8		T144	11		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	6		T131	6		T28	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T238	11		T16	1		T65	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	2		T224	19		T187	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T7	3		T51	7		T55	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	7		T54	11		T25	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T131	6		T141	9		T33	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T136	14		T53	5		T204	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T56	2		T48	1		T206	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	1		T198	16		T268	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	6		T154	4		T135	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T25	3		T105	5		T200	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	9		T156	14		T109	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T177	2		T200	7		T173	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T2	11		T54	6		T56	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T50	7		T49	19		T65	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T186	11		T162	9		T184	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T42	12		T188	13		T20	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T21	3		T277	5		T281	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T256	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T278	11		T34	10		T279	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T134	5		T28	2		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T138	10		T252	3		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T133	12		T35	12		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T51	1		T142	11		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T80	6		T238	13		T65	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	4		T131	10		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T1	1		T4	18		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	1		T25	1		T33	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	1		T33	2		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	9		T50	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T133	1		T56	1		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T145	12		T17	4		T53	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	18		T12	1		T154	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T232	1		T53	2		T256	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T54	1		T48	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T133	11		T140	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	13		T7	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T50	1		T134	8		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T21	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T278	2		T34	3		T279	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	2		T177	8		T167	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	14		T252	8		T249	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	8		T25	13		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	6		T28	9		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T238	11		T65	4		T166	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	2		T131	6		T32	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T7	3		T51	7		T55	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T54	11		T25	15		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T141	9		T262	12		T266	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	7		T136	14		T173	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T56	2		T131	6		T33	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	1		T53	5		T105	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	6		T154	4		T186	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T200	16		T150	9		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T54	6		T135	11		T156	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T25	3		T177	2		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	11		T56	4		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T50	7		T42	12		T49	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2