Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22671

1

T1

1

T2

59

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3471

1

T2

16

T7

35

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19869

1

T2

35

T3

12

T5

235

auto[1]

6273

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T234	1		-	-		-	-
values[0]	137	1			T186	32		T109	17		T207	9
values[1]	528	1			T2	16		T134	5		T15	2
values[2]	2832	1			T1	1		T2	24		T4	18
values[3]	592	1			T7	5		T56	8		T35	20
values[4]	745	1			T50	1		T133	12		T28	4
values[5]	634	1			T9	6		T140	2		T49	1
values[6]	971	1			T134	8		T42	24		T131	5
values[7]	829	1			T133	11		T154	7		T155	12
values[8]	711	1			T7	30		T51	8		T141	10
values[9]	1303	1			T12	1		T50	8		T133	1
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	764	1			T2	16		T51	7		T134	5
values[1]	2850	1			T1	1		T2	24		T4	18
values[2]	635	1			T133	12		T56	3		T35	20
values[3]	652	1			T50	1		T140	1		T25	14
values[4]	866	1			T9	6		T140	1		T42	24
values[5]	910	1			T134	8		T32	22		T154	7
values[6]	855	1			T7	6		T135	23		T49	40
values[7]	631	1			T51	8		T133	11		T141	10
values[8]	864	1			T7	24		T12	1		T50	8
values[9]	224	1			T54	12		T144	12		T136	21
minimum	16891	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T54	7		T15	2		T32	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	8		T51	7		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T1	1		T2	12		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	1		T33	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	1		T142	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T56	3		T35	9		T32	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	14		T49	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T50	1		T140	1		T28	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	13		T65	5		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	4		T140	1		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T154	5		T144	12		T224	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T134	1		T32	12		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T135	12		T49	21		T166	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	4		T236	2		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	8		T141	10		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T133	1		T48	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T50	8		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	7		T133	1		T131	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T136	10		T262	13		T204	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T54	12		T144	3		T138	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16752	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T205	1		T283	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T32	4		T33	10		T238	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	8		T134	4		T28	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T2	12		T4	16		T10	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T7	4		T33	1		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T133	11		T142	2		T27	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	11		T32	6		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T166	10		T187	21		T284	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	1		T53	14		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T42	11		T65	3		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	2		T131	2		T65	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T154	2		T144	14		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T134	7		T32	10		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	11		T49	19		T166	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	2		T236	26		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	13		T196	11		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	10		T155	14		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	8		T229	5		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	17		T131	8		T80	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T136	11		T204	11		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T144	9		T138	2		T207	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T205	9		T283	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T186	19		T109	17		T285	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T207	1		T286	5		T228	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T15	2		T32	7		T33	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	8		T134	1		T28	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T1	1		T2	12		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T51	7		T33	1		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	5		T142	2		T25	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T56	3		T35	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	1		T156	15		T187	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T50	1		T28	3		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	1		T65	5		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	4		T140	2		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T42	13		T144	12		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T134	1		T131	3		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T154	5		T166	18		T167	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	1		T155	1		T167	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T51	8		T141	10		T25	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	11		T48	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T12	1		T50	8		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T133	1		T54	12		T131	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T186	13		T285	11		T287	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T207	8		T286	7		T288	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T32	4		T33	10		T251	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	8		T134	4		T28	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T2	12		T4	16		T10	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T33	1		T145	11		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T142	12		T27	4		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	4		T35	11		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	11		T187	21		T246	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	1		T53	14		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T65	3		T17	2		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	2		T204	30		T205	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T42	11		T144	14		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	7		T131	2		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T154	2		T166	8		T167	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	10		T155	11		T167	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	11		T49	32		T173	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	19		T236	12		T186	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T31	8		T229	5		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T131	8		T80	5		T144	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T54	1		T15	1		T32	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	9		T51	1		T134	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	1		T2	13		T4	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T7	5		T33	2		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T133	12		T142	3		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T56	1		T35	12		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	1		T49	1		T166	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T50	1		T140	1		T28	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T42	12		T65	4		T17	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	4		T140	1		T131	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T154	3		T144	15		T224	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	8		T32	11		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T135	12		T49	21		T166	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	3		T236	28		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	1		T141	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	11		T48	1		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T50	1		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	18		T133	1		T131	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T136	12		T262	1		T204	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T54	1		T144	10		T138	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T205	10		T283	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T54	6		T15	1		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	7		T51	6		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T2	11		T55	13		T56	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T106	12		T260	9		T201	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T156	14		T109	10		T230	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T56	2		T35	8		T32	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T25	13		T187	14		T289	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T28	2		T53	5		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T42	12		T65	4		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	2		T131	2		T65	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T154	4		T144	11		T224	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T32	11		T136	14		T167	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T135	11		T49	19		T166	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	3		T186	10		T198	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	7		T141	9		T25	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T179	20		T230	12		T290	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T50	7		T229	2		T136	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	6		T131	6		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T136	9		T262	12		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T54	11		T144	2		T138	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T109	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T283	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T186	14		T109	1		T285	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T207	9		T286	8		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	1		T32	5		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	9		T134	5		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T1	1		T2	13		T4	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T51	1		T33	2		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	1		T142	14		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	5		T56	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T133	12		T156	1		T187	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	1		T28	2		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	1		T65	4		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	4		T140	2		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T42	12		T144	15		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T134	8		T131	3		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T154	3		T166	9		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T133	11		T155	12		T167	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T51	1		T141	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	21		T48	1		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T12	1		T50	1		T31	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T133	1		T54	1		T131	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T186	18		T109	16		T287	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T286	4		T228	6		T90	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	1		T32	6		T33	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	7		T28	9		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	11		T54	6		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T51	6		T150	10		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T56	4		T25	13		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T56	2		T35	8		T32	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T156	14		T187	14		T289	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T28	2		T53	5		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T65	4		T17	1		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	2		T204	24		T201	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T42	12		T144	11		T138	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T131	2		T32	11		T65	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T154	4		T166	17		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T167	8		T198	13		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T51	7		T141	9		T25	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	9		T186	10		T157	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T50	7		T229	2		T136	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T54	11		T131	6		T144	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2