Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19971

1

T2

35

T3

12

T5

235

auto[ADC_CTRL_FILTER_COND_OUT]

6171

1

T1

1

T2

40

T4

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19887

1

T2

51

T3

12

T5

235

auto[1]

6255

1

T1

1

T2

24

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T291	6		-	-		-	-
values[0]	76	1			T131	5		T145	12		T200	25
values[1]	531	1			T2	24		T9	6		T50	1
values[2]	839	1			T2	16		T7	5		T51	7
values[3]	739	1			T134	5		T140	1		T131	16
values[4]	700	1			T140	2		T131	15		T32	11
values[5]	661	1			T50	8		T133	12		T54	12
values[6]	897	1			T12	1		T51	8		T42	24
values[7]	776	1			T7	24		T56	5		T25	14
values[8]	708	1			T7	6		T133	12		T54	7
values[9]	3350	1			T1	1		T4	18		T10	30
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	868	1			T2	24		T7	5		T9	6
values[1]	2996	1			T1	1		T2	16		T4	18
values[2]	722	1			T134	5		T131	31		T141	10
values[3]	664	1			T133	12		T54	12		T140	2
values[4]	793	1			T32	21		T136	21		T138	11
values[5]	778	1			T7	24		T12	1		T50	8
values[6]	794	1			T133	12		T56	5		T25	14
values[7]	666	1			T7	6		T54	7		T32	22
values[8]	771	1			T35	20		T25	20		T48	7
values[9]	212	1			T56	3		T49	40		T138	24
minimum	16878	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T50	1		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	12		T9	4		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	7		T15	2		T186	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1553	1			T1	1		T2	8		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T131	14		T141	10		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	1		T177	3		T186	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	12		T140	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T133	1		T140	1		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	15		T136	10		T198	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T138	6		T173	14		T150	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T7	7		T12	1		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	13		T135	12		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T133	1		T56	5		T25	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T133	1		T238	12		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	4		T173	4		T262	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T54	7		T32	12		T138	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T236	1		T196	1		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T35	9		T25	20		T48	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T56	3		T248	4		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T49	21		T138	15		T109	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T178	1		T292	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	4		T131	2		T31	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T2	12		T9	2		T134	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T186	10		T106	12		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1132	1			T2	8		T4	16		T10	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	17		T142	2		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	4		T186	11		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T27	4		T28	1		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T133	11		T33	10		T167	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T32	6		T136	11		T188	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T138	5		T173	11		T237	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	17		T229	5		T145	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T42	11		T135	11		T155	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T133	10		T108	17		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T238	12		T49	13		T137	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	2		T293	13		T286	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	10		T138	2		T186	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T236	14		T196	11		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T35	11		T236	12		T248	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T217	12		T294	12		T283	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T49	19		T138	9		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T292	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T131	3		T145	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T200	17		T295	3		T296	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T50	1		T31	1		T177	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	12		T9	4		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T51	7		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	8		T142	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	7		T141	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	1		T140	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	1		T131	7		T32	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T140	1		T33	13		T177	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	8		T54	12		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T133	1		T167	1		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T51	8		T145	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T42	13		T137	15		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	7		T56	5		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T135	12		T238	12		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	4		T133	1		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	1		T54	7		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T56	3		T236	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1633	1			T1	1		T4	2		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T291	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T131	2		T145	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T200	8		T295	4		T296	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T31	8		T155	11		T200	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	12		T9	2		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	4		T33	1		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	8		T142	10		T28	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	9		T142	2		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	4		T188	8		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T131	8		T32	4		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T33	10		T186	11		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	1		T32	6		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	11		T167	1		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T145	19		T167	9		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T42	11		T137	13		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	17		T229	5		T167	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T135	11		T238	12		T49	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	2		T133	10		T108	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	10		T138	2		T186	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T236	14		T196	11		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1127	1			T4	16		T10	27		T11	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	5		T50	1		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T2	13		T9	4		T134	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T51	1		T15	1		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1481	1			T1	1		T2	9		T4	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T131	19		T141	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	5		T177	1		T186	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T54	1		T140	1		T27	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	12		T140	1		T33	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	7		T136	12		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T138	6		T173	12		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	18		T12	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T42	12		T135	12		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T133	11		T56	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T133	1		T238	13		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	3		T173	1		T262	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	1		T32	11		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T236	15		T196	12		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	12		T25	2		T48	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T56	1		T248	1		T217	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T49	21		T138	10		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T178	1		T292	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T131	2		T177	8		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	11		T9	2		T28	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T51	6		T15	1		T186	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T2	7		T55	13		T38	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	12		T141	9		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T177	2		T186	10		T262	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T54	11		T28	2		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T33	12		T172	9		T187	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T32	14		T136	9		T198	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	5		T173	13		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	6		T50	7		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T42	12		T135	11		T156	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	4		T25	13		T108	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T238	11		T137	14		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	3		T173	3		T262	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T54	6		T32	11		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T242	1		T251	12		T248	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	8		T25	18		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T56	2		T248	3		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T49	19		T138	14		T109	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T292	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T291	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T131	3		T145	12		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T200	9		T295	5		T296	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T50	1		T31	9		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	13		T9	4		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	5		T51	1		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	9		T142	11		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T131	10		T141	1		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	5		T140	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	1		T131	9		T32	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	1		T33	11		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	1		T54	1		T28	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	12		T167	2		T138	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T51	1		T145	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T42	12		T137	14		T155	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	18		T56	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T135	12		T238	13		T49	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	3		T133	11		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	1		T54	1		T32	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T56	1		T236	15		T196	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1501	1			T1	1		T4	18		T10	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T131	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T200	16		T295	2		T296	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T177	8		T200	7		T249	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	11		T9	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T51	6		T15	1		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	7		T28	9		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	6		T141	9		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T262	16		T188	13		T151	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	6		T32	6		T136	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T33	12		T177	2		T186	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	7		T54	11		T28	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T138	5		T179	7		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	7		T167	12		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T42	12		T137	14		T173	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	6		T56	4		T25	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T135	11		T238	11		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	3		T108	13		T173	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	6		T32	11		T138	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T56	2		T242	1		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1259	1			T55	13		T35	8		T38	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2