Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22656

1

T1

1

T2

59

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3486

1

T2

16

T7

5

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20262

1

T2

35

T3

12

T5

235

auto[1]

5880

1

T1

1

T2

40

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T140	1		T236	13		T297	14
values[0]	33	1			T227	11		T228	7		T241	15
values[1]	585	1			T2	24		T7	11		T133	1
values[2]	797	1			T134	8		T131	16		T177	3
values[3]	766	1			T51	7		T134	5		T56	3
values[4]	790	1			T133	12		T142	11		T32	22
values[5]	2808	1			T1	1		T2	16		T4	18
values[6]	527	1			T7	24		T9	6		T140	1
values[7]	736	1			T50	1		T133	11		T141	10
values[8]	964	1			T54	12		T15	2		T48	1
values[9]	1079	1			T12	1		T50	8		T56	5
minimum	16859	1			T2	35		T3	12		T5	235

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	636	1			T2	24		T7	11		T133	1
values[1]	873	1			T134	8		T131	16		T177	3
values[2]	805	1			T51	7		T133	12		T134	5
values[3]	2900	1			T1	1		T4	18		T10	30
values[4]	588	1			T2	16		T51	8		T54	7
values[5]	513	1			T7	24		T9	6		T140	1
values[6]	863	1			T50	1		T133	11		T141	10
values[7]	925	1			T50	8		T54	12		T15	2
values[8]	873	1			T12	1		T56	5		T25	14
values[9]	146	1			T140	1		T229	8		T240	8
minimum	17020	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	12		T7	4		T131	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T133	1		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T131	7		T177	3		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T134	1		T166	1		T138	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T56	3		T171	1		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T51	7		T133	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T1	1		T4	2		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	12		T80	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T54	7		T140	1		T35	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	8		T51	8		T28	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	7		T28	3		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	4		T140	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T145	2		T231	4		T293	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	1		T133	1		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T50	8		T54	12		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	2		T232	1		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T56	5		T25	14		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T27	1		T238	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T234	1		T235	1		T298	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T140	1		T229	3		T240	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16778	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T250	3		T216	11		T267	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	12		T7	2		T131	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	4		T131	2		T49	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T131	9		T144	14		T186	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T134	7		T166	10		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	2		T138	5		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T133	11		T134	4		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T4	16		T10	27		T11	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	10		T80	5		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T35	11		T42	11		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	8		T28	7		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	17		T28	1		T32	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	2		T31	8		T33	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	22		T231	1		T293	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T133	10		T32	6		T49	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T135	11		T144	9		T105	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T236	14		T179	14		T206	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T236	12		T138	2		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	4		T238	12		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T235	11		T298	2		T69	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T229	5		T240	3		T299	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T154	2		T49	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T216	9		T267	3		T300	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T236	1		T297	8		T234	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T140	1		T240	5		T246	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T227	11		T228	7		T241	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	12		T7	4		T131	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T7	1		T133	1		T131	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T131	7		T177	3		T144	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T134	1		T65	10		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T56	3		T138	6		T204	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T51	7		T134	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T142	1		T177	9		T48	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	1		T32	12		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T1	1		T4	2		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	8		T51	8		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	7		T33	1		T200	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	4		T140	1		T33	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	3		T32	7		T145	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	1		T133	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T54	12		T135	12		T144	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	2		T48	1		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T50	8		T56	5		T25	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T27	1		T238	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16735	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T236	12		T297	6		T235	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T240	3		T246	12		T90	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T241	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	12		T7	2		T131	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	4		T131	2		T49	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T131	9		T144	14		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	7		T65	9		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T138	5		T204	11		T266	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	4		T145	8		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	10		T16	1		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	11		T32	10		T80	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T4	16		T10	27		T11	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	8		T28	7		T155	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T7	17		T33	1		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T9	2		T33	11		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	1		T32	4		T145	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	10		T31	8		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T135	11		T144	9		T105	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T49	13		T236	14		T186	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T138	2		T18	7		T149	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T27	4		T238	12		T229	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	13		T7	3		T131	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	5		T133	1		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T131	10		T177	1		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T134	8		T166	11		T138	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T56	1		T171	1		T136	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T51	1		T133	12		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T1	1		T4	18		T10	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T32	11		T80	6		T155	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T54	1		T140	1		T35	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	9		T51	1		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	18		T28	2		T32	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	4		T140	1		T31	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T145	24		T231	4		T293	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T50	1		T133	11		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T50	1		T54	1		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	1		T232	1		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T56	1		T25	1		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T27	5		T238	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T234	1		T235	12		T298	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T140	1		T229	6		T240	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16916	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T250	3		T216	15		T267	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	11		T7	3		T131	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T131	2		T49	19		T65	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T131	6		T177	2		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T138	14		T106	12		T173	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T56	2		T136	9		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	6		T137	14		T166	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T55	13		T38	26		T25	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	11		T53	5		T224	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T54	6		T35	8		T42	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	7		T51	7		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	6		T28	2		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	2		T33	12		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T231	1		T293	9		T175	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	9		T32	14		T186	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T50	7		T54	11		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	1		T262	12		T179	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T56	4		T25	13		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T238	11		T17	1		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T298	2		T69	1		T301	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T229	2		T240	4		T246	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T154	4		T65	4		T208	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T216	5		T267	2		T302	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T236	13		T297	7		T234	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T140	1		T240	4		T246	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T227	1		T228	1		T241	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	13		T7	3		T131	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	5		T133	1		T131	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T131	10		T177	1		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	8		T65	10		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	1		T138	6		T204	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T51	1		T134	5		T145	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T142	11		T177	1		T48	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T133	12		T32	11		T80	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T1	1		T4	18		T10	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	9		T51	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	18		T33	2		T200	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	4		T140	1		T33	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T28	2		T32	5		T145	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	1		T133	11		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T54	1		T135	12		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	1		T48	1		T49	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T50	1		T56	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	1		T27	5		T238	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	35		T3	12		T5	235
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T297	7		T298	2		T303	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T240	4		T246	17		T90	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T227	10		T228	6		T241	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	11		T7	3		T131	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T131	2		T49	19		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T131	6		T177	2		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	9		T248	2		T264	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T56	2		T138	5		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	6		T138	14		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T177	8		T48	1		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T32	11		T137	14		T166	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T54	6		T55	13		T35	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	7		T51	7		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	6		T200	16		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	2		T33	12		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	2		T32	6		T293	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	9		T32	14		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T54	11		T135	11		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T186	18		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T50	7		T56	4		T25	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T238	11		T229	2		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2