Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26142

1

T1

1

T2

75

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22503

1

T1

1

T2

35

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3639

1

T2

40

T7

6

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19920

1

T2

75

T3

12

T5

227

auto[1]

6222

1

T1

1

T4

18

T5

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22000

1

T1

1

T2

55

T3

12

auto[1]

4142

1

T2

20

T4

16

T7

23

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	428	1			T5	8		T8	1		T45	1
values[0]	138	1			T2	24		T33	2		T138	13
values[1]	887	1			T7	24		T134	5		T28	4
values[2]	2885	1			T1	1		T2	16		T4	18
values[3]	664	1			T140	1		T35	20		T236	13
values[4]	807	1			T9	6		T50	1		T51	8
values[5]	757	1			T134	8		T131	5		T141	10
values[6]	652	1			T131	31		T25	14		T32	43
values[7]	754	1			T54	7		T42	24		T142	3
values[8]	539	1			T133	11		T142	11		T15	2
values[9]	1166	1			T7	5		T133	12		T54	12
minimum	16465	1			T2	35		T3	12		T5	227

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1090	1			T2	24		T7	24		T12	1
values[1]	2876	1			T1	1		T2	16		T4	18
values[2]	916	1			T9	6		T51	8		T35	20
values[3]	651	1			T50	1		T133	1		T134	8
values[4]	748	1			T131	15		T141	10		T28	18
values[5]	561	1			T54	7		T131	16		T25	14
values[6]	735	1			T42	24		T142	3		T15	2
values[7]	570	1			T133	11		T142	11		T232	1
values[8]	930	1			T7	5		T133	12		T54	12
values[9]	133	1			T16	4		T186	32		T105	14
minimum	16932	1			T2	35		T3	12		T5	235

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

4188

1

T2

18

T7

9

T9

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	7		T12	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	12		T134	1		T28	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T1	1		T4	2		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	8		T7	4		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T35	9		T33	13		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	4		T51	8		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T133	1		T140	1		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	1		T134	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	7		T32	15		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T141	10		T28	11		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	7		T145	1		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	7		T25	14		T49	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	13		T15	2		T65	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T142	1		T25	16		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	1		T142	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T249	6		T268	7		T179	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T133	1		T177	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T54	12		T56	3		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T16	3		T186	19		T105	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T157	3		T159	5		T302	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16755	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T304	16		T305	1		T239	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	17		T31	8		T167	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	12		T134	4		T28	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T4	16		T10	27		T11	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	8		T7	2		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T35	11		T33	10		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	2		T236	12		T145	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T131	2		T154	2		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T134	7		T238	12		T49	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T131	8		T32	6		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	7		T32	10		T137	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T131	9		T145	11		T149	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	19		T144	14		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	11		T65	3		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	2		T27	4		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	10		T142	10		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T249	5		T179	14		T280	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	4		T133	11		T53	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T136	2		T155	14		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T16	1		T186	13		T105	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T157	11		T159	2		T286	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T49	6		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T239	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T5	8		T8	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T138	11		T199	1		T206	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T2	12		T33	1		T304	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	7		T31	1		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T134	1		T28	3		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1488	1			T1	1		T4	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	8		T7	4		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T140	1		T35	9		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T236	1		T137	1		T252	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T133	1		T140	1		T56	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	4		T50	1		T51	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T131	3		T154	5		T229	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T134	1		T141	10		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T131	14		T32	15		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	14		T32	12		T144	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T42	13		T144	4		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T54	7		T142	1		T25	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	1		T142	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	12		T144	3		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T7	1		T133	1		T177	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T54	12		T56	3		T25	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16341	1			T2	35		T3	12		T5	227
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T179	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T138	2		T206	4		T258	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T2	12		T33	1		T306	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	17		T31	8		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T134	4		T28	1		T80	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T4	16		T10	27		T11	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	8		T7	2		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T35	11		T145	11		T204	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T236	12		T252	2		T217	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	10		T186	11		T108	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T238	12		T49	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T131	2		T154	2		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T134	7		T28	7		T137	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	17		T32	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	10		T144	14		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T42	11		T144	11		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T142	2		T27	4		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T133	10		T142	10		T65	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T135	11		T144	9		T195	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T7	4		T133	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T136	2		T155	14		T138	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T49	6		T17	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T7	18		T12	1		T31	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	13		T134	5		T28	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T1	1		T4	18		T10	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	9		T7	3		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T35	12		T33	11		T145	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	4		T51	1		T236	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	1		T140	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	1		T134	8		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T131	9		T32	7		T229	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T141	1		T28	9		T32	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T131	10		T145	12		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	1		T25	1		T49	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T42	12		T15	1		T65	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T142	3		T25	1		T27	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	11		T142	11		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T249	6		T268	1		T179	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T7	5		T133	12		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T54	1		T56	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T16	3		T186	14		T105	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T157	12		T159	3		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16874	1			T2	35		T3	12		T5	235
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T304	1		T305	1		T239	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	6		T167	8		T138	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	11		T28	2		T65	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T50	7		T51	6		T55	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	7		T7	3		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T35	8		T33	12		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	2		T51	7		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T56	4		T131	2		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T238	11		T136	9		T187	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	6		T32	14		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T141	9		T28	9		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T131	6		T267	2		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T54	6		T25	13		T49	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	12		T15	1		T65	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T25	15		T135	11		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T136	14		T173	3		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T249	5		T268	6		T179	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T177	2		T53	5		T106	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T54	11		T56	2		T25	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T16	1		T186	18		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T157	2		T159	4		T302	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T173	13		T151	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T304	15		T239	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T5	8		T8	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T138	3		T199	1		T206	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T2	13		T33	2		T304	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T7	18		T31	9		T32	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T134	5		T28	2		T80	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	1		T4	18		T10	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	9		T7	3		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T140	1		T35	12		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T236	13		T137	1		T252	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T133	1		T140	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	4		T50	1		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	3		T154	3		T229	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T134	8		T141	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T131	19		T32	7		T145	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	1		T32	11		T144	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T42	12		T144	12		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	1		T142	3		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T133	11		T142	11		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T135	12		T144	10		T195	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T7	5		T133	12		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T54	1		T56	1		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T2	35		T3	12		T5	227
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T179	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T138	10		T206	7		T258	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T2	11		T304	15		T306	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	6		T32	6		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	2		T65	9		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T50	7		T51	6		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	7		T7	3		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	8		T204	14		T150	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T252	8		T201	7		T307	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T56	4		T33	12		T186	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	2		T51	7		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	2		T154	4		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	9		T28	9		T137	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T131	12		T32	14		T204	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	13		T32	11		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	12		T144	3		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T54	6		T25	15		T49	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	1		T65	4		T198	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	11		T144	2		T249	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T177	2		T16	1		T136	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T54	11		T56	2		T25	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21954

1

T1

1

T2

57

T3

12

auto[1]

auto[0]

4188

1

T2

18

T7

9

T9

2