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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.12


Total test records in report: 919
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T793 /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4288685486 Mar 28 01:04:41 PM PDT 24 Mar 28 01:15:55 PM PDT 24 400857882442 ps
T794 /workspace/coverage/default/46.adc_ctrl_poweron_counter.1375114314 Mar 28 01:08:29 PM PDT 24 Mar 28 01:08:32 PM PDT 24 3124515164 ps
T795 /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.597537655 Mar 28 01:04:59 PM PDT 24 Mar 28 01:06:57 PM PDT 24 194422478903 ps
T796 /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1242071407 Mar 28 01:04:27 PM PDT 24 Mar 28 01:06:33 PM PDT 24 198496804370 ps
T71 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3549875831 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:20 PM PDT 24 809509529 ps
T61 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3652823381 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 4946828174 ps
T84 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1358658656 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:21 PM PDT 24 509593209 ps
T124 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.580858810 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:29 PM PDT 24 542762009 ps
T66 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1844800250 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:40 PM PDT 24 8286955013 ps
T83 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.715792078 Mar 28 12:32:08 PM PDT 24 Mar 28 12:32:10 PM PDT 24 485120992 ps
T125 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3593136606 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:16 PM PDT 24 416961878 ps
T797 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.577036828 Mar 28 12:32:07 PM PDT 24 Mar 28 12:32:08 PM PDT 24 431059790 ps
T62 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4176637177 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:20 PM PDT 24 2415432662 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.199661471 Mar 28 12:31:43 PM PDT 24 Mar 28 12:31:45 PM PDT 24 894466193 ps
T798 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3701731542 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:24 PM PDT 24 430402293 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.391750853 Mar 28 12:32:07 PM PDT 24 Mar 28 12:32:11 PM PDT 24 407254518 ps
T130 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2556120703 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:43 PM PDT 24 673034784 ps
T67 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.540632757 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 4614612812 ps
T77 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2368380733 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:33 PM PDT 24 533776944 ps
T97 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.349283775 Mar 28 12:32:07 PM PDT 24 Mar 28 12:32:09 PM PDT 24 538581888 ps
T64 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3555402877 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:42 PM PDT 24 523853387 ps
T78 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2479128892 Mar 28 12:32:07 PM PDT 24 Mar 28 12:32:10 PM PDT 24 522434963 ps
T63 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.450556233 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:47 PM PDT 24 4637131759 ps
T98 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3275469534 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:13 PM PDT 24 409104873 ps
T79 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.848778197 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:12 PM PDT 24 781328532 ps
T799 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1153302303 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:27 PM PDT 24 455131441 ps
T800 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1049199902 Mar 28 12:31:43 PM PDT 24 Mar 28 12:31:45 PM PDT 24 387263463 ps
T99 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2142202966 Mar 28 12:31:46 PM PDT 24 Mar 28 12:31:49 PM PDT 24 556513734 ps
T68 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1590165711 Mar 28 12:31:38 PM PDT 24 Mar 28 12:31:44 PM PDT 24 8479992595 ps
T801 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1466822166 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:21 PM PDT 24 421596989 ps
T85 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1532446538 Mar 28 12:32:05 PM PDT 24 Mar 28 12:32:25 PM PDT 24 7937290962 ps
T802 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1844662788 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:23 PM PDT 24 572865318 ps
T803 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1540181762 Mar 28 12:32:13 PM PDT 24 Mar 28 12:32:17 PM PDT 24 479271376 ps
T112 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2679508996 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:20 PM PDT 24 466721925 ps
T126 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.26497681 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:22 PM PDT 24 2458929367 ps
T804 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.620811933 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:25 PM PDT 24 516515729 ps
T805 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1171175038 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:22 PM PDT 24 490099361 ps
T806 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1703350976 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:17 PM PDT 24 439171405 ps
T807 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1718234500 Mar 28 12:32:29 PM PDT 24 Mar 28 12:32:31 PM PDT 24 365446685 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1363458356 Mar 28 12:32:03 PM PDT 24 Mar 28 12:32:09 PM PDT 24 3898475941 ps
T72 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3472852801 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:47 PM PDT 24 4454290947 ps
T808 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2925231971 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:42 PM PDT 24 329928615 ps
T809 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3936297851 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:14 PM PDT 24 516414082 ps
T810 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1143151325 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 535238630 ps
T128 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.691131858 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:39 PM PDT 24 2301358271 ps
T811 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.666263627 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:41 PM PDT 24 1111970583 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3213970582 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:20 PM PDT 24 386227339 ps
T335 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3296202000 Mar 28 12:32:05 PM PDT 24 Mar 28 12:32:28 PM PDT 24 8398541343 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3579294290 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:41 PM PDT 24 1124741074 ps
T129 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3305398410 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:29 PM PDT 24 4545664727 ps
T813 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1323954712 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 446422452 ps
T814 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2484245157 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:21 PM PDT 24 529542054 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2189561360 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:39 PM PDT 24 634404659 ps
T114 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3887200954 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 653692744 ps
T816 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.723975309 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:23 PM PDT 24 713455990 ps
T817 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3042733555 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:26 PM PDT 24 9409255936 ps
T115 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3864165263 Mar 28 12:31:57 PM PDT 24 Mar 28 12:31:58 PM PDT 24 501892525 ps
T818 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3161269689 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 307366115 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4132537620 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:19 PM PDT 24 303981723 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3902008985 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:33 PM PDT 24 8309344133 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.275950540 Mar 28 12:31:34 PM PDT 24 Mar 28 12:32:01 PM PDT 24 20814013312 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.235394448 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:43 PM PDT 24 342500187 ps
T822 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2859292386 Mar 28 12:31:47 PM PDT 24 Mar 28 12:31:49 PM PDT 24 510137530 ps
T117 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2981158513 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:54 PM PDT 24 26997712497 ps
T823 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1178581731 Mar 28 12:32:08 PM PDT 24 Mar 28 12:32:11 PM PDT 24 767629564 ps
T824 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.593871683 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:12 PM PDT 24 338378133 ps
T825 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1150773763 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:14 PM PDT 24 509200761 ps
T826 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1528884062 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2218040203 ps
T86 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2503982792 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:35 PM PDT 24 4257641411 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2007120781 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:12 PM PDT 24 679354602 ps
T828 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2942330185 Mar 28 12:31:55 PM PDT 24 Mar 28 12:32:22 PM PDT 24 26377101914 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3283812917 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:13 PM PDT 24 339583295 ps
T830 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1966989575 Mar 28 12:32:06 PM PDT 24 Mar 28 12:32:08 PM PDT 24 668827165 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2341112336 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2287280820 ps
T832 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2849846286 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:12 PM PDT 24 433937622 ps
T833 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3823657290 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:26 PM PDT 24 516570256 ps
T834 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2670216773 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:30 PM PDT 24 4589643732 ps
T835 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3298481978 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:14 PM PDT 24 528376696 ps
T836 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2550670861 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:31 PM PDT 24 4610689250 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1279827238 Mar 28 12:31:54 PM PDT 24 Mar 28 12:32:26 PM PDT 24 25831450172 ps
T838 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.382379516 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:18 PM PDT 24 4292586409 ps
T839 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1272570445 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:17 PM PDT 24 671592391 ps
T840 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3517747877 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:34 PM PDT 24 4176105223 ps
T841 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4280759158 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:38 PM PDT 24 586641639 ps
T842 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3712085412 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 514651738 ps
T843 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1662842471 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:16 PM PDT 24 427512013 ps
T844 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4268622971 Mar 28 12:32:04 PM PDT 24 Mar 28 12:32:08 PM PDT 24 2609952688 ps
T845 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3875521753 Mar 28 12:32:05 PM PDT 24 Mar 28 12:32:06 PM PDT 24 283760538 ps
T846 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3727896302 Mar 28 12:32:00 PM PDT 24 Mar 28 12:32:01 PM PDT 24 482160905 ps
T847 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3567578994 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:40 PM PDT 24 389203751 ps
T336 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3126532615 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:24 PM PDT 24 5310903559 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2752042715 Mar 28 12:31:53 PM PDT 24 Mar 28 12:31:59 PM PDT 24 1192475272 ps
T848 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3611176519 Mar 28 12:32:07 PM PDT 24 Mar 28 12:32:10 PM PDT 24 472468243 ps
T849 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3792270963 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:24 PM PDT 24 350531933 ps
T119 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.889679421 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:28 PM PDT 24 341093860 ps
T850 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.499785338 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:19 PM PDT 24 824102439 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1022349235 Mar 28 12:31:40 PM PDT 24 Mar 28 12:31:42 PM PDT 24 522623726 ps
T851 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.811452018 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 329731780 ps
T852 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3317019235 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:23 PM PDT 24 464770509 ps
T853 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2288405669 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:22 PM PDT 24 470311997 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2306145737 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2445736523 ps
T855 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3463208919 Mar 28 12:32:05 PM PDT 24 Mar 28 12:32:07 PM PDT 24 321765242 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1600028402 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:21 PM PDT 24 287161551 ps
T857 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1348428337 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:37 PM PDT 24 372819814 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2205276726 Mar 28 12:31:54 PM PDT 24 Mar 28 12:31:56 PM PDT 24 406216496 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3904912949 Mar 28 12:32:05 PM PDT 24 Mar 28 12:32:10 PM PDT 24 4763518264 ps
T121 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.708079503 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:39 PM PDT 24 832021191 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.84546623 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:46 PM PDT 24 924202182 ps
T860 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2836553242 Mar 28 12:32:08 PM PDT 24 Mar 28 12:32:12 PM PDT 24 375918639 ps
T861 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.381113217 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:26 PM PDT 24 369751103 ps
T123 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2643180755 Mar 28 12:31:33 PM PDT 24 Mar 28 12:31:35 PM PDT 24 501225543 ps
T862 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1212825024 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:32 PM PDT 24 8435880784 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2295836289 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:14 PM PDT 24 473400667 ps
T864 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.906997569 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:42 PM PDT 24 409934230 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3511365847 Mar 28 12:31:39 PM PDT 24 Mar 28 12:31:42 PM PDT 24 323976741 ps
T866 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3986815321 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:41 PM PDT 24 4313780087 ps
T867 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.766192748 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:14 PM PDT 24 313736979 ps
T868 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2432781845 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:21 PM PDT 24 437822274 ps
T869 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.761675317 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:13 PM PDT 24 570245891 ps
T870 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1635304924 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:23 PM PDT 24 576229750 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1709514843 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:23 PM PDT 24 508650145 ps
T872 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2172012081 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 312578257 ps
T873 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1935160201 Mar 28 12:31:53 PM PDT 24 Mar 28 12:32:44 PM PDT 24 53156761102 ps
T874 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2773973837 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:28 PM PDT 24 375348380 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1126041442 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:39 PM PDT 24 4332580808 ps
T876 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3745222243 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2115000806 ps
T877 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2567249356 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:20 PM PDT 24 621798099 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1626189821 Mar 28 12:31:46 PM PDT 24 Mar 28 12:31:50 PM PDT 24 8989972183 ps
T879 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3396802394 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:25 PM PDT 24 288511899 ps
T880 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3460213955 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:47 PM PDT 24 8620866474 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2805058389 Mar 28 12:31:43 PM PDT 24 Mar 28 12:31:45 PM PDT 24 474713076 ps
T882 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3963784094 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:29 PM PDT 24 507335454 ps
T883 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3237344440 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 538602395 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.7285455 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:26 PM PDT 24 443008205 ps
T885 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3019529803 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:11 PM PDT 24 335753898 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.319085434 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:18 PM PDT 24 480451125 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2743782053 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:29 PM PDT 24 561472101 ps
T888 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2725499677 Mar 28 12:31:48 PM PDT 24 Mar 28 12:32:01 PM PDT 24 4406263184 ps
T889 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1534979241 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:23 PM PDT 24 310476332 ps
T890 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.842711501 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:30 PM PDT 24 7371795364 ps
T891 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1116648124 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:11 PM PDT 24 465441206 ps
T892 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1526668700 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2490284074 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2308633106 Mar 28 12:31:59 PM PDT 24 Mar 28 12:32:00 PM PDT 24 635684859 ps
T894 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.981168484 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2346646957 ps
T895 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1784247351 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:21 PM PDT 24 341022444 ps
T896 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2685909501 Mar 28 12:32:08 PM PDT 24 Mar 28 12:32:09 PM PDT 24 391878722 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3907481970 Mar 28 12:31:37 PM PDT 24 Mar 28 12:31:39 PM PDT 24 434304768 ps
T898 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2904202504 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:23 PM PDT 24 520599082 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1934091976 Mar 28 12:31:41 PM PDT 24 Mar 28 12:31:50 PM PDT 24 1982712931 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.439162869 Mar 28 12:31:48 PM PDT 24 Mar 28 12:31:49 PM PDT 24 387437579 ps
T901 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1180403071 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:37 PM PDT 24 2794141571 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3385188998 Mar 28 12:31:35 PM PDT 24 Mar 28 12:31:38 PM PDT 24 1133917425 ps
T903 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2917609676 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:22 PM PDT 24 287443838 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1504737895 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:37 PM PDT 24 8472508666 ps
T905 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4028242283 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:25 PM PDT 24 525245194 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3883569393 Mar 28 12:31:46 PM PDT 24 Mar 28 12:31:47 PM PDT 24 534646249 ps
T907 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2267289987 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:47 PM PDT 24 5683736007 ps
T908 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3040744888 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:13 PM PDT 24 481695080 ps
T909 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4169403832 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:24 PM PDT 24 369790608 ps
T910 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3790646769 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:18 PM PDT 24 392389669 ps
T911 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2348174572 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:28 PM PDT 24 485687540 ps
T912 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1232842979 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:24 PM PDT 24 485066261 ps
T913 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.654019887 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:11 PM PDT 24 320362266 ps
T914 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3457225847 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:27 PM PDT 24 560650476 ps
T915 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.886083650 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:20 PM PDT 24 338479961 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.820910362 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:29 PM PDT 24 582570181 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3139390988 Mar 28 12:31:34 PM PDT 24 Mar 28 12:31:41 PM PDT 24 4594079814 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3205494787 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:14 PM PDT 24 624224206 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.208486616 Mar 28 12:31:36 PM PDT 24 Mar 28 12:31:40 PM PDT 24 1303872096 ps

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.166224033
Short name T2
Test name
Test status
Simulation time 371261723147 ps
CPU time 188.72 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:11:50 PM PDT 24
Peak memory 201948 kb
Host smart-5946a9f5-67ba-43eb-b1db-3b643fe53aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166224033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
166224033
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3555913395
Short name T15
Test name
Test status
Simulation time 122192098841 ps
CPU time 102.03 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:08:17 PM PDT 24
Peak memory 210632 kb
Host smart-d9e1020c-f15e-4702-aaa7-acc18a764cb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555913395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3555913395
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3384701443
Short name T50
Test name
Test status
Simulation time 471859132025 ps
CPU time 60.92 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:05:23 PM PDT 24
Peak memory 201880 kb
Host smart-bbd86c31-c84a-4390-98ab-2a497b642cda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384701443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3384701443
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3158743380
Short name T58
Test name
Test status
Simulation time 105847177416 ps
CPU time 353.65 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:13:25 PM PDT 24
Peak memory 202268 kb
Host smart-3a7de237-db35-4d27-986c-9aeae010b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158743380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3158743380
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2790766729
Short name T138
Test name
Test status
Simulation time 575030365857 ps
CPU time 160.07 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 201880 kb
Host smart-54cc0734-a667-451b-99e3-11c8739fcff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790766729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2790766729
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.857059304
Short name T131
Test name
Test status
Simulation time 513968183301 ps
CPU time 1221.37 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 201876 kb
Host smart-8edcb6d6-5d64-4bf6-9d96-accb0e7eafbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857059304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.857059304
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.334839089
Short name T7
Test name
Test status
Simulation time 485074358056 ps
CPU time 1181.99 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:24:28 PM PDT 24
Peak memory 201904 kb
Host smart-3a6fd895-f0ed-4caf-b61a-b45443c96459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334839089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.334839089
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2125992245
Short name T186
Test name
Test status
Simulation time 498739858201 ps
CPU time 291.14 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:11:47 PM PDT 24
Peak memory 201988 kb
Host smart-17255458-37a6-427c-be5b-b9f5a37447eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125992245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2125992245
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3818763802
Short name T48
Test name
Test status
Simulation time 392936203640 ps
CPU time 375.26 seconds
Started Mar 28 01:05:16 PM PDT 24
Finished Mar 28 01:11:31 PM PDT 24
Peak memory 218676 kb
Host smart-42b621e4-ff1a-45ac-a2f9-132257e2a5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818763802 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3818763802
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1889631490
Short name T167
Test name
Test status
Simulation time 556560243873 ps
CPU time 894.93 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:19:17 PM PDT 24
Peak memory 201880 kb
Host smart-4081c776-0ed6-4697-a435-2f9c959e6f32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889631490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1889631490
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.823186587
Short name T49
Test name
Test status
Simulation time 781413959636 ps
CPU time 111.82 seconds
Started Mar 28 01:06:36 PM PDT 24
Finished Mar 28 01:08:29 PM PDT 24
Peak memory 201908 kb
Host smart-b35d264b-5a60-42eb-bcfc-1893669bea43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823186587 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.823186587
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.391750853
Short name T76
Test name
Test status
Simulation time 407254518 ps
CPU time 3.03 seconds
Started Mar 28 12:32:07 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 201852 kb
Host smart-d65e166d-da42-4a5b-bb4e-b9e250cf6d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391750853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.391750853
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.248464732
Short name T136
Test name
Test status
Simulation time 524785353857 ps
CPU time 436.93 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 201872 kb
Host smart-3d04c5b1-a3c7-44db-8cf6-75443e3b761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248464732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.248464732
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.78903668
Short name T240
Test name
Test status
Simulation time 493522371770 ps
CPU time 1031.18 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:25:37 PM PDT 24
Peak memory 201888 kb
Host smart-d897edfe-a301-4ed5-93fd-93b289881a85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78903668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gatin
g.78903668
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1251892696
Short name T150
Test name
Test status
Simulation time 551364020810 ps
CPU time 1278.97 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 201952 kb
Host smart-05033f65-a61f-48c4-be7c-4ef6a70ced51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251892696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1251892696
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1410875934
Short name T248
Test name
Test status
Simulation time 511629510523 ps
CPU time 544.21 seconds
Started Mar 28 01:07:32 PM PDT 24
Finished Mar 28 01:16:37 PM PDT 24
Peak memory 201888 kb
Host smart-6362acae-a623-4980-b8b4-f7ef9bf674b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410875934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1410875934
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3521179887
Short name T36
Test name
Test status
Simulation time 441673094 ps
CPU time 1.6 seconds
Started Mar 28 01:04:52 PM PDT 24
Finished Mar 28 01:04:53 PM PDT 24
Peak memory 201484 kb
Host smart-7f0037a1-0093-48a9-835d-874d2f8b098f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521179887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3521179887
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3555402877
Short name T64
Test name
Test status
Simulation time 523853387 ps
CPU time 1.49 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 201560 kb
Host smart-e42744dd-fb35-4b4a-83bc-f5f58c0f7ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555402877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3555402877
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2514361851
Short name T157
Test name
Test status
Simulation time 801996313754 ps
CPU time 1412.3 seconds
Started Mar 28 01:05:20 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 202212 kb
Host smart-16f4b201-c2c5-4086-abb7-a7f5aa746882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514361851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2514361851
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3243967650
Short name T75
Test name
Test status
Simulation time 8286200380 ps
CPU time 3.58 seconds
Started Mar 28 01:03:23 PM PDT 24
Finished Mar 28 01:03:27 PM PDT 24
Peak memory 218448 kb
Host smart-c2acb42a-5ced-4676-89f4-b86af2d1b3c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243967650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3243967650
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.687299617
Short name T230
Test name
Test status
Simulation time 625673526572 ps
CPU time 693.74 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:20:15 PM PDT 24
Peak memory 201992 kb
Host smart-cc9ed058-3945-49c7-bc1d-dcaecfa6834a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687299617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.687299617
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3202577654
Short name T204
Test name
Test status
Simulation time 508111773790 ps
CPU time 556.21 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:14:34 PM PDT 24
Peak memory 201888 kb
Host smart-eb520b94-0b19-4c72-b9d9-6f493cc3d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202577654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3202577654
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1773821099
Short name T179
Test name
Test status
Simulation time 542340181108 ps
CPU time 309.28 seconds
Started Mar 28 01:08:02 PM PDT 24
Finished Mar 28 01:13:11 PM PDT 24
Peak memory 201872 kb
Host smart-699e4597-2689-4080-a7aa-f5886bd9518a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773821099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1773821099
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2327565878
Short name T11
Test name
Test status
Simulation time 490197613195 ps
CPU time 1116.8 seconds
Started Mar 28 01:03:26 PM PDT 24
Finished Mar 28 01:22:03 PM PDT 24
Peak memory 201864 kb
Host smart-16b6103e-a35c-4b83-a976-ff9f9360f394
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327565878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2327565878
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1768312544
Short name T144
Test name
Test status
Simulation time 549494932544 ps
CPU time 334.18 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:11:53 PM PDT 24
Peak memory 201956 kb
Host smart-3b4be89b-9979-484f-98de-2efd7a373c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768312544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1768312544
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3649249185
Short name T187
Test name
Test status
Simulation time 326395067298 ps
CPU time 148.54 seconds
Started Mar 28 01:08:38 PM PDT 24
Finished Mar 28 01:11:07 PM PDT 24
Peak memory 201988 kb
Host smart-81762382-e669-43ae-b7af-593e3f5fe36f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649249185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3649249185
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4091055477
Short name T283
Test name
Test status
Simulation time 536287640457 ps
CPU time 578.33 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:14:29 PM PDT 24
Peak memory 201768 kb
Host smart-da953a8d-e7f1-40a1-beb7-b6121414a2a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091055477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4091055477
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4256809861
Short name T161
Test name
Test status
Simulation time 193430606856 ps
CPU time 115.38 seconds
Started Mar 28 01:06:24 PM PDT 24
Finished Mar 28 01:08:20 PM PDT 24
Peak memory 201884 kb
Host smart-52d44118-d9fa-4aad-93e2-b1a9fcc4f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256809861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4256809861
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.6076715
Short name T236
Test name
Test status
Simulation time 330147678967 ps
CPU time 387.03 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:15:08 PM PDT 24
Peak memory 201892 kb
Host smart-251cbe65-c4a5-4f62-a368-cc57dbcb9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6076715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.6076715
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1366248589
Short name T42
Test name
Test status
Simulation time 163679673402 ps
CPU time 362.76 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:10:47 PM PDT 24
Peak memory 201908 kb
Host smart-841e0886-c7c4-4f2e-85a1-b2524b68f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366248589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1366248589
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1844800250
Short name T66
Test name
Test status
Simulation time 8286955013 ps
CPU time 4.78 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 201676 kb
Host smart-73968a68-5d5f-484c-9b2b-a49299def478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844800250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1844800250
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2156612268
Short name T207
Test name
Test status
Simulation time 485431263405 ps
CPU time 293.43 seconds
Started Mar 28 01:03:27 PM PDT 24
Finished Mar 28 01:08:22 PM PDT 24
Peak memory 201852 kb
Host smart-5710a1aa-e6b6-4e35-be8d-24b08fedc537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156612268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2156612268
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2883982217
Short name T162
Test name
Test status
Simulation time 493765249220 ps
CPU time 1124.2 seconds
Started Mar 28 01:04:52 PM PDT 24
Finished Mar 28 01:23:37 PM PDT 24
Peak memory 201864 kb
Host smart-228b9075-fe0b-4189-8a58-f80b13d10b46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883982217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2883982217
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1527319802
Short name T241
Test name
Test status
Simulation time 189718273710 ps
CPU time 130.57 seconds
Started Mar 28 01:06:21 PM PDT 24
Finished Mar 28 01:08:32 PM PDT 24
Peak memory 210304 kb
Host smart-2cf187b8-8cec-4032-83ea-7e02680c745d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527319802 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1527319802
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.502836100
Short name T158
Test name
Test status
Simulation time 612972872953 ps
CPU time 1286.29 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:24:51 PM PDT 24
Peak memory 201900 kb
Host smart-eb6bea92-a773-4dc4-86a1-d3981cd35592
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502836100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.502836100
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3364300523
Short name T282
Test name
Test status
Simulation time 572736277085 ps
CPU time 246.47 seconds
Started Mar 28 01:06:00 PM PDT 24
Finished Mar 28 01:10:06 PM PDT 24
Peak memory 201868 kb
Host smart-763d0def-fa90-4bee-ab07-27b86b7eec0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364300523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3364300523
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.556601420
Short name T292
Test name
Test status
Simulation time 534697906452 ps
CPU time 871.31 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:18:25 PM PDT 24
Peak memory 201892 kb
Host smart-1f4af2f5-fb70-48a2-aaff-738654bd560c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556601420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.556601420
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2014111899
Short name T166
Test name
Test status
Simulation time 347800683670 ps
CPU time 162.8 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 201772 kb
Host smart-9a7be5a4-5a0b-4abe-9b19-8542aebd90f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014111899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2014111899
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3040427409
Short name T45
Test name
Test status
Simulation time 98442574846 ps
CPU time 394.29 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:12:17 PM PDT 24
Peak memory 202228 kb
Host smart-bcb60bef-0da3-4912-a32e-b35a8db844e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040427409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3040427409
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3305398410
Short name T129
Test name
Test status
Simulation time 4545664727 ps
CPU time 6.55 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201784 kb
Host smart-8c287bc8-a172-4830-9e87-562a22d8617a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305398410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3305398410
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1349233000
Short name T206
Test name
Test status
Simulation time 343274570319 ps
CPU time 211.82 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:07:37 PM PDT 24
Peak memory 201824 kb
Host smart-b5a81dd2-e8cd-4120-8aa6-24cd17d9d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349233000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1349233000
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2616359638
Short name T274
Test name
Test status
Simulation time 487650702521 ps
CPU time 276.83 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 201924 kb
Host smart-3c37c796-8adc-4cb5-9c20-c890051cff2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616359638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2616359638
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.314115140
Short name T295
Test name
Test status
Simulation time 351865639455 ps
CPU time 615.03 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:14:00 PM PDT 24
Peak memory 201944 kb
Host smart-c82a2e0a-ea20-423a-867e-93266cd41c60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314115140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.314115140
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1190854687
Short name T306
Test name
Test status
Simulation time 426081760174 ps
CPU time 258.43 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 201656 kb
Host smart-0186c467-663d-4654-82eb-56b1d36caef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190854687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1190854687
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2090190144
Short name T109
Test name
Test status
Simulation time 541859070397 ps
CPU time 1252.61 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:26:54 PM PDT 24
Peak memory 201916 kb
Host smart-0751cb6f-cade-411e-86da-fe7b0146ca9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090190144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2090190144
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1006665235
Short name T183
Test name
Test status
Simulation time 515603038590 ps
CPU time 209.76 seconds
Started Mar 28 01:03:33 PM PDT 24
Finished Mar 28 01:07:03 PM PDT 24
Peak memory 201904 kb
Host smart-d889f10c-276d-42a8-a483-b4a08f215409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006665235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1006665235
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3222781369
Short name T159
Test name
Test status
Simulation time 408395587149 ps
CPU time 73.94 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:06:32 PM PDT 24
Peak memory 201888 kb
Host smart-1ab07604-6695-407d-9a3f-cd8369864eff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222781369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3222781369
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3936297851
Short name T809
Test name
Test status
Simulation time 516414082 ps
CPU time 4.71 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 217808 kb
Host smart-5c33f426-6aa2-497b-844e-1f2556456b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936297851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3936297851
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3097165909
Short name T313
Test name
Test status
Simulation time 331454572478 ps
CPU time 218.72 seconds
Started Mar 28 01:05:39 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 201888 kb
Host smart-8088bab3-4304-4644-b0f5-c60bb30564c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097165909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3097165909
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1405139496
Short name T69
Test name
Test status
Simulation time 83236197396 ps
CPU time 169.76 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 210208 kb
Host smart-615f1037-021f-4151-8c32-4d9cb4c0001f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405139496 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1405139496
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.555216682
Short name T28
Test name
Test status
Simulation time 162826070293 ps
CPU time 175.47 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:07:53 PM PDT 24
Peak memory 210504 kb
Host smart-57200db4-3653-48ae-82d8-b7f798b4eef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555216682 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.555216682
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3930534846
Short name T21
Test name
Test status
Simulation time 8511082389 ps
CPU time 18.47 seconds
Started Mar 28 01:06:00 PM PDT 24
Finished Mar 28 01:06:18 PM PDT 24
Peak memory 202108 kb
Host smart-ee8478b7-8e6a-4274-a4fa-9317a4e52018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930534846 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3930534846
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2871277263
Short name T304
Test name
Test status
Simulation time 534049866615 ps
CPU time 318.12 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 201952 kb
Host smart-18447b27-d2ef-4e53-b2c6-a7b636fcb3ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871277263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2871277263
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.4188279173
Short name T291
Test name
Test status
Simulation time 335715226148 ps
CPU time 799.99 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:17:45 PM PDT 24
Peak memory 201888 kb
Host smart-beb57a42-e963-47c9-b85b-91bad5ed5442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188279173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4188279173
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1864414741
Short name T34
Test name
Test status
Simulation time 125966884839 ps
CPU time 135.23 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:06:40 PM PDT 24
Peak memory 210584 kb
Host smart-ddd26df5-09f7-4c93-be2a-50b2630df303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864414741 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1864414741
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2028006446
Short name T254
Test name
Test status
Simulation time 175108172580 ps
CPU time 193.19 seconds
Started Mar 28 01:06:18 PM PDT 24
Finished Mar 28 01:09:31 PM PDT 24
Peak memory 201924 kb
Host smart-8e173ee8-7d74-4b0c-a5fa-7420fb9363f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028006446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2028006446
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3112268502
Short name T210
Test name
Test status
Simulation time 116070282305 ps
CPU time 611.87 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:18:38 PM PDT 24
Peak memory 202184 kb
Host smart-fe591fcc-6783-48e4-a3cd-865b91ad5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112268502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3112268502
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.287106081
Short name T303
Test name
Test status
Simulation time 550104859219 ps
CPU time 355.47 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:09:50 PM PDT 24
Peak memory 201904 kb
Host smart-8a09631b-286a-4fe1-a51c-70df36cca6a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287106081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.287106081
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3145884494
Short name T252
Test name
Test status
Simulation time 172748134433 ps
CPU time 170.89 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:06:55 PM PDT 24
Peak memory 201808 kb
Host smart-fd56ed18-18a0-4149-9fca-d1459266b1c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145884494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3145884494
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3405803540
Short name T218
Test name
Test status
Simulation time 119254858349 ps
CPU time 643.54 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:14:29 PM PDT 24
Peak memory 202200 kb
Host smart-51aeb29b-d6ef-4c4e-a67a-b7e0b5dac518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405803540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3405803540
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.244934978
Short name T269
Test name
Test status
Simulation time 492932751815 ps
CPU time 1181.42 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:26:17 PM PDT 24
Peak memory 201892 kb
Host smart-1e29e2b7-d81f-4ff4-8ab0-c94ffe93f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244934978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.244934978
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1570792430
Short name T258
Test name
Test status
Simulation time 361507297812 ps
CPU time 782.67 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:20:14 PM PDT 24
Peak memory 201904 kb
Host smart-b3417e53-7f79-4731-bde9-633a5e047a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570792430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1570792430
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1366654408
Short name T227
Test name
Test status
Simulation time 185801687339 ps
CPU time 109.48 seconds
Started Mar 28 01:08:02 PM PDT 24
Finished Mar 28 01:09:51 PM PDT 24
Peak memory 201956 kb
Host smart-cecb194f-4988-45f8-9feb-4130371e859a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366654408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1366654408
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.107366378
Short name T234
Test name
Test status
Simulation time 334956202745 ps
CPU time 837.21 seconds
Started Mar 28 01:08:39 PM PDT 24
Finished Mar 28 01:22:37 PM PDT 24
Peak memory 201960 kb
Host smart-415362e2-8430-4544-9db7-f47bc3076585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107366378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.107366378
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2503982792
Short name T86
Test name
Test status
Simulation time 4257641411 ps
CPU time 11.39 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 201860 kb
Host smart-35eb325d-4a55-42f9-b36f-3b6dee642c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503982792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2503982792
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1659011550
Short name T585
Test name
Test status
Simulation time 550897095798 ps
CPU time 519.52 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:13:05 PM PDT 24
Peak memory 201880 kb
Host smart-ea0efa72-4e2b-47af-a42c-3ad2dab4a624
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659011550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1659011550
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2415869911
Short name T253
Test name
Test status
Simulation time 374629706596 ps
CPU time 796.77 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:17:46 PM PDT 24
Peak memory 201996 kb
Host smart-b795c2dc-0b1b-4118-a2bd-b3da37a27d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415869911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2415869911
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2186186085
Short name T311
Test name
Test status
Simulation time 562169770942 ps
CPU time 309.96 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 201892 kb
Host smart-23395c1f-ea7f-428d-ade9-e1c8d8c756ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186186085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2186186085
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3006036813
Short name T211
Test name
Test status
Simulation time 83080967705 ps
CPU time 431.1 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:10:36 PM PDT 24
Peak memory 202128 kb
Host smart-07d2c5a3-2e41-4e5c-a702-2a22dca2ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006036813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3006036813
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1494983004
Short name T228
Test name
Test status
Simulation time 364290933252 ps
CPU time 880.02 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:20:43 PM PDT 24
Peak memory 201892 kb
Host smart-eb19597c-01aa-4b0f-a39f-380ea8be0169
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494983004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1494983004
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4015731184
Short name T256
Test name
Test status
Simulation time 327120408480 ps
CPU time 820.8 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:21:41 PM PDT 24
Peak memory 202012 kb
Host smart-1b1d1b4d-7cac-4271-ab1e-42dfdcf030ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015731184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4015731184
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3303267589
Short name T312
Test name
Test status
Simulation time 491198134751 ps
CPU time 191.02 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:07:14 PM PDT 24
Peak memory 201856 kb
Host smart-715ab207-0c65-49ff-9052-f2dd7966ea70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303267589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3303267589
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3990487108
Short name T53
Test name
Test status
Simulation time 366520563930 ps
CPU time 224.63 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:07:51 PM PDT 24
Peak memory 210472 kb
Host smart-fe0f4dfe-d612-4468-8200-01716906424f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990487108 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3990487108
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3639369214
Short name T246
Test name
Test status
Simulation time 534002188297 ps
CPU time 272.49 seconds
Started Mar 28 01:04:29 PM PDT 24
Finished Mar 28 01:09:01 PM PDT 24
Peak memory 201892 kb
Host smart-556c04e0-0336-47df-842f-0e323be8eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639369214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3639369214
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1895608853
Short name T219
Test name
Test status
Simulation time 114846291384 ps
CPU time 439.55 seconds
Started Mar 28 01:05:06 PM PDT 24
Finished Mar 28 01:12:26 PM PDT 24
Peak memory 202208 kb
Host smart-097b6c33-007e-44a0-9fe5-3b6ca2323389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895608853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1895608853
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2899274719
Short name T294
Test name
Test status
Simulation time 497335791495 ps
CPU time 1177.46 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:24:56 PM PDT 24
Peak memory 201956 kb
Host smart-4cf54051-74c8-400f-aad7-18a5d7213e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899274719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2899274719
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2564241086
Short name T151
Test name
Test status
Simulation time 498455837663 ps
CPU time 1219.18 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 201912 kb
Host smart-ab2e3b3d-b0bc-4d9c-a472-3221f10cf68e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564241086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2564241086
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3028764322
Short name T16
Test name
Test status
Simulation time 96800860606 ps
CPU time 159.01 seconds
Started Mar 28 01:07:33 PM PDT 24
Finished Mar 28 01:10:12 PM PDT 24
Peak memory 210524 kb
Host smart-b7718c7d-5728-45bf-b035-1fc36cd0f909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028764322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3028764322
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2505309684
Short name T239
Test name
Test status
Simulation time 492520851042 ps
CPU time 1166.58 seconds
Started Mar 28 01:08:29 PM PDT 24
Finished Mar 28 01:27:55 PM PDT 24
Peak memory 201812 kb
Host smart-2cbb131b-c5d7-40e0-934f-b42b88af69bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505309684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2505309684
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3356330837
Short name T247
Test name
Test status
Simulation time 186183954551 ps
CPU time 433.82 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:15:40 PM PDT 24
Peak memory 201912 kb
Host smart-0adeb25f-04c5-482f-bf13-849d09cb94f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356330837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3356330837
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.84546623
Short name T122
Test name
Test status
Simulation time 924202182 ps
CPU time 4.71 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:46 PM PDT 24
Peak memory 201696 kb
Host smart-2c9a6e6b-08d7-47f6-8784-ff7aceb8d03f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84546623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasi
ng.84546623
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.275950540
Short name T116
Test name
Test status
Simulation time 20814013312 ps
CPU time 27.65 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:32:01 PM PDT 24
Peak memory 201828 kb
Host smart-899e7810-36cf-48da-8ccf-54a50b171e03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275950540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.275950540
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.666263627
Short name T811
Test name
Test status
Simulation time 1111970583 ps
CPU time 1.49 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 201532 kb
Host smart-dbdd49d2-26be-4300-9dc2-77b6ddd961da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666263627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.666263627
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2142202966
Short name T99
Test name
Test status
Simulation time 556513734 ps
CPU time 2.2 seconds
Started Mar 28 12:31:46 PM PDT 24
Finished Mar 28 12:31:49 PM PDT 24
Peak memory 201600 kb
Host smart-c7e9e6c4-da9e-4604-9be9-3f297ff05659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142202966 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2142202966
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3883569393
Short name T906
Test name
Test status
Simulation time 534646249 ps
CPU time 1.01 seconds
Started Mar 28 12:31:46 PM PDT 24
Finished Mar 28 12:31:47 PM PDT 24
Peak memory 201540 kb
Host smart-b9dc4857-b968-42a3-a0ba-eae67ed23b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883569393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3883569393
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1049199902
Short name T800
Test name
Test status
Simulation time 387263463 ps
CPU time 0.85 seconds
Started Mar 28 12:31:43 PM PDT 24
Finished Mar 28 12:31:45 PM PDT 24
Peak memory 201548 kb
Host smart-4f35b95a-e82d-44d5-8420-b99b811d23ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049199902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1049199902
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1126041442
Short name T875
Test name
Test status
Simulation time 4332580808 ps
CPU time 4.22 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 201652 kb
Host smart-b34578e7-ffb1-4cf2-b6d0-44e0706723e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126041442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1126041442
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3511365847
Short name T865
Test name
Test status
Simulation time 323976741 ps
CPU time 1.95 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 201884 kb
Host smart-a7d1c8c3-236e-477a-85b9-fcceb903fcc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511365847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3511365847
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3904912949
Short name T859
Test name
Test status
Simulation time 4763518264 ps
CPU time 4.16 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:10 PM PDT 24
Peak memory 201924 kb
Host smart-b2b972d0-395c-4221-af21-21ff4b6c6292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904912949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3904912949
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.708079503
Short name T121
Test name
Test status
Simulation time 832021191 ps
CPU time 4.1 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 201784 kb
Host smart-ff0ad57b-b192-4892-8bdf-a83bf49e0399
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708079503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.708079503
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1279827238
Short name T837
Test name
Test status
Simulation time 25831450172 ps
CPU time 32.51 seconds
Started Mar 28 12:31:54 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201836 kb
Host smart-023d8c1e-99ee-4081-938f-f1b81fdf1fcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279827238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1279827238
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.208486616
Short name T919
Test name
Test status
Simulation time 1303872096 ps
CPU time 3.54 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 201580 kb
Host smart-010c85b3-ab60-4a6a-8c2f-be51f93e7d34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208486616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.208486616
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2205276726
Short name T858
Test name
Test status
Simulation time 406216496 ps
CPU time 1.76 seconds
Started Mar 28 12:31:54 PM PDT 24
Finished Mar 28 12:31:56 PM PDT 24
Peak memory 201660 kb
Host smart-c4327e0f-43ca-4f08-9396-1716a4d1d1ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205276726 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2205276726
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.439162869
Short name T900
Test name
Test status
Simulation time 387437579 ps
CPU time 0.79 seconds
Started Mar 28 12:31:48 PM PDT 24
Finished Mar 28 12:31:49 PM PDT 24
Peak memory 201580 kb
Host smart-c1c7ed7f-0353-4452-84a0-068a29b69941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439162869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.439162869
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2805058389
Short name T881
Test name
Test status
Simulation time 474713076 ps
CPU time 1.68 seconds
Started Mar 28 12:31:43 PM PDT 24
Finished Mar 28 12:31:45 PM PDT 24
Peak memory 201544 kb
Host smart-6ce2fd46-ebbd-4b26-9dfc-9787a783b64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805058389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2805058389
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.691131858
Short name T128
Test name
Test status
Simulation time 2301358271 ps
CPU time 2.4 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 201620 kb
Host smart-978cedbc-f366-4f2a-b714-42f6ef7c780f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691131858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.691131858
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3567578994
Short name T847
Test name
Test status
Simulation time 389203751 ps
CPU time 2.62 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:40 PM PDT 24
Peak memory 217764 kb
Host smart-e57505b6-71b0-4738-81b3-ff5a1a3e14e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567578994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3567578994
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1590165711
Short name T68
Test name
Test status
Simulation time 8479992595 ps
CPU time 6.12 seconds
Started Mar 28 12:31:38 PM PDT 24
Finished Mar 28 12:31:44 PM PDT 24
Peak memory 201884 kb
Host smart-2f4346db-a6b5-46b8-9797-4c1f93b990c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590165711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1590165711
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1844662788
Short name T802
Test name
Test status
Simulation time 572865318 ps
CPU time 1.11 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201648 kb
Host smart-57e766f0-5cef-4b07-9d71-4f8511e521ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844662788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1844662788
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3864165263
Short name T115
Test name
Test status
Simulation time 501892525 ps
CPU time 1.33 seconds
Started Mar 28 12:31:57 PM PDT 24
Finished Mar 28 12:31:58 PM PDT 24
Peak memory 201568 kb
Host smart-fa257a0b-e592-4d00-9fc8-d5021c8a8520
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864165263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3864165263
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3875521753
Short name T845
Test name
Test status
Simulation time 283760538 ps
CPU time 1.29 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:06 PM PDT 24
Peak memory 201580 kb
Host smart-092ae10e-5a6d-42f4-b17f-7ff53d201db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875521753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3875521753
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2267289987
Short name T907
Test name
Test status
Simulation time 5683736007 ps
CPU time 20.01 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:47 PM PDT 24
Peak memory 201808 kb
Host smart-d368c270-743e-43ea-926d-6082bdaee17d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267289987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2267289987
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2670216773
Short name T834
Test name
Test status
Simulation time 4589643732 ps
CPU time 11.57 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201784 kb
Host smart-117eaa4a-5f40-4b92-b99f-b9ea9394ac3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670216773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2670216773
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3275469534
Short name T98
Test name
Test status
Simulation time 409104873 ps
CPU time 1.14 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201624 kb
Host smart-ba64682c-c0c4-49ec-b0f0-119e189ff0c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275469534 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3275469534
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.381113217
Short name T861
Test name
Test status
Simulation time 369751103 ps
CPU time 0.84 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201556 kb
Host smart-c3fffb25-9b14-427e-958f-2713f055968f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381113217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.381113217
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1323954712
Short name T813
Test name
Test status
Simulation time 446422452 ps
CPU time 1.57 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201532 kb
Host smart-a627484d-6bb7-40e3-afa2-ce77d64a5151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323954712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1323954712
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1180403071
Short name T901
Test name
Test status
Simulation time 2794141571 ps
CPU time 13.99 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:37 PM PDT 24
Peak memory 201948 kb
Host smart-7561c1fd-c1cb-48a2-bdae-4b5352064c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180403071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1180403071
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3040744888
Short name T908
Test name
Test status
Simulation time 481695080 ps
CPU time 1.54 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201868 kb
Host smart-d175ae76-254b-44e6-88c9-4a45bffa56fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040744888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3040744888
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1532446538
Short name T85
Test name
Test status
Simulation time 7937290962 ps
CPU time 19.43 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201868 kb
Host smart-2ee4d12d-1f9e-4b96-9244-a87d74d85cca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532446538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1532446538
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.820910362
Short name T916
Test name
Test status
Simulation time 582570181 ps
CPU time 1.2 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 210004 kb
Host smart-30454625-2c8d-4a5a-940f-bbbf9fbc97b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820910362 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.820910362
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3887200954
Short name T114
Test name
Test status
Simulation time 653692744 ps
CPU time 1.02 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201536 kb
Host smart-f7202968-2ad9-4fd3-babb-a60acbc43b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887200954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3887200954
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3213970582
Short name T812
Test name
Test status
Simulation time 386227339 ps
CPU time 0.83 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201556 kb
Host smart-a2889b21-77ed-4a98-a663-28b5295f71a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213970582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3213970582
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3611176519
Short name T848
Test name
Test status
Simulation time 472468243 ps
CPU time 2.44 seconds
Started Mar 28 12:32:07 PM PDT 24
Finished Mar 28 12:32:10 PM PDT 24
Peak memory 201856 kb
Host smart-9d05b8c5-b964-4ff4-82cb-bb2fd0e4f5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611176519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3611176519
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3902008985
Short name T820
Test name
Test status
Simulation time 8309344133 ps
CPU time 21.15 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201828 kb
Host smart-e605a419-7d96-4d09-b583-59e187802435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902008985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3902008985
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.723975309
Short name T816
Test name
Test status
Simulation time 713455990 ps
CPU time 1.67 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 210072 kb
Host smart-67874547-5c67-49a5-803d-c3579a896d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723975309 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.723975309
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3463208919
Short name T855
Test name
Test status
Simulation time 321765242 ps
CPU time 1.48 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:07 PM PDT 24
Peak memory 201580 kb
Host smart-db093d2b-fceb-4c24-96a4-70c4e4a3329a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463208919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3463208919
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3161269689
Short name T818
Test name
Test status
Simulation time 307366115 ps
CPU time 0.8 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201576 kb
Host smart-56e6346d-38ba-49fd-baa1-07286924a300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161269689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3161269689
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.26497681
Short name T126
Test name
Test status
Simulation time 2458929367 ps
CPU time 10.32 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201632 kb
Host smart-5ba6b474-a993-49a0-8c3a-1cb4b1bdae3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26497681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ct
rl_same_csr_outstanding.26497681
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1718234500
Short name T807
Test name
Test status
Simulation time 365446685 ps
CPU time 2.02 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201868 kb
Host smart-a2a741dc-cd82-49b3-adc8-d9395b836aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718234500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1718234500
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3126532615
Short name T336
Test name
Test status
Simulation time 5310903559 ps
CPU time 2.32 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201820 kb
Host smart-4ad37019-1a8f-4967-b363-9178990dd0f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126532615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3126532615
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2432781845
Short name T868
Test name
Test status
Simulation time 437822274 ps
CPU time 1.94 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201620 kb
Host smart-dc999ab1-c124-41e5-9987-0a514988125a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432781845 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2432781845
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.7285455
Short name T884
Test name
Test status
Simulation time 443008205 ps
CPU time 1.06 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201556 kb
Host smart-c3ba6e09-8be3-4034-a356-a237f4ab12d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7285455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.7285455
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1600028402
Short name T856
Test name
Test status
Simulation time 287161551 ps
CPU time 1.28 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201564 kb
Host smart-d4591921-5f2a-4565-9e93-fc5e152b84a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600028402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1600028402
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2306145737
Short name T854
Test name
Test status
Simulation time 2445736523 ps
CPU time 2.85 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201600 kb
Host smart-e1eca778-0056-4509-8d9d-3bcb5933559e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306145737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2306145737
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2288405669
Short name T853
Test name
Test status
Simulation time 470311997 ps
CPU time 1.41 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201840 kb
Host smart-010fdc31-11a2-49a2-8550-4cfe77b09c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288405669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2288405669
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2550670861
Short name T836
Test name
Test status
Simulation time 4610689250 ps
CPU time 3.92 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201820 kb
Host smart-5eb8096c-1615-4f20-ae2f-3271902a4383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550670861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2550670861
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2567249356
Short name T877
Test name
Test status
Simulation time 621798099 ps
CPU time 1.62 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201588 kb
Host smart-79db62d0-4ab9-42d7-a247-7a1a692cbd22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567249356 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2567249356
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3457225847
Short name T914
Test name
Test status
Simulation time 560650476 ps
CPU time 2.14 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201688 kb
Host smart-1e7d82e5-20d8-43b3-989b-7c57de7197c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457225847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3457225847
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.577036828
Short name T797
Test name
Test status
Simulation time 431059790 ps
CPU time 1.11 seconds
Started Mar 28 12:32:07 PM PDT 24
Finished Mar 28 12:32:08 PM PDT 24
Peak memory 201596 kb
Host smart-31b4a16e-6f77-4c08-a226-8fb3f0e5b427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577036828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.577036828
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2341112336
Short name T831
Test name
Test status
Simulation time 2287280820 ps
CPU time 6.12 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201624 kb
Host smart-2e11d306-1646-4198-b1a2-6717149eb76b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341112336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2341112336
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1178581731
Short name T823
Test name
Test status
Simulation time 767629564 ps
CPU time 2.1 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 201856 kb
Host smart-a3515afd-9e0c-4e1c-9551-6c7ffff3e2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178581731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1178581731
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3042733555
Short name T817
Test name
Test status
Simulation time 9409255936 ps
CPU time 4.36 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201840 kb
Host smart-898b8164-ec91-4eaa-be53-0d9e04721a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042733555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3042733555
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1358658656
Short name T84
Test name
Test status
Simulation time 509593209 ps
CPU time 1.34 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201612 kb
Host smart-962ee4dd-c135-4c0f-bbb4-b7d2523a3ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358658656 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1358658656
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2679508996
Short name T112
Test name
Test status
Simulation time 466721925 ps
CPU time 1.41 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201564 kb
Host smart-43d6f2d2-e82d-4eba-9d31-d3b2ad132dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679508996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2679508996
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2295836289
Short name T863
Test name
Test status
Simulation time 473400667 ps
CPU time 0.9 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201556 kb
Host smart-ef0d31e2-d37b-43cd-a9e5-203af532b3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295836289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2295836289
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3986815321
Short name T866
Test name
Test status
Simulation time 4313780087 ps
CPU time 16.79 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:41 PM PDT 24
Peak memory 201876 kb
Host smart-eaa12e64-7a8c-421d-9756-a3c24456e933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986815321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3986815321
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2368380733
Short name T77
Test name
Test status
Simulation time 533776944 ps
CPU time 3.2 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201880 kb
Host smart-51631773-d2ff-45b9-b877-3da54792bceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368380733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2368380733
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1504737895
Short name T904
Test name
Test status
Simulation time 8472508666 ps
CPU time 12.79 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:37 PM PDT 24
Peak memory 201904 kb
Host smart-e0301ac3-9af8-4e38-a83f-97f3037f169f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504737895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1504737895
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3549875831
Short name T71
Test name
Test status
Simulation time 809509529 ps
CPU time 1.1 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201644 kb
Host smart-fee91215-8ae1-4bea-bfaf-03d5d05a2289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549875831 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3549875831
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3593136606
Short name T125
Test name
Test status
Simulation time 416961878 ps
CPU time 0.96 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:16 PM PDT 24
Peak memory 201564 kb
Host smart-65aec414-fd22-4a6b-84ad-d2e519560fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593136606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3593136606
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4132537620
Short name T819
Test name
Test status
Simulation time 303981723 ps
CPU time 1.01 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 201532 kb
Host smart-3e0bc91d-0c92-4f87-9307-463e531bfcc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132537620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4132537620
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4176637177
Short name T62
Test name
Test status
Simulation time 2415432662 ps
CPU time 1.68 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201600 kb
Host smart-03829aac-fac1-45bf-9f67-bcc871f85e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176637177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4176637177
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.981168484
Short name T894
Test name
Test status
Simulation time 2346646957 ps
CPU time 2.77 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 218264 kb
Host smart-f87ac8c0-f614-478a-8ada-0e9b9dd3be7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981168484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.981168484
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.842711501
Short name T890
Test name
Test status
Simulation time 7371795364 ps
CPU time 11.18 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201832 kb
Host smart-a977095b-ca8f-442b-946e-5fa431635372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842711501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.842711501
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1709514843
Short name T871
Test name
Test status
Simulation time 508650145 ps
CPU time 1.24 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201628 kb
Host smart-d3af4996-587c-405a-81ad-8955e87a0da2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709514843 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1709514843
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.889679421
Short name T119
Test name
Test status
Simulation time 341093860 ps
CPU time 1.46 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201568 kb
Host smart-ad0e847f-61e7-442d-8e22-82ff275812b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889679421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.889679421
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1171175038
Short name T805
Test name
Test status
Simulation time 490099361 ps
CPU time 1.81 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201524 kb
Host smart-63e1c208-6de3-40f2-96c1-4f7012e81df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171175038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1171175038
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1528884062
Short name T826
Test name
Test status
Simulation time 2218040203 ps
CPU time 8.64 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201624 kb
Host smart-5f6eed8b-445b-4a99-b3c8-f4c8c378fd73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528884062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1528884062
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3237344440
Short name T883
Test name
Test status
Simulation time 538602395 ps
CPU time 1.69 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201808 kb
Host smart-94523e5f-3ab6-4052-9600-b833d55747cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237344440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3237344440
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3517747877
Short name T840
Test name
Test status
Simulation time 4176105223 ps
CPU time 11.71 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 201752 kb
Host smart-bea69ba3-bf89-4fdc-84b4-02bb7c765745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517747877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3517747877
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2743782053
Short name T887
Test name
Test status
Simulation time 561472101 ps
CPU time 1.11 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201632 kb
Host smart-547963fc-7cc4-4b0e-9095-63f93d2eabb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743782053 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2743782053
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1784247351
Short name T895
Test name
Test status
Simulation time 341022444 ps
CPU time 1.64 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201580 kb
Host smart-7f0f20cb-c0c7-4aa6-87f7-0ba20dde6103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784247351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1784247351
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3701731542
Short name T798
Test name
Test status
Simulation time 430402293 ps
CPU time 1.66 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201560 kb
Host smart-04cb035b-fb1b-4f04-ab89-1df4c92f0322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701731542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3701731542
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3745222243
Short name T876
Test name
Test status
Simulation time 2115000806 ps
CPU time 2.17 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201568 kb
Host smart-fc36d26a-a024-416f-b7e6-a46ba5bb1713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745222243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3745222243
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1540181762
Short name T803
Test name
Test status
Simulation time 479271376 ps
CPU time 1.98 seconds
Started Mar 28 12:32:13 PM PDT 24
Finished Mar 28 12:32:17 PM PDT 24
Peak memory 201796 kb
Host smart-b7f223ec-38ce-4319-ab8d-14dc6fb3d623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540181762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1540181762
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1212825024
Short name T862
Test name
Test status
Simulation time 8435880784 ps
CPU time 12.07 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201788 kb
Host smart-11197b17-3eec-41f7-9166-3705e8a05d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212825024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1212825024
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.499785338
Short name T850
Test name
Test status
Simulation time 824102439 ps
CPU time 2.46 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 201700 kb
Host smart-ba6e11f3-c39d-451b-a529-48e295d8690a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499785338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.499785338
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1935160201
Short name T873
Test name
Test status
Simulation time 53156761102 ps
CPU time 45.38 seconds
Started Mar 28 12:31:53 PM PDT 24
Finished Mar 28 12:32:44 PM PDT 24
Peak memory 201828 kb
Host smart-7dccc6b1-3767-473f-9040-66dfeaf2064e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935160201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1935160201
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2556120703
Short name T130
Test name
Test status
Simulation time 673034784 ps
CPU time 1.13 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:43 PM PDT 24
Peak memory 201572 kb
Host smart-d5469b8f-0f52-489e-8573-e1e9610c5ec7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556120703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2556120703
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2189561360
Short name T815
Test name
Test status
Simulation time 634404659 ps
CPU time 1.14 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 201624 kb
Host smart-7daa1719-4586-4de9-ac5a-8bdab98815a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189561360 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2189561360
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.235394448
Short name T821
Test name
Test status
Simulation time 342500187 ps
CPU time 1.58 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:43 PM PDT 24
Peak memory 201552 kb
Host smart-5fd05ad2-d779-4251-a0f8-e70867dc0f34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235394448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.235394448
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2925231971
Short name T808
Test name
Test status
Simulation time 329928615 ps
CPU time 0.8 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 201584 kb
Host smart-22d876f1-0c99-4c20-b523-1a0644e708f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925231971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2925231971
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.450556233
Short name T63
Test name
Test status
Simulation time 4637131759 ps
CPU time 6.81 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:47 PM PDT 24
Peak memory 201872 kb
Host smart-62b19493-77bb-4d22-b510-3caa21bbabc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450556233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.450556233
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2859292386
Short name T822
Test name
Test status
Simulation time 510137530 ps
CPU time 2.27 seconds
Started Mar 28 12:31:47 PM PDT 24
Finished Mar 28 12:31:49 PM PDT 24
Peak memory 201828 kb
Host smart-d3aa8f46-8dce-42e7-9300-ff714d893728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859292386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2859292386
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2725499677
Short name T888
Test name
Test status
Simulation time 4406263184 ps
CPU time 12.39 seconds
Started Mar 28 12:31:48 PM PDT 24
Finished Mar 28 12:32:01 PM PDT 24
Peak memory 201880 kb
Host smart-1f4af707-af85-4a74-a77c-8a2d8f640f74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725499677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2725499677
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3298481978
Short name T835
Test name
Test status
Simulation time 528376696 ps
CPU time 1.84 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201560 kb
Host smart-7f2b12d6-660d-40ba-b1ee-59aca4adf2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298481978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3298481978
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4169403832
Short name T909
Test name
Test status
Simulation time 369790608 ps
CPU time 1.58 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201556 kb
Host smart-5bde4a82-8346-4b8f-8bb9-fafb2b3830bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169403832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4169403832
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.886083650
Short name T915
Test name
Test status
Simulation time 338479961 ps
CPU time 0.87 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201576 kb
Host smart-15032c1d-d641-46cc-b4c5-334306ba95d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886083650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.886083650
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2172012081
Short name T872
Test name
Test status
Simulation time 312578257 ps
CPU time 1.29 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201564 kb
Host smart-02c9a64b-b79e-4dc3-822a-049df2f7f6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172012081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2172012081
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2484245157
Short name T814
Test name
Test status
Simulation time 529542054 ps
CPU time 0.92 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201576 kb
Host smart-8638eb6f-c7ff-4ff9-8955-0ecccd8d7c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484245157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2484245157
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3963784094
Short name T882
Test name
Test status
Simulation time 507335454 ps
CPU time 1.82 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201524 kb
Host smart-82933688-2b98-41ab-902f-44519c838723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963784094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3963784094
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4028242283
Short name T905
Test name
Test status
Simulation time 525245194 ps
CPU time 1.28 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201520 kb
Host smart-86810fe0-92ee-43dc-a831-653c1044afa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028242283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4028242283
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2348174572
Short name T911
Test name
Test status
Simulation time 485687540 ps
CPU time 0.92 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201520 kb
Host smart-bb9d8472-3dd2-44d9-9781-a34c029dcb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348174572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2348174572
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.654019887
Short name T913
Test name
Test status
Simulation time 320362266 ps
CPU time 1.33 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 201524 kb
Host smart-17e9d764-dbf0-4fcf-831a-4351bc63009b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654019887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.654019887
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1116648124
Short name T891
Test name
Test status
Simulation time 465441206 ps
CPU time 1.6 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 201540 kb
Host smart-d357c2fc-7fd3-4c99-8506-0335484d1c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116648124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1116648124
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3385188998
Short name T902
Test name
Test status
Simulation time 1133917425 ps
CPU time 3.05 seconds
Started Mar 28 12:31:35 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 201760 kb
Host smart-576a216e-d17e-4b5a-b13a-5c4f967dc9ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385188998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3385188998
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2981158513
Short name T117
Test name
Test status
Simulation time 26997712497 ps
CPU time 20.61 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:54 PM PDT 24
Peak memory 201800 kb
Host smart-6e17b253-d74d-4939-b9ab-9340716779f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981158513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2981158513
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3579294290
Short name T113
Test name
Test status
Simulation time 1124741074 ps
CPU time 2.03 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 201548 kb
Host smart-b347d7e1-b92c-41a6-a087-995bc8968556
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579294290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3579294290
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3907481970
Short name T897
Test name
Test status
Simulation time 434304768 ps
CPU time 1.06 seconds
Started Mar 28 12:31:37 PM PDT 24
Finished Mar 28 12:31:39 PM PDT 24
Peak memory 201640 kb
Host smart-e0782488-0230-42ab-a568-0dd9e1c052d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907481970 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3907481970
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1348428337
Short name T857
Test name
Test status
Simulation time 372819814 ps
CPU time 0.72 seconds
Started Mar 28 12:31:36 PM PDT 24
Finished Mar 28 12:31:37 PM PDT 24
Peak memory 201560 kb
Host smart-1868b591-8e14-4b5a-8eae-e3143cfb0b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348428337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1348428337
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1363458356
Short name T127
Test name
Test status
Simulation time 3898475941 ps
CPU time 5.73 seconds
Started Mar 28 12:32:03 PM PDT 24
Finished Mar 28 12:32:09 PM PDT 24
Peak memory 201784 kb
Host smart-fb9b633f-4aee-4a47-bc78-dff06317f275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363458356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1363458356
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2479128892
Short name T78
Test name
Test status
Simulation time 522434963 ps
CPU time 2.31 seconds
Started Mar 28 12:32:07 PM PDT 24
Finished Mar 28 12:32:10 PM PDT 24
Peak memory 201828 kb
Host smart-3f3efa96-0cb0-434b-b697-86d3ad33c044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479128892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2479128892
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3472852801
Short name T72
Test name
Test status
Simulation time 4454290947 ps
CPU time 12.08 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:47 PM PDT 24
Peak memory 201796 kb
Host smart-72a463c1-dcbd-4bf5-96bf-4cddee7b3bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472852801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3472852801
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1466822166
Short name T801
Test name
Test status
Simulation time 421596989 ps
CPU time 0.95 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201560 kb
Host smart-4c267f28-a6e0-4d01-b915-280928fd03ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466822166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1466822166
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.811452018
Short name T851
Test name
Test status
Simulation time 329731780 ps
CPU time 0.86 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201564 kb
Host smart-7d2eb884-be56-46d2-a37d-062e4e78798e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811452018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.811452018
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1534979241
Short name T889
Test name
Test status
Simulation time 310476332 ps
CPU time 0.81 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201532 kb
Host smart-28ba7b1c-fd4e-4d9c-ba21-aa2797d28724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534979241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1534979241
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1703350976
Short name T806
Test name
Test status
Simulation time 439171405 ps
CPU time 1.65 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:17 PM PDT 24
Peak memory 201576 kb
Host smart-8756a968-c67b-4081-aa51-789fa746f4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703350976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1703350976
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3317019235
Short name T852
Test name
Test status
Simulation time 464770509 ps
CPU time 0.89 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201548 kb
Host smart-963c8c5c-2de7-4ab3-91e5-cc94a9664f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317019235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3317019235
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2917609676
Short name T903
Test name
Test status
Simulation time 287443838 ps
CPU time 1.3 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201572 kb
Host smart-db9e49d3-061d-4a1b-a8d4-80a23f437e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917609676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2917609676
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3792270963
Short name T849
Test name
Test status
Simulation time 350531933 ps
CPU time 1.49 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201544 kb
Host smart-95e11fb2-be94-4797-9f99-0b8b412988ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792270963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3792270963
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3790646769
Short name T910
Test name
Test status
Simulation time 392389669 ps
CPU time 1.1 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:18 PM PDT 24
Peak memory 201552 kb
Host smart-2ecf9899-7ede-408e-ab3e-0c21235e7eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790646769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3790646769
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1232842979
Short name T912
Test name
Test status
Simulation time 485066261 ps
CPU time 0.79 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201532 kb
Host smart-4e225a48-3e40-4c8b-8b7a-3dda2e2fa95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232842979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1232842979
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1662842471
Short name T843
Test name
Test status
Simulation time 427512013 ps
CPU time 1.73 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:16 PM PDT 24
Peak memory 201528 kb
Host smart-56a93fa6-33a6-4200-bce2-eef8155fdab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662842471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1662842471
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2752042715
Short name T118
Test name
Test status
Simulation time 1192475272 ps
CPU time 5.49 seconds
Started Mar 28 12:31:53 PM PDT 24
Finished Mar 28 12:31:59 PM PDT 24
Peak memory 201760 kb
Host smart-fb9e472b-5b49-481a-ac47-6de53f128d4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752042715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2752042715
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2942330185
Short name T828
Test name
Test status
Simulation time 26377101914 ps
CPU time 25.97 seconds
Started Mar 28 12:31:55 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201884 kb
Host smart-ae6b48bb-5247-4ea2-b951-6a46f1d117d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942330185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2942330185
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.199661471
Short name T111
Test name
Test status
Simulation time 894466193 ps
CPU time 1.69 seconds
Started Mar 28 12:31:43 PM PDT 24
Finished Mar 28 12:31:45 PM PDT 24
Peak memory 201560 kb
Host smart-ba16e981-00b7-4b19-a7f0-da1a21d2299e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199661471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.199661471
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2308633106
Short name T893
Test name
Test status
Simulation time 635684859 ps
CPU time 1.28 seconds
Started Mar 28 12:31:59 PM PDT 24
Finished Mar 28 12:32:00 PM PDT 24
Peak memory 201664 kb
Host smart-78beb4b3-b437-46c1-bc94-25634d70d46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308633106 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2308633106
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1022349235
Short name T120
Test name
Test status
Simulation time 522623726 ps
CPU time 0.88 seconds
Started Mar 28 12:31:40 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 201556 kb
Host smart-ab75eddf-5fcb-4835-beae-8874c5aa7a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022349235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1022349235
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.906997569
Short name T864
Test name
Test status
Simulation time 409934230 ps
CPU time 0.87 seconds
Started Mar 28 12:31:39 PM PDT 24
Finished Mar 28 12:31:42 PM PDT 24
Peak memory 201564 kb
Host smart-ee78dfd3-c2b4-42e0-b3e3-49268e8416f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906997569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.906997569
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3139390988
Short name T917
Test name
Test status
Simulation time 4594079814 ps
CPU time 6.36 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:41 PM PDT 24
Peak memory 201828 kb
Host smart-7a3868f4-28c6-44cf-b574-9759fc494b02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139390988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3139390988
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3712085412
Short name T842
Test name
Test status
Simulation time 514651738 ps
CPU time 1.78 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201520 kb
Host smart-34092495-8eaa-4e4f-83dd-c5a0d324fbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712085412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3712085412
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1153302303
Short name T799
Test name
Test status
Simulation time 455131441 ps
CPU time 1.09 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201548 kb
Host smart-89f086da-6e2f-424c-a925-7843fe5187ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153302303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1153302303
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.620811933
Short name T804
Test name
Test status
Simulation time 516515729 ps
CPU time 0.93 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201540 kb
Host smart-c6a32d52-6364-4826-8a9f-12a75742288c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620811933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.620811933
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2685909501
Short name T896
Test name
Test status
Simulation time 391878722 ps
CPU time 0.88 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:09 PM PDT 24
Peak memory 201588 kb
Host smart-d43a12ab-9efe-43a8-be04-56972913e766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685909501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2685909501
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3396802394
Short name T879
Test name
Test status
Simulation time 288511899 ps
CPU time 1.33 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201540 kb
Host smart-491da205-c6de-4d91-9257-9f506a8062c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396802394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3396802394
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1150773763
Short name T825
Test name
Test status
Simulation time 509200761 ps
CPU time 1.85 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201532 kb
Host smart-23a4e4c7-eefb-44c3-865a-8c61ab951c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150773763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1150773763
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3823657290
Short name T833
Test name
Test status
Simulation time 516570256 ps
CPU time 1.78 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201568 kb
Host smart-e19d88b2-a82d-459f-a467-2375d1226d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823657290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3823657290
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1143151325
Short name T810
Test name
Test status
Simulation time 535238630 ps
CPU time 1.21 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201564 kb
Host smart-b1a0b4cd-07b0-4ef3-aa60-57b6a492d639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143151325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1143151325
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1635304924
Short name T870
Test name
Test status
Simulation time 576229750 ps
CPU time 0.88 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201560 kb
Host smart-fb381f79-647d-4696-9877-bd8c538adc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635304924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1635304924
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2904202504
Short name T898
Test name
Test status
Simulation time 520599082 ps
CPU time 1.02 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201596 kb
Host smart-1a43f93e-02d2-4440-89ec-decd7a9aa08f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904202504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2904202504
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.319085434
Short name T886
Test name
Test status
Simulation time 480451125 ps
CPU time 1.43 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:18 PM PDT 24
Peak memory 201712 kb
Host smart-bf051ff2-b46a-47cc-a8a0-94e6b4473061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319085434 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.319085434
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2643180755
Short name T123
Test name
Test status
Simulation time 501225543 ps
CPU time 2.01 seconds
Started Mar 28 12:31:33 PM PDT 24
Finished Mar 28 12:31:35 PM PDT 24
Peak memory 201576 kb
Host smart-c64a234e-160a-41df-9d93-df55bdba2e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643180755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2643180755
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2849846286
Short name T832
Test name
Test status
Simulation time 433937622 ps
CPU time 1.63 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:12 PM PDT 24
Peak memory 201524 kb
Host smart-f546d36d-95e3-4985-814d-2c870483298d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849846286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2849846286
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1934091976
Short name T899
Test name
Test status
Simulation time 1982712931 ps
CPU time 7.81 seconds
Started Mar 28 12:31:41 PM PDT 24
Finished Mar 28 12:31:50 PM PDT 24
Peak memory 201540 kb
Host smart-6bf9c585-708a-493e-bd5b-77bc81d66370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934091976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1934091976
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4280759158
Short name T841
Test name
Test status
Simulation time 586641639 ps
CPU time 3.22 seconds
Started Mar 28 12:31:34 PM PDT 24
Finished Mar 28 12:31:38 PM PDT 24
Peak memory 210048 kb
Host smart-499f4383-9668-49e6-907b-5a37700c208d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280759158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4280759158
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1626189821
Short name T878
Test name
Test status
Simulation time 8989972183 ps
CPU time 3.57 seconds
Started Mar 28 12:31:46 PM PDT 24
Finished Mar 28 12:31:50 PM PDT 24
Peak memory 201800 kb
Host smart-21509b5a-07ff-4c59-aa59-fa151888181d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626189821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1626189821
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.349283775
Short name T97
Test name
Test status
Simulation time 538581888 ps
CPU time 1.49 seconds
Started Mar 28 12:32:07 PM PDT 24
Finished Mar 28 12:32:09 PM PDT 24
Peak memory 201628 kb
Host smart-ac348ce4-e97a-49c4-bc6d-677b67968cfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349283775 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.349283775
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2773973837
Short name T874
Test name
Test status
Simulation time 375348380 ps
CPU time 1.12 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201568 kb
Host smart-d57d059b-9eb9-4565-8b95-55325ac716eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773973837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2773973837
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1272570445
Short name T839
Test name
Test status
Simulation time 671592391 ps
CPU time 0.73 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:17 PM PDT 24
Peak memory 201556 kb
Host smart-bfe33a6f-911f-4bde-b0dd-a9c7b027bbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272570445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1272570445
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3652823381
Short name T61
Test name
Test status
Simulation time 4946828174 ps
CPU time 6.31 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201816 kb
Host smart-e1a58b04-6069-4213-8d68-10163ad1b10f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652823381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3652823381
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.848778197
Short name T79
Test name
Test status
Simulation time 781328532 ps
CPU time 2.57 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:12 PM PDT 24
Peak memory 217820 kb
Host smart-9c1c4554-5a65-4d03-aedb-faf53935dea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848778197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.848778197
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3205494787
Short name T918
Test name
Test status
Simulation time 624224206 ps
CPU time 2.47 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201620 kb
Host smart-be3558f7-7f47-46e3-b7a2-d87b5cc1154f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205494787 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3205494787
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3019529803
Short name T885
Test name
Test status
Simulation time 335753898 ps
CPU time 1.1 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 201556 kb
Host smart-69b329db-a083-4828-999b-a96f9387890e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019529803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3019529803
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.593871683
Short name T824
Test name
Test status
Simulation time 338378133 ps
CPU time 0.83 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:12 PM PDT 24
Peak memory 201448 kb
Host smart-d5558710-baea-4da0-80ff-213c3796fcee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593871683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.593871683
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4268622971
Short name T844
Test name
Test status
Simulation time 2609952688 ps
CPU time 4.01 seconds
Started Mar 28 12:32:04 PM PDT 24
Finished Mar 28 12:32:08 PM PDT 24
Peak memory 201616 kb
Host smart-68923583-d282-4d61-b5f9-6cd5c53d445e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268622971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4268622971
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2007120781
Short name T827
Test name
Test status
Simulation time 679354602 ps
CPU time 1.57 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:12 PM PDT 24
Peak memory 201840 kb
Host smart-47ec47fd-16c8-4187-bcd6-32d7554c32c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007120781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2007120781
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.540632757
Short name T67
Test name
Test status
Simulation time 4614612812 ps
CPU time 6.66 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201772 kb
Host smart-6e642301-936f-4f44-9ed0-5a87899f393b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540632757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.540632757
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1966989575
Short name T830
Test name
Test status
Simulation time 668827165 ps
CPU time 1.28 seconds
Started Mar 28 12:32:06 PM PDT 24
Finished Mar 28 12:32:08 PM PDT 24
Peak memory 201616 kb
Host smart-454b2d34-7837-40a4-8620-79bbe38e8707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966989575 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1966989575
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.580858810
Short name T124
Test name
Test status
Simulation time 542762009 ps
CPU time 1.96 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201496 kb
Host smart-0d8a7c8c-9718-4a88-8d3a-96aba87b50a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580858810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.580858810
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3283812917
Short name T829
Test name
Test status
Simulation time 339583295 ps
CPU time 1.43 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201572 kb
Host smart-ead1ca4d-c770-4e3c-840b-c0ea4e37a116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283812917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3283812917
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1526668700
Short name T892
Test name
Test status
Simulation time 2490284074 ps
CPU time 2.28 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201636 kb
Host smart-7067ab04-2ea0-4757-8305-bf1699689bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526668700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1526668700
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2836553242
Short name T860
Test name
Test status
Simulation time 375918639 ps
CPU time 2.59 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:12 PM PDT 24
Peak memory 201940 kb
Host smart-b74b79b9-8b43-4eff-86ef-635af8036988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836553242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2836553242
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3460213955
Short name T880
Test name
Test status
Simulation time 8620866474 ps
CPU time 21.98 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:47 PM PDT 24
Peak memory 201832 kb
Host smart-f37c1ce3-bd30-4b83-a13e-0bf8fc0fdf85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460213955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3460213955
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.761675317
Short name T869
Test name
Test status
Simulation time 570245891 ps
CPU time 1.47 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201640 kb
Host smart-8f52520c-7ce6-4327-b36b-896590dee864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761675317 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.761675317
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3727896302
Short name T846
Test name
Test status
Simulation time 482160905 ps
CPU time 0.97 seconds
Started Mar 28 12:32:00 PM PDT 24
Finished Mar 28 12:32:01 PM PDT 24
Peak memory 201436 kb
Host smart-14e918c0-b186-4d92-8bcf-98d21cdb2da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727896302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3727896302
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.766192748
Short name T867
Test name
Test status
Simulation time 313736979 ps
CPU time 0.87 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201576 kb
Host smart-d4c2999d-4aa3-4dde-b932-2517d2cbae0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766192748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.766192748
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.382379516
Short name T838
Test name
Test status
Simulation time 4292586409 ps
CPU time 8.43 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:18 PM PDT 24
Peak memory 201832 kb
Host smart-76a38f4c-ca8a-46bf-a74a-74bca3ef6920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382379516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.382379516
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.715792078
Short name T83
Test name
Test status
Simulation time 485120992 ps
CPU time 1.6 seconds
Started Mar 28 12:32:08 PM PDT 24
Finished Mar 28 12:32:10 PM PDT 24
Peak memory 201912 kb
Host smart-5aaf20fc-6219-4b0b-a82e-950c2f370c70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715792078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.715792078
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3296202000
Short name T335
Test name
Test status
Simulation time 8398541343 ps
CPU time 22.95 seconds
Started Mar 28 12:32:05 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201928 kb
Host smart-9552c530-6e9c-449a-86da-cb8d1f381cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296202000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3296202000
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3446049985
Short name T686
Test name
Test status
Simulation time 305765448 ps
CPU time 1.29 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:03:30 PM PDT 24
Peak memory 201472 kb
Host smart-afdbb828-b394-4054-8828-2550c584cc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446049985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3446049985
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4202960296
Short name T184
Test name
Test status
Simulation time 496607994417 ps
CPU time 250.06 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:07:35 PM PDT 24
Peak memory 201976 kb
Host smart-a86b31a7-8487-445f-914d-557e8a142e81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202960296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4202960296
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2959876942
Short name T689
Test name
Test status
Simulation time 325398439026 ps
CPU time 357.61 seconds
Started Mar 28 01:03:23 PM PDT 24
Finished Mar 28 01:09:21 PM PDT 24
Peak memory 201952 kb
Host smart-d37c16f8-9def-4b50-8146-586856377f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959876942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2959876942
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1850091855
Short name T786
Test name
Test status
Simulation time 170025134762 ps
CPU time 264.27 seconds
Started Mar 28 01:03:22 PM PDT 24
Finished Mar 28 01:07:47 PM PDT 24
Peak memory 201868 kb
Host smart-5edf33af-39f5-4e44-9d0e-821ad7d4dea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850091855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1850091855
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.708814500
Short name T780
Test name
Test status
Simulation time 494795642501 ps
CPU time 297.15 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:08:21 PM PDT 24
Peak memory 201764 kb
Host smart-4c50f36d-422a-401c-b1f3-0d4c1d4fec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708814500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.708814500
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1589810679
Short name T495
Test name
Test status
Simulation time 167445697689 ps
CPU time 402.85 seconds
Started Mar 28 01:03:26 PM PDT 24
Finished Mar 28 01:10:09 PM PDT 24
Peak memory 201948 kb
Host smart-9c80bfe3-ee4e-4d3b-9a0f-debd46f14c17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589810679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1589810679
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2107079446
Short name T430
Test name
Test status
Simulation time 208037306063 ps
CPU time 131.63 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:05:36 PM PDT 24
Peak memory 201832 kb
Host smart-cb6587f0-d09c-4604-8b5e-6a4c6b511f4b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107079446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2107079446
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2285420846
Short name T164
Test name
Test status
Simulation time 75403876831 ps
CPU time 425.67 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:10:30 PM PDT 24
Peak memory 202248 kb
Host smart-f7b8f138-5e03-407f-a574-4383489d298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285420846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2285420846
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1392905636
Short name T349
Test name
Test status
Simulation time 30884520765 ps
CPU time 35.91 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:04:00 PM PDT 24
Peak memory 201696 kb
Host smart-192374a5-24f1-40a8-8f35-eb87c75135c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392905636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1392905636
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.19028958
Short name T620
Test name
Test status
Simulation time 2887673856 ps
CPU time 2.56 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:03:31 PM PDT 24
Peak memory 201560 kb
Host smart-e5b80f42-73fc-487a-8445-6544b98c2eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19028958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.19028958
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3053636438
Short name T552
Test name
Test status
Simulation time 5534610264 ps
CPU time 13.34 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:03:38 PM PDT 24
Peak memory 201616 kb
Host smart-2ffa7c43-f644-4e52-8701-2f31ccfe31a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053636438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3053636438
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3931872935
Short name T710
Test name
Test status
Simulation time 4902869228 ps
CPU time 3.56 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:03:28 PM PDT 24
Peak memory 201664 kb
Host smart-f69324a8-9271-4976-b5a8-1812db8ec7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931872935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3931872935
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.859258762
Short name T255
Test name
Test status
Simulation time 352500521528 ps
CPU time 438 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 218120 kb
Host smart-5f13f5c0-e235-416f-8209-fcc7142c793c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859258762 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.859258762
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2122492133
Short name T374
Test name
Test status
Simulation time 475360208 ps
CPU time 0.9 seconds
Started Mar 28 01:03:26 PM PDT 24
Finished Mar 28 01:03:27 PM PDT 24
Peak memory 201524 kb
Host smart-ba73b993-dcd3-4cd6-8e41-626779b3e278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122492133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2122492133
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2253164320
Short name T273
Test name
Test status
Simulation time 325974660301 ps
CPU time 182.9 seconds
Started Mar 28 01:03:34 PM PDT 24
Finished Mar 28 01:06:37 PM PDT 24
Peak memory 201976 kb
Host smart-e069a1fc-a778-4c8d-aae7-5cac5c0448b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253164320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2253164320
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.971066148
Short name T225
Test name
Test status
Simulation time 492848489948 ps
CPU time 316.21 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:08:45 PM PDT 24
Peak memory 201832 kb
Host smart-dd0d3b58-f6f2-464e-991b-82ba11f8dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971066148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.971066148
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3825897291
Short name T357
Test name
Test status
Simulation time 493064323621 ps
CPU time 1039.2 seconds
Started Mar 28 01:03:33 PM PDT 24
Finished Mar 28 01:20:53 PM PDT 24
Peak memory 201880 kb
Host smart-7c6c6238-7df7-4a0d-abfe-6a99a8d042bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825897291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3825897291
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3152022182
Short name T526
Test name
Test status
Simulation time 493185651532 ps
CPU time 1150.25 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:22:39 PM PDT 24
Peak memory 201716 kb
Host smart-63870a82-5d4e-4979-8698-70b256c38fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152022182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3152022182
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.744039521
Short name T550
Test name
Test status
Simulation time 498043150369 ps
CPU time 1155.21 seconds
Started Mar 28 01:03:27 PM PDT 24
Finished Mar 28 01:22:44 PM PDT 24
Peak memory 201700 kb
Host smart-6317a9e7-cc81-44e3-a98c-7c8404aa2783
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=744039521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.744039521
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1133697682
Short name T141
Test name
Test status
Simulation time 187308580821 ps
CPU time 69.64 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:04:35 PM PDT 24
Peak memory 201972 kb
Host smart-d1fd652e-f4a5-4224-9bb7-75a849b2b4b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133697682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1133697682
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1545880896
Short name T143
Test name
Test status
Simulation time 403788390894 ps
CPU time 56.34 seconds
Started Mar 28 01:03:26 PM PDT 24
Finished Mar 28 01:04:23 PM PDT 24
Peak memory 201884 kb
Host smart-619a14a8-51e8-4fb9-8b8a-3877fbe68f9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545880896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1545880896
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2683016237
Short name T755
Test name
Test status
Simulation time 70276184394 ps
CPU time 229.81 seconds
Started Mar 28 01:03:34 PM PDT 24
Finished Mar 28 01:07:24 PM PDT 24
Peak memory 202176 kb
Host smart-135f8f86-c5d5-4d66-b80b-1379bb621d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683016237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2683016237
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3890978339
Short name T402
Test name
Test status
Simulation time 46209510926 ps
CPU time 91.05 seconds
Started Mar 28 01:03:33 PM PDT 24
Finished Mar 28 01:05:04 PM PDT 24
Peak memory 201708 kb
Host smart-7ef7ffe5-a8d2-404f-bd22-a23a41892418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890978339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3890978339
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.969418616
Short name T389
Test name
Test status
Simulation time 3821394223 ps
CPU time 2.28 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:03:26 PM PDT 24
Peak memory 201672 kb
Host smart-3439bc12-6e9b-42d2-9908-c6b346faca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969418616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.969418616
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3943158323
Short name T74
Test name
Test status
Simulation time 4632261559 ps
CPU time 3.55 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:03:27 PM PDT 24
Peak memory 217532 kb
Host smart-6e4eadb1-5f8d-416f-a664-d972c0879646
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943158323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3943158323
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3515473229
Short name T350
Test name
Test status
Simulation time 5701983768 ps
CPU time 7.47 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:03:36 PM PDT 24
Peak memory 201712 kb
Host smart-2e9cdd21-cdca-4361-9c32-03280441d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515473229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3515473229
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.18795820
Short name T80
Test name
Test status
Simulation time 160199986250 ps
CPU time 101.01 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:05:07 PM PDT 24
Peak memory 201816 kb
Host smart-0274df15-fd43-41eb-ae01-9660758e3b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18795820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.18795820
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1530964662
Short name T9
Test name
Test status
Simulation time 12146474035 ps
CPU time 24.76 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:03:49 PM PDT 24
Peak memory 202100 kb
Host smart-84ebb4db-d944-4594-b7e1-225ea48286cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530964662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1530964662
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.594291185
Short name T477
Test name
Test status
Simulation time 465221315 ps
CPU time 1.65 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:04:05 PM PDT 24
Peak memory 201584 kb
Host smart-e3792203-7608-4271-b35f-bc99fe31b305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594291185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.594291185
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2172734807
Short name T191
Test name
Test status
Simulation time 536176167365 ps
CPU time 193.65 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:07:20 PM PDT 24
Peak memory 201828 kb
Host smart-d20c3cc9-37df-417e-95d4-1d885fd383cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172734807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2172734807
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1419022625
Short name T524
Test name
Test status
Simulation time 163106705804 ps
CPU time 379.21 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:10:24 PM PDT 24
Peak memory 201948 kb
Host smart-12c13ae0-efc1-4eed-ba48-b35bd92f8ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419022625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1419022625
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.559304041
Short name T502
Test name
Test status
Simulation time 492310010005 ps
CPU time 1108.42 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 201740 kb
Host smart-2c828e35-720e-4a74-8b0d-f9a599ee5c77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=559304041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.559304041
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4141657785
Short name T782
Test name
Test status
Simulation time 328153000466 ps
CPU time 217.49 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:07:41 PM PDT 24
Peak memory 201960 kb
Host smart-d9b8272e-89b8-42d2-a9ee-e85c0cdf0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141657785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4141657785
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2362034042
Short name T738
Test name
Test status
Simulation time 324880423065 ps
CPU time 432.62 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 201880 kb
Host smart-a78fa183-e0fc-4c16-b6f2-5b7283b04e88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362034042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2362034042
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.111224905
Short name T596
Test name
Test status
Simulation time 201499945892 ps
CPU time 249.54 seconds
Started Mar 28 01:04:09 PM PDT 24
Finished Mar 28 01:08:19 PM PDT 24
Peak memory 201928 kb
Host smart-f0d5484e-6e31-4be6-a02a-446d5870475d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111224905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.111224905
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1580789956
Short name T606
Test name
Test status
Simulation time 621620483437 ps
CPU time 864.66 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:18:30 PM PDT 24
Peak memory 201852 kb
Host smart-a3561338-f030-434a-acf6-3f638669ba90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580789956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1580789956
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1812054194
Short name T221
Test name
Test status
Simulation time 118011868201 ps
CPU time 479.79 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:12:06 PM PDT 24
Peak memory 202224 kb
Host smart-e71cbe51-b7fa-4cb8-9b87-5ea74a967ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812054194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1812054194
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2284598434
Short name T772
Test name
Test status
Simulation time 23204814372 ps
CPU time 29.82 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:04:34 PM PDT 24
Peak memory 201696 kb
Host smart-9755ba51-d72f-43c9-8f43-e9e407831aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284598434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2284598434
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1583175821
Short name T457
Test name
Test status
Simulation time 4159762358 ps
CPU time 1.97 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:04:07 PM PDT 24
Peak memory 201712 kb
Host smart-331403a9-4d2d-463e-afbb-ff7520bb6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583175821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1583175821
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1317193144
Short name T432
Test name
Test status
Simulation time 5653970110 ps
CPU time 3.81 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:04:08 PM PDT 24
Peak memory 201704 kb
Host smart-695b4add-70d3-4b50-943b-8bfad46270e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317193144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1317193144
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.940538269
Short name T787
Test name
Test status
Simulation time 219024113508 ps
CPU time 64.91 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:05:11 PM PDT 24
Peak memory 201948 kb
Host smart-60808118-5335-4edd-bd3a-6aa2d6d5659f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940538269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
940538269
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.945793895
Short name T696
Test name
Test status
Simulation time 474488889 ps
CPU time 0.9 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:04:23 PM PDT 24
Peak memory 201584 kb
Host smart-b6537aa3-817a-4a44-982b-fc4b06de9a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945793895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.945793895
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.353454185
Short name T789
Test name
Test status
Simulation time 339014986560 ps
CPU time 795.98 seconds
Started Mar 28 01:04:10 PM PDT 24
Finished Mar 28 01:17:26 PM PDT 24
Peak memory 201808 kb
Host smart-da4f3fd0-a0ec-4642-9d7e-7977dc6d06eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353454185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.353454185
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3174921006
Short name T89
Test name
Test status
Simulation time 167348909285 ps
CPU time 202.17 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:07:29 PM PDT 24
Peak memory 201852 kb
Host smart-a439d939-468d-44cc-bf51-ef7ec4ebad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174921006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3174921006
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2058190573
Short name T481
Test name
Test status
Simulation time 162195174540 ps
CPU time 349.51 seconds
Started Mar 28 01:04:07 PM PDT 24
Finished Mar 28 01:09:57 PM PDT 24
Peak memory 201940 kb
Host smart-250277e6-d99c-4ffd-88df-01f662733ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058190573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2058190573
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1886120171
Short name T494
Test name
Test status
Simulation time 324478831579 ps
CPU time 784.19 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:17:09 PM PDT 24
Peak memory 201700 kb
Host smart-d2510833-40ce-459e-85bf-01098811ff90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886120171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1886120171
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2059679219
Short name T233
Test name
Test status
Simulation time 326379932949 ps
CPU time 392.38 seconds
Started Mar 28 01:04:08 PM PDT 24
Finished Mar 28 01:10:40 PM PDT 24
Peak memory 201800 kb
Host smart-8b66173e-cb11-470c-a2f4-59ef3d0287cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059679219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2059679219
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2529557074
Short name T628
Test name
Test status
Simulation time 322625208230 ps
CPU time 181.63 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 201964 kb
Host smart-8a290d40-8d6b-4042-9b5b-c9b79fff58ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529557074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2529557074
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3250991364
Short name T702
Test name
Test status
Simulation time 391089427292 ps
CPU time 888.5 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:18:55 PM PDT 24
Peak memory 201872 kb
Host smart-734f882e-c1e4-4dae-86d3-2a9aaa35d118
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250991364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3250991364
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3219871426
Short name T517
Test name
Test status
Simulation time 632509610444 ps
CPU time 1316.05 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:26:03 PM PDT 24
Peak memory 201872 kb
Host smart-baa856da-6a2a-40fe-b5aa-9abeed87e87d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219871426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3219871426
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3675485356
Short name T8
Test name
Test status
Simulation time 95043013185 ps
CPU time 343.68 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:10:07 PM PDT 24
Peak memory 202260 kb
Host smart-b3d4f279-5abf-4440-84ea-98ef139d2bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675485356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3675485356
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4151727938
Short name T454
Test name
Test status
Simulation time 34551830522 ps
CPU time 25.28 seconds
Started Mar 28 01:04:08 PM PDT 24
Finished Mar 28 01:04:33 PM PDT 24
Peak memory 201628 kb
Host smart-aa05d281-69fc-4225-9575-c3cfd40f0698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151727938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4151727938
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.49783712
Short name T556
Test name
Test status
Simulation time 2900240995 ps
CPU time 2.17 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:04:09 PM PDT 24
Peak memory 201676 kb
Host smart-205b29cf-1517-4d8c-a70d-fc046d95240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49783712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.49783712
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3689374366
Short name T501
Test name
Test status
Simulation time 5946480421 ps
CPU time 4.27 seconds
Started Mar 28 01:04:10 PM PDT 24
Finished Mar 28 01:04:14 PM PDT 24
Peak memory 201620 kb
Host smart-a001956c-63bd-446f-af11-3ec4653b3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689374366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3689374366
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1899292754
Short name T414
Test name
Test status
Simulation time 123310086966 ps
CPU time 294.03 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:09:17 PM PDT 24
Peak memory 210300 kb
Host smart-17ba5147-3f49-407b-9df3-f78b3f5396eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899292754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1899292754
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.843832049
Short name T52
Test name
Test status
Simulation time 65734347255 ps
CPU time 157.79 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:06:59 PM PDT 24
Peak memory 217928 kb
Host smart-44a3e020-41c0-4af7-8207-b607bc87c329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843832049 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.843832049
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2594598308
Short name T725
Test name
Test status
Simulation time 458423277 ps
CPU time 0.9 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:04:22 PM PDT 24
Peak memory 201516 kb
Host smart-f50427f9-3e6f-44b2-8223-6455b4653beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594598308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2594598308
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.103612467
Short name T316
Test name
Test status
Simulation time 588398887755 ps
CPU time 241.06 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:08:25 PM PDT 24
Peak memory 201808 kb
Host smart-1b997aba-b053-43b7-9fe9-f0bc27bde825
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103612467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.103612467
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1796321463
Short name T195
Test name
Test status
Simulation time 350979452074 ps
CPU time 797.64 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:17:40 PM PDT 24
Peak memory 201876 kb
Host smart-74a5df7f-2baf-46e4-a787-2ee50447849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796321463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1796321463
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2821546342
Short name T669
Test name
Test status
Simulation time 164748968811 ps
CPU time 98.71 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:06:02 PM PDT 24
Peak memory 201720 kb
Host smart-8948deb1-2c5f-4246-a61f-148d6ab1fea6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821546342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2821546342
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1964175834
Short name T643
Test name
Test status
Simulation time 334449957415 ps
CPU time 400.68 seconds
Started Mar 28 01:04:20 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 201976 kb
Host smart-a8864d1a-0235-4fe9-afdb-046c9d52c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964175834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1964175834
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4101543278
Short name T426
Test name
Test status
Simulation time 497714000428 ps
CPU time 284.04 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:09:05 PM PDT 24
Peak memory 201880 kb
Host smart-e4594248-75dd-457a-a8b0-267b16b09a5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101543278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4101543278
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4070434743
Short name T752
Test name
Test status
Simulation time 392813930047 ps
CPU time 963.2 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:20:27 PM PDT 24
Peak memory 201800 kb
Host smart-f0a0db2d-faec-4d11-9b3b-f2abda18c26a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070434743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4070434743
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.243605283
Short name T95
Test name
Test status
Simulation time 98660224726 ps
CPU time 348.93 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 202136 kb
Host smart-d7d00ea7-0118-4e34-a56d-59eb0530b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243605283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.243605283
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2712369590
Short name T579
Test name
Test status
Simulation time 41035418197 ps
CPU time 12.07 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:04:36 PM PDT 24
Peak memory 201632 kb
Host smart-5c054b98-012f-42ba-aaa1-f37023143426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712369590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2712369590
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3219818708
Short name T417
Test name
Test status
Simulation time 4934571469 ps
CPU time 3.41 seconds
Started Mar 28 01:04:26 PM PDT 24
Finished Mar 28 01:04:29 PM PDT 24
Peak memory 201652 kb
Host smart-3e1991ca-92b7-4df4-930d-8cbac38cc3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219818708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3219818708
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3600875537
Short name T497
Test name
Test status
Simulation time 5770612302 ps
CPU time 13.87 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:04:38 PM PDT 24
Peak memory 201620 kb
Host smart-8586c79d-8c68-490b-a936-06abf712e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600875537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3600875537
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2135014933
Short name T249
Test name
Test status
Simulation time 182206981169 ps
CPU time 72.97 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:05:37 PM PDT 24
Peak memory 201920 kb
Host smart-1230bc6e-c134-404d-9d7a-1f07fce5d8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135014933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2135014933
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3377605755
Short name T707
Test name
Test status
Simulation time 137219342345 ps
CPU time 86.9 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:05:52 PM PDT 24
Peak memory 210264 kb
Host smart-fc90bccc-144c-4203-a441-c79c7a34a08a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377605755 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3377605755
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2635968798
Short name T721
Test name
Test status
Simulation time 297625998 ps
CPU time 0.97 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:04:25 PM PDT 24
Peak memory 201568 kb
Host smart-f15c3e68-c18a-47de-a95f-854898ebaef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635968798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2635968798
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3834366275
Short name T160
Test name
Test status
Simulation time 325296413274 ps
CPU time 87.09 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:05:52 PM PDT 24
Peak memory 201988 kb
Host smart-cb2ec480-2ad3-41fa-b508-711e2e8462f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834366275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3834366275
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2471703033
Short name T235
Test name
Test status
Simulation time 162393280455 ps
CPU time 411.7 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:11:13 PM PDT 24
Peak memory 201888 kb
Host smart-922e4231-9f94-4cba-bbe3-f88189302bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471703033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2471703033
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1245658316
Short name T673
Test name
Test status
Simulation time 334735379155 ps
CPU time 111.54 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:06:16 PM PDT 24
Peak memory 201832 kb
Host smart-f90271a1-4fc3-4396-a83c-2c63ffe6d8d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245658316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1245658316
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3920824512
Short name T555
Test name
Test status
Simulation time 161015136206 ps
CPU time 344.33 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:10:09 PM PDT 24
Peak memory 201928 kb
Host smart-d45d41e5-304b-4170-a6a5-b1aa4ec7da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920824512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3920824512
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1375636343
Short name T46
Test name
Test status
Simulation time 161641303070 ps
CPU time 264.61 seconds
Started Mar 28 01:04:26 PM PDT 24
Finished Mar 28 01:08:51 PM PDT 24
Peak memory 201828 kb
Host smart-b6e814bd-27ae-4f31-8e70-ecfe203bec1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375636343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1375636343
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.916128240
Short name T202
Test name
Test status
Simulation time 552021120908 ps
CPU time 336.27 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:10:00 PM PDT 24
Peak memory 201976 kb
Host smart-1dff4e2a-a594-4860-91f3-16b8a462ce06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916128240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.916128240
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1242071407
Short name T796
Test name
Test status
Simulation time 198496804370 ps
CPU time 125.76 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:06:33 PM PDT 24
Peak memory 201800 kb
Host smart-316a78c4-e88f-4a58-80ea-ac92800dc075
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242071407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1242071407
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3592669566
Short name T594
Test name
Test status
Simulation time 93516542007 ps
CPU time 491.42 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:12:36 PM PDT 24
Peak memory 202176 kb
Host smart-e616bb05-03c8-49e1-85e1-ef2c479f8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592669566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3592669566
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4157457221
Short name T741
Test name
Test status
Simulation time 30918606212 ps
CPU time 69.8 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:05:32 PM PDT 24
Peak memory 201624 kb
Host smart-eec7dbc1-11ad-4580-b4b7-8dd658dbb1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157457221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4157457221
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.93067722
Short name T373
Test name
Test status
Simulation time 4907600880 ps
CPU time 12.36 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:04:37 PM PDT 24
Peak memory 201608 kb
Host smart-af1df5dd-f790-4ef1-92cd-4c415ffb97f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93067722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.93067722
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.325197742
Short name T735
Test name
Test status
Simulation time 5819134707 ps
CPU time 15.88 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:04:40 PM PDT 24
Peak memory 201548 kb
Host smart-9e47957f-1490-4652-beb3-3ec12edef36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325197742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.325197742
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.580547380
Short name T216
Test name
Test status
Simulation time 367644660581 ps
CPU time 488.42 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:12:32 PM PDT 24
Peak memory 210448 kb
Host smart-7b4fb4a4-7ee7-48c7-9d93-c6a0ae3d3fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580547380 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.580547380
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.483084809
Short name T388
Test name
Test status
Simulation time 496379551 ps
CPU time 1.62 seconds
Started Mar 28 01:04:29 PM PDT 24
Finished Mar 28 01:04:30 PM PDT 24
Peak memory 201528 kb
Host smart-46dbdb6f-3bf3-407d-bc03-b63f4887516f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483084809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.483084809
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1241869018
Short name T767
Test name
Test status
Simulation time 325933597339 ps
CPU time 335.86 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 201204 kb
Host smart-9de680fe-3199-4163-ba31-e18c7efd4def
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241869018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1241869018
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3423321138
Short name T289
Test name
Test status
Simulation time 167194363392 ps
CPU time 393.57 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:10:59 PM PDT 24
Peak memory 201880 kb
Host smart-98b88292-0f9c-4550-9b3c-e2b2dcd20926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423321138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3423321138
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.316110975
Short name T677
Test name
Test status
Simulation time 159903488580 ps
CPU time 109.63 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:06:11 PM PDT 24
Peak memory 201800 kb
Host smart-36e141b2-0bce-40d1-8068-722d48fe73e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316110975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.316110975
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.486590010
Short name T713
Test name
Test status
Simulation time 348812891509 ps
CPU time 207.15 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:07:50 PM PDT 24
Peak memory 201860 kb
Host smart-82e98783-bfe0-424f-84d8-d3565d4ec2b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=486590010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.486590010
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.801620584
Short name T270
Test name
Test status
Simulation time 498143639358 ps
CPU time 1063.32 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:22:09 PM PDT 24
Peak memory 201852 kb
Host smart-3d2344ea-2a61-4d37-99cb-1019d53c4d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801620584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.801620584
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.442265594
Short name T1
Test name
Test status
Simulation time 167196931069 ps
CPU time 110.11 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:06:15 PM PDT 24
Peak memory 201352 kb
Host smart-f3087a8c-65c0-4bce-8953-b5eab0478f40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=442265594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.442265594
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1490741250
Short name T260
Test name
Test status
Simulation time 373141679579 ps
CPU time 901.22 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:19:30 PM PDT 24
Peak memory 201976 kb
Host smart-8a230b16-732d-449c-b7d0-81ee470b709c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490741250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1490741250
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.771444808
Short name T381
Test name
Test status
Simulation time 385391344451 ps
CPU time 256.32 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:08:38 PM PDT 24
Peak memory 201864 kb
Host smart-8813ead6-794d-47ec-8209-adee9e2b5744
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771444808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.771444808
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3706387052
Short name T663
Test name
Test status
Simulation time 87910638033 ps
CPU time 325.35 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:09:47 PM PDT 24
Peak memory 202184 kb
Host smart-6121830e-66a6-4bab-b905-6a172ee7a340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706387052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3706387052
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1504886142
Short name T573
Test name
Test status
Simulation time 43332362035 ps
CPU time 97.29 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:05:59 PM PDT 24
Peak memory 201696 kb
Host smart-af8a08bf-2c88-4a47-8ee9-ad948aac8286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504886142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1504886142
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2344775374
Short name T341
Test name
Test status
Simulation time 3684126743 ps
CPU time 5.46 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:04:28 PM PDT 24
Peak memory 201632 kb
Host smart-4381441c-c302-455c-8e6a-d3e5a26b5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344775374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2344775374
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1042290074
Short name T591
Test name
Test status
Simulation time 5976423683 ps
CPU time 1.62 seconds
Started Mar 28 01:04:20 PM PDT 24
Finished Mar 28 01:04:22 PM PDT 24
Peak memory 201716 kb
Host smart-1014f5c3-c4cc-4f76-8fea-9fc5793efab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042290074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1042290074
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.400794975
Short name T709
Test name
Test status
Simulation time 170680549999 ps
CPU time 44.32 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:05:05 PM PDT 24
Peak memory 201812 kb
Host smart-94191cf5-36f6-4d6a-8649-9bd59b75dc1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400794975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
400794975
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1228629570
Short name T379
Test name
Test status
Simulation time 352962748 ps
CPU time 0.8 seconds
Started Mar 28 01:04:21 PM PDT 24
Finished Mar 28 01:04:22 PM PDT 24
Peak memory 201568 kb
Host smart-bb56b1ff-eeaa-4e5e-9bcd-11f2e93e0cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228629570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1228629570
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1529120570
Short name T581
Test name
Test status
Simulation time 165606259217 ps
CPU time 93.31 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:06:02 PM PDT 24
Peak memory 201932 kb
Host smart-bd354df4-3d82-4c6f-bef8-aabd53b4587f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529120570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1529120570
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.901111179
Short name T259
Test name
Test status
Simulation time 325142627868 ps
CPU time 764.73 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:17:13 PM PDT 24
Peak memory 201896 kb
Host smart-299cedaf-d0e9-4c70-b0b0-98bdca82529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901111179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.901111179
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2067381575
Short name T458
Test name
Test status
Simulation time 492302049241 ps
CPU time 1140.8 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:23:30 PM PDT 24
Peak memory 201828 kb
Host smart-4759cbc4-b698-49c2-bee5-2b26b50ef050
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067381575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2067381575
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2166690259
Short name T171
Test name
Test status
Simulation time 166212266421 ps
CPU time 401.58 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201936 kb
Host smart-1687afb1-f952-43d4-9cfc-6551aeac6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166690259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2166690259
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.371006957
Short name T395
Test name
Test status
Simulation time 329983122600 ps
CPU time 745.17 seconds
Started Mar 28 01:04:29 PM PDT 24
Finished Mar 28 01:16:54 PM PDT 24
Peak memory 201876 kb
Host smart-8916af9b-2135-4327-9725-c512fd98f427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371006957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.371006957
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.314203881
Short name T442
Test name
Test status
Simulation time 406230547169 ps
CPU time 253.43 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:08:42 PM PDT 24
Peak memory 201832 kb
Host smart-e0f0e127-df8f-4eb2-a8ba-e3453be69141
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314203881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.314203881
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2483199513
Short name T339
Test name
Test status
Simulation time 78806739357 ps
CPU time 263.52 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:08:48 PM PDT 24
Peak memory 202092 kb
Host smart-27ffac09-e761-4525-b02e-505211e7692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483199513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2483199513
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3817775948
Short name T345
Test name
Test status
Simulation time 31749674823 ps
CPU time 63.12 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:05:29 PM PDT 24
Peak memory 201704 kb
Host smart-fec46aac-d174-4960-8751-69c8026f72d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817775948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3817775948
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.479970189
Short name T544
Test name
Test status
Simulation time 4943604027 ps
CPU time 9.78 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:04:38 PM PDT 24
Peak memory 201668 kb
Host smart-db2b71dd-268d-4879-8472-c090171b4890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479970189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.479970189
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3804451393
Short name T778
Test name
Test status
Simulation time 5662124008 ps
CPU time 13.04 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:04:42 PM PDT 24
Peak memory 201648 kb
Host smart-afdd9cb3-11d0-4bb3-a220-178de73b26f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804451393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3804451393
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2181834057
Short name T617
Test name
Test status
Simulation time 36161154437 ps
CPU time 41.59 seconds
Started Mar 28 01:04:24 PM PDT 24
Finished Mar 28 01:05:05 PM PDT 24
Peak memory 201620 kb
Host smart-9460f939-fdb5-41b2-af87-e071b0770c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181834057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2181834057
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3004978757
Short name T595
Test name
Test status
Simulation time 301388448511 ps
CPU time 160.69 seconds
Started Mar 28 01:04:26 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 210144 kb
Host smart-d36a8b58-77a6-4144-9fc6-8f4710881a78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004978757 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3004978757
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4130926105
Short name T750
Test name
Test status
Simulation time 476595991 ps
CPU time 0.87 seconds
Started Mar 28 01:04:26 PM PDT 24
Finished Mar 28 01:04:27 PM PDT 24
Peak memory 201556 kb
Host smart-85338982-b0a7-4a06-a61e-1423330cb9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130926105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4130926105
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1940852667
Short name T32
Test name
Test status
Simulation time 491945795692 ps
CPU time 943.29 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 201952 kb
Host smart-9d404934-a244-44fc-b158-43049cd5646d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940852667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1940852667
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1384875180
Short name T599
Test name
Test status
Simulation time 520024216620 ps
CPU time 1157.31 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:23:46 PM PDT 24
Peak memory 201868 kb
Host smart-15a03ca8-e700-483f-877b-5415dd19588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384875180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1384875180
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.685601355
Short name T92
Test name
Test status
Simulation time 163336195523 ps
CPU time 94.62 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:06:00 PM PDT 24
Peak memory 201888 kb
Host smart-6f02f2c7-0463-4d85-a542-684245cc0eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685601355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.685601355
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1490047688
Short name T584
Test name
Test status
Simulation time 322404965661 ps
CPU time 402.93 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 201860 kb
Host smart-a7facfef-3efc-484c-bcac-b139b2ea5a09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490047688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1490047688
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.835254376
Short name T597
Test name
Test status
Simulation time 489969439966 ps
CPU time 874.21 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:19:03 PM PDT 24
Peak memory 201940 kb
Host smart-39b3b746-f2da-4871-a6e9-2cbe39232e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835254376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.835254376
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.671570524
Short name T367
Test name
Test status
Simulation time 321276397059 ps
CPU time 225.86 seconds
Started Mar 28 01:04:27 PM PDT 24
Finished Mar 28 01:08:13 PM PDT 24
Peak memory 201848 kb
Host smart-6f36cb64-b9cf-46d0-8792-2e70c2931cd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=671570524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.671570524
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3643906158
Short name T317
Test name
Test status
Simulation time 178508674481 ps
CPU time 95.39 seconds
Started Mar 28 01:04:22 PM PDT 24
Finished Mar 28 01:05:58 PM PDT 24
Peak memory 201888 kb
Host smart-526ab4bf-f347-42c3-b903-9ec85b07e9d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643906158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3643906158
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1315450636
Short name T360
Test name
Test status
Simulation time 401998270601 ps
CPU time 841.15 seconds
Started Mar 28 01:04:23 PM PDT 24
Finished Mar 28 01:18:25 PM PDT 24
Peak memory 201884 kb
Host smart-dcca1c72-9455-4ee7-af77-cbfc7dcf25c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315450636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1315450636
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2896150429
Short name T510
Test name
Test status
Simulation time 100526644163 ps
CPU time 428.64 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 202140 kb
Host smart-de9bf1b2-f862-4143-81a4-50e01c2748ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896150429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2896150429
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3677019465
Short name T377
Test name
Test status
Simulation time 35250284469 ps
CPU time 20.4 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:04:46 PM PDT 24
Peak memory 201696 kb
Host smart-83708545-c929-42e8-8cdf-0826cfa41cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677019465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3677019465
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3576612181
Short name T476
Test name
Test status
Simulation time 4967345898 ps
CPU time 5.22 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:04:30 PM PDT 24
Peak memory 201692 kb
Host smart-2b4e00df-45c7-4e27-8d9a-3cdede660a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576612181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3576612181
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2042837236
Short name T676
Test name
Test status
Simulation time 5815941755 ps
CPU time 4.23 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:04:33 PM PDT 24
Peak memory 201652 kb
Host smart-4b5abfd5-5085-4fdd-85b0-e9c1aa9127ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042837236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2042837236
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3833469326
Short name T315
Test name
Test status
Simulation time 61740177048 ps
CPU time 152.55 seconds
Started Mar 28 01:04:28 PM PDT 24
Finished Mar 28 01:07:01 PM PDT 24
Peak memory 211476 kb
Host smart-305c14e7-9906-4279-93a4-03e7f01be61b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833469326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3833469326
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.686682472
Short name T557
Test name
Test status
Simulation time 310681404 ps
CPU time 1.1 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:04:47 PM PDT 24
Peak memory 201552 kb
Host smart-9f388311-82c3-48a8-bf10-d9b955a2dcfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686682472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.686682472
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.715847344
Short name T200
Test name
Test status
Simulation time 340151372270 ps
CPU time 707.87 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:16:31 PM PDT 24
Peak memory 202016 kb
Host smart-246f6a43-c1dc-46d1-a349-e2c93150514c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715847344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.715847344
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3489783175
Short name T769
Test name
Test status
Simulation time 171979130788 ps
CPU time 105.7 seconds
Started Mar 28 01:04:52 PM PDT 24
Finished Mar 28 01:06:39 PM PDT 24
Peak memory 201860 kb
Host smart-4f0c20f2-21a8-490c-895b-ed692c076f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489783175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3489783175
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2875589911
Short name T551
Test name
Test status
Simulation time 490964510151 ps
CPU time 286.24 seconds
Started Mar 28 01:04:30 PM PDT 24
Finished Mar 28 01:09:16 PM PDT 24
Peak memory 201720 kb
Host smart-1f951a79-32a5-4fa5-8acc-a79115698169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875589911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2875589911
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3984796439
Short name T467
Test name
Test status
Simulation time 163574411405 ps
CPU time 402.81 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:11:08 PM PDT 24
Peak memory 201860 kb
Host smart-eb9e6833-988c-44af-8b69-63462c0ec233
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984796439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3984796439
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2472187039
Short name T492
Test name
Test status
Simulation time 164516401816 ps
CPU time 97.73 seconds
Started Mar 28 01:04:25 PM PDT 24
Finished Mar 28 01:06:04 PM PDT 24
Peak memory 201892 kb
Host smart-1808d77b-4180-4e36-9862-307ce6e8213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472187039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2472187039
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2260968424
Short name T185
Test name
Test status
Simulation time 166856811785 ps
CPU time 71.78 seconds
Started Mar 28 01:04:29 PM PDT 24
Finished Mar 28 01:05:41 PM PDT 24
Peak memory 201860 kb
Host smart-5959e97c-fc50-4559-a8d5-3c303c180729
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260968424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2260968424
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.639803620
Short name T261
Test name
Test status
Simulation time 207978136982 ps
CPU time 505.67 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:13:11 PM PDT 24
Peak memory 201804 kb
Host smart-e53c5c31-cfcc-403d-8a1d-3c810ee7c7e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639803620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.639803620
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3787542457
Short name T546
Test name
Test status
Simulation time 618881447213 ps
CPU time 1509.32 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:29:56 PM PDT 24
Peak memory 201968 kb
Host smart-adfa3087-1bc7-4df1-b1be-0b9947b774bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787542457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3787542457
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.830247724
Short name T407
Test name
Test status
Simulation time 92102557264 ps
CPU time 278.65 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:09:29 PM PDT 24
Peak memory 202248 kb
Host smart-24f1a8ec-5ad0-4cff-bed6-8afd4eebe612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830247724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.830247724
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1809772673
Short name T616
Test name
Test status
Simulation time 27137061334 ps
CPU time 29.52 seconds
Started Mar 28 01:04:41 PM PDT 24
Finished Mar 28 01:05:13 PM PDT 24
Peak memory 201624 kb
Host smart-47f55110-73d0-46d1-bd9d-ccbe2faed457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809772673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1809772673
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1614093290
Short name T361
Test name
Test status
Simulation time 5185140987 ps
CPU time 12.33 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:05:13 PM PDT 24
Peak memory 201588 kb
Host smart-793252d7-3304-4d3c-918a-1b7937d88104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614093290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1614093290
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1587640687
Short name T668
Test name
Test status
Simulation time 5753750058 ps
CPU time 7.81 seconds
Started Mar 28 01:04:29 PM PDT 24
Finished Mar 28 01:04:37 PM PDT 24
Peak memory 201680 kb
Host smart-0b863dbc-7813-4da5-9aa5-5a78ebc5d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587640687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1587640687
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2269287332
Short name T682
Test name
Test status
Simulation time 498981220378 ps
CPU time 320.75 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:10:11 PM PDT 24
Peak memory 201708 kb
Host smart-0637f035-a494-4c48-b5ac-e419e01ad618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269287332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2269287332
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1234146046
Short name T327
Test name
Test status
Simulation time 208720079727 ps
CPU time 198.63 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:08:04 PM PDT 24
Peak memory 210476 kb
Host smart-b4cbffd1-c29d-45a2-b9e6-e202b34a2a8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234146046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1234146046
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3680486189
Short name T134
Test name
Test status
Simulation time 323204052074 ps
CPU time 778.12 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:17:42 PM PDT 24
Peak memory 201952 kb
Host smart-81fdab44-eb31-44e2-ac2f-39c5b6239106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680486189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3680486189
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2540687942
Short name T774
Test name
Test status
Simulation time 167552532861 ps
CPU time 117.73 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:06:48 PM PDT 24
Peak memory 201804 kb
Host smart-d0d198c3-42c8-45f5-ad34-172cfd3a55c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540687942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2540687942
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4271439948
Short name T94
Test name
Test status
Simulation time 161819944759 ps
CPU time 75.66 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:06:06 PM PDT 24
Peak memory 201660 kb
Host smart-b8dc122b-dd09-416e-94a8-f5aa52afe854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271439948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4271439948
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3969325937
Short name T390
Test name
Test status
Simulation time 165059036491 ps
CPU time 313.21 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:09:57 PM PDT 24
Peak memory 201916 kb
Host smart-436a671f-5501-43e3-a76a-dc8eface4508
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969325937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3969325937
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4288685486
Short name T793
Test name
Test status
Simulation time 400857882442 ps
CPU time 671.14 seconds
Started Mar 28 01:04:41 PM PDT 24
Finished Mar 28 01:15:55 PM PDT 24
Peak memory 201816 kb
Host smart-ab32fa8e-a46f-4ff6-8730-0b343dec40aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288685486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4288685486
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1382587739
Short name T470
Test name
Test status
Simulation time 133683691198 ps
CPU time 475.19 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:12:44 PM PDT 24
Peak memory 202184 kb
Host smart-a172e804-a9fb-4f52-a0df-0e43fd84b9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382587739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1382587739
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2638551714
Short name T711
Test name
Test status
Simulation time 26445203777 ps
CPU time 60.97 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:05:44 PM PDT 24
Peak memory 201728 kb
Host smart-5fb54698-6325-4b28-a622-051cf8e20ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638551714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2638551714
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3758941711
Short name T443
Test name
Test status
Simulation time 2694597528 ps
CPU time 6.86 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:04:50 PM PDT 24
Peak memory 201696 kb
Host smart-999f50e0-60ba-47ca-83ba-b4329e373bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758941711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3758941711
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4062149420
Short name T571
Test name
Test status
Simulation time 6067832394 ps
CPU time 3.22 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:04:49 PM PDT 24
Peak memory 201704 kb
Host smart-01dba483-41ff-4cd3-93ae-f13002349d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062149420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4062149420
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1917014839
Short name T575
Test name
Test status
Simulation time 142664474299 ps
CPU time 494.07 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:13:00 PM PDT 24
Peak memory 210444 kb
Host smart-cfc180d2-bf38-4098-9dbe-35c1a8cae187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917014839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1917014839
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2746062095
Short name T753
Test name
Test status
Simulation time 26002392900 ps
CPU time 91.46 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:06:17 PM PDT 24
Peak memory 210512 kb
Host smart-8da16495-4636-4ecf-8eff-697151e7e650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746062095 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2746062095
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1629988038
Short name T547
Test name
Test status
Simulation time 498968553 ps
CPU time 1 seconds
Started Mar 28 01:04:48 PM PDT 24
Finished Mar 28 01:04:50 PM PDT 24
Peak memory 201580 kb
Host smart-e0dfaa2d-8b58-4779-9aa9-dfef028bcbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629988038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1629988038
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.804753218
Short name T182
Test name
Test status
Simulation time 524150617822 ps
CPU time 192.01 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:07:58 PM PDT 24
Peak memory 201920 kb
Host smart-5e876da8-405a-4606-b6bb-8576ca4ac77c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804753218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.804753218
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1051713838
Short name T251
Test name
Test status
Simulation time 171322214194 ps
CPU time 382.66 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:11:13 PM PDT 24
Peak memory 201828 kb
Host smart-5c89fac6-aab8-4318-aca2-4b188ee7e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051713838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1051713838
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.740955014
Short name T237
Test name
Test status
Simulation time 328068819854 ps
CPU time 251.72 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:08:55 PM PDT 24
Peak memory 201932 kb
Host smart-43443478-29b2-4e18-921b-7eb5cc16631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740955014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.740955014
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4169469005
Short name T732
Test name
Test status
Simulation time 492490086238 ps
CPU time 132.48 seconds
Started Mar 28 01:04:53 PM PDT 24
Finished Mar 28 01:07:06 PM PDT 24
Peak memory 201800 kb
Host smart-fcd6cec1-5f51-48f6-883a-1f5971f9aff4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169469005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4169469005
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1140525421
Short name T189
Test name
Test status
Simulation time 331489203160 ps
CPU time 132.56 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:06:56 PM PDT 24
Peak memory 201912 kb
Host smart-9d498883-0163-46de-b7d0-23a1705e2eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140525421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1140525421
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.348023641
Short name T380
Test name
Test status
Simulation time 490279091026 ps
CPU time 1051.94 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:22:21 PM PDT 24
Peak memory 201872 kb
Host smart-d82321bf-39af-4025-9dff-5e15bb5c5f19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=348023641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.348023641
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.725266726
Short name T198
Test name
Test status
Simulation time 362634389191 ps
CPU time 420.16 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:11:44 PM PDT 24
Peak memory 201992 kb
Host smart-4ba547f5-67fe-4e81-ac84-b347b04fa4c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725266726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.725266726
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1909167102
Short name T460
Test name
Test status
Simulation time 197908479471 ps
CPU time 421.7 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:11:53 PM PDT 24
Peak memory 201836 kb
Host smart-1e503709-8b76-4d55-a477-d29be20a2e78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909167102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1909167102
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1929812093
Short name T57
Test name
Test status
Simulation time 108356488317 ps
CPU time 531.14 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:13:36 PM PDT 24
Peak memory 202180 kb
Host smart-b2526d57-3db1-4b3f-abb9-8ccd5f896a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929812093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1929812093
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.790983035
Short name T748
Test name
Test status
Simulation time 38906988300 ps
CPU time 9.6 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:05:00 PM PDT 24
Peak memory 201624 kb
Host smart-1f0de39b-5c75-495c-87da-96f415821acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790983035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.790983035
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1496310937
Short name T451
Test name
Test status
Simulation time 4280386514 ps
CPU time 3.37 seconds
Started Mar 28 01:04:52 PM PDT 24
Finished Mar 28 01:04:57 PM PDT 24
Peak memory 201532 kb
Host smart-e14170d3-9acd-47bb-8166-4c54485c4899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496310937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1496310937
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2087760784
Short name T612
Test name
Test status
Simulation time 5564159690 ps
CPU time 4.05 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:04:53 PM PDT 24
Peak memory 201700 kb
Host smart-ae16d518-51b6-4908-a46c-260ebee44abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087760784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2087760784
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.943403749
Short name T105
Test name
Test status
Simulation time 174739753204 ps
CPU time 385.74 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 201852 kb
Host smart-c5c9e1e0-6991-453a-b114-7479a914e616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943403749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
943403749
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1741621444
Short name T278
Test name
Test status
Simulation time 338695594596 ps
CPU time 164.61 seconds
Started Mar 28 01:04:48 PM PDT 24
Finished Mar 28 01:07:32 PM PDT 24
Peak memory 210468 kb
Host smart-bd033168-4ea8-412d-b98a-c0f7834611a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741621444 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1741621444
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3662591365
Short name T569
Test name
Test status
Simulation time 510535092 ps
CPU time 0.95 seconds
Started Mar 28 01:03:29 PM PDT 24
Finished Mar 28 01:03:30 PM PDT 24
Peak memory 201548 kb
Host smart-0c8379d1-aa12-4b5a-8afa-d1aba5eb2890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662591365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3662591365
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3906335552
Short name T574
Test name
Test status
Simulation time 451519070136 ps
CPU time 946.94 seconds
Started Mar 28 01:03:34 PM PDT 24
Finished Mar 28 01:19:21 PM PDT 24
Peak memory 201984 kb
Host smart-67c38d04-0362-4076-b9d6-1b28d00da3d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906335552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3906335552
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3319943161
Short name T626
Test name
Test status
Simulation time 368102200952 ps
CPU time 400.9 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:10:05 PM PDT 24
Peak memory 201964 kb
Host smart-ec012336-8e3a-4697-b01f-660363d31de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319943161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3319943161
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1737888967
Short name T560
Test name
Test status
Simulation time 327601386145 ps
CPU time 193.07 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:06:42 PM PDT 24
Peak memory 201784 kb
Host smart-049307d1-7a0c-4a8e-a33a-8996a8ee1e6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737888967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1737888967
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2930981994
Short name T607
Test name
Test status
Simulation time 164783946764 ps
CPU time 297.82 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:08:27 PM PDT 24
Peak memory 201952 kb
Host smart-7e34c9d2-6246-439c-8f38-6428ed0abd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930981994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2930981994
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1552499690
Short name T355
Test name
Test status
Simulation time 329417386334 ps
CPU time 765.25 seconds
Started Mar 28 01:03:27 PM PDT 24
Finished Mar 28 01:16:13 PM PDT 24
Peak memory 201708 kb
Host smart-345faa95-56d6-4067-97c1-deb7e41add8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552499690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1552499690
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1187841901
Short name T262
Test name
Test status
Simulation time 516232715463 ps
CPU time 107.12 seconds
Started Mar 28 01:03:26 PM PDT 24
Finished Mar 28 01:05:14 PM PDT 24
Peak memory 201928 kb
Host smart-822ed9bc-7206-4bf7-b86d-b06c9e02854e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187841901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1187841901
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2499584640
Short name T429
Test name
Test status
Simulation time 411384942262 ps
CPU time 877.1 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:18:02 PM PDT 24
Peak memory 201832 kb
Host smart-048f0406-7118-49f0-ba2d-655d387d743d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499584640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2499584640
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4138034351
Short name T783
Test name
Test status
Simulation time 29798475757 ps
CPU time 19.23 seconds
Started Mar 28 01:03:27 PM PDT 24
Finished Mar 28 01:03:47 PM PDT 24
Peak memory 201596 kb
Host smart-2e93b7a4-ba51-41a7-94b4-60d3a7598a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138034351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4138034351
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1895604201
Short name T681
Test name
Test status
Simulation time 4463562500 ps
CPU time 5.86 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:03:35 PM PDT 24
Peak memory 201620 kb
Host smart-78947bd0-b75f-4ba0-a84f-368a6d67b00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895604201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1895604201
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3453028961
Short name T88
Test name
Test status
Simulation time 8074802657 ps
CPU time 18.15 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:03:43 PM PDT 24
Peak memory 218320 kb
Host smart-71561153-8960-482b-a035-51acaad4026e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453028961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3453028961
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1116076921
Short name T529
Test name
Test status
Simulation time 5839348571 ps
CPU time 1.64 seconds
Started Mar 28 01:03:28 PM PDT 24
Finished Mar 28 01:03:30 PM PDT 24
Peak memory 201524 kb
Host smart-61b25ae2-bd18-4a67-886f-796fc0b8b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116076921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1116076921
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1149420476
Short name T428
Test name
Test status
Simulation time 102927393780 ps
CPU time 281.16 seconds
Started Mar 28 01:03:24 PM PDT 24
Finished Mar 28 01:08:05 PM PDT 24
Peak memory 202192 kb
Host smart-f0c0b10e-d50d-479b-bfab-d44f984b3ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149420476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1149420476
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2230335
Short name T242
Test name
Test status
Simulation time 100210407448 ps
CPU time 163.75 seconds
Started Mar 28 01:03:33 PM PDT 24
Finished Mar 28 01:06:17 PM PDT 24
Peak memory 210516 kb
Host smart-28080437-e876-4685-b57b-2c9e27499a12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230335 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2230335
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4263047713
Short name T340
Test name
Test status
Simulation time 459834332 ps
CPU time 1.7 seconds
Started Mar 28 01:04:48 PM PDT 24
Finished Mar 28 01:04:50 PM PDT 24
Peak memory 201584 kb
Host smart-70dd1a80-4d00-4568-8828-6799ff6f9143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263047713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4263047713
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3319298837
Short name T535
Test name
Test status
Simulation time 506663978217 ps
CPU time 519.36 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:13:26 PM PDT 24
Peak memory 201892 kb
Host smart-e661fc15-be00-4435-8e74-ab17e2335955
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319298837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3319298837
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1410643727
Short name T768
Test name
Test status
Simulation time 167006796984 ps
CPU time 66.35 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:05:57 PM PDT 24
Peak memory 201772 kb
Host smart-62edf167-5494-4a93-9445-0f459eed29bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410643727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1410643727
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2009736973
Short name T698
Test name
Test status
Simulation time 499527690579 ps
CPU time 1055.42 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 201856 kb
Host smart-295d5303-4323-41ba-82df-98a33567160a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009736973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2009736973
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3556472712
Short name T640
Test name
Test status
Simulation time 330750934756 ps
CPU time 410.32 seconds
Started Mar 28 01:04:46 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 201892 kb
Host smart-ce1400d7-ccf7-4883-8bc7-b660a19ec18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556472712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3556472712
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3802359121
Short name T565
Test name
Test status
Simulation time 494563530053 ps
CPU time 455.17 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:12:21 PM PDT 24
Peak memory 201780 kb
Host smart-52c9d20c-52b4-4062-9794-5f1f3900fbec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802359121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3802359121
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2363255021
Short name T301
Test name
Test status
Simulation time 639388588084 ps
CPU time 220.58 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:08:28 PM PDT 24
Peak memory 201980 kb
Host smart-f9913b43-7b94-473f-9ab2-ff1a9cc8e392
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363255021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2363255021
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2717968763
Short name T436
Test name
Test status
Simulation time 399268701493 ps
CPU time 233.47 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:08:44 PM PDT 24
Peak memory 201916 kb
Host smart-065021e3-a718-4fdc-8e8f-34be8c35484b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717968763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2717968763
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.762467424
Short name T215
Test name
Test status
Simulation time 109720547783 ps
CPU time 392.47 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:11:16 PM PDT 24
Peak memory 202224 kb
Host smart-a43485b0-d26c-4e07-abe2-d0db3e97af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762467424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.762467424
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1769161978
Short name T691
Test name
Test status
Simulation time 23236169629 ps
CPU time 54.78 seconds
Started Mar 28 01:04:52 PM PDT 24
Finished Mar 28 01:05:47 PM PDT 24
Peak memory 201592 kb
Host smart-6d5090a3-dde3-4b2f-bf08-1f5f16f79a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769161978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1769161978
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1015457883
Short name T662
Test name
Test status
Simulation time 3341093120 ps
CPU time 2.77 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:04:54 PM PDT 24
Peak memory 201588 kb
Host smart-96b3c4ba-1a30-4c96-a7b7-d9c8b599aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015457883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1015457883
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2702984074
Short name T456
Test name
Test status
Simulation time 6073349514 ps
CPU time 2.49 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:04:46 PM PDT 24
Peak memory 201708 kb
Host smart-ac86e303-dd62-4622-a726-dfe9f57fb654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702984074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2702984074
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1033344989
Short name T330
Test name
Test status
Simulation time 326572290187 ps
CPU time 189.37 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:08:00 PM PDT 24
Peak memory 201900 kb
Host smart-3a5d9f3c-9cd4-4ec6-9b59-82ee7998a67d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033344989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1033344989
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1159453336
Short name T208
Test name
Test status
Simulation time 167673448692 ps
CPU time 42.24 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:05:28 PM PDT 24
Peak memory 210156 kb
Host smart-16fc99c6-50c3-443f-beb6-da16dc674560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159453336 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1159453336
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2304791739
Short name T479
Test name
Test status
Simulation time 496155551 ps
CPU time 0.92 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:04:48 PM PDT 24
Peak memory 201584 kb
Host smart-da898d99-90eb-499a-8463-30cf88d516c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304791739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2304791739
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3313915341
Short name T154
Test name
Test status
Simulation time 164892723967 ps
CPU time 363.16 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:10:49 PM PDT 24
Peak memory 201716 kb
Host smart-13857f62-3d2c-485f-a0ff-254e8291fb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313915341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3313915341
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1508564965
Short name T723
Test name
Test status
Simulation time 159936253685 ps
CPU time 372.6 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:10:56 PM PDT 24
Peak memory 201780 kb
Host smart-6132c822-0b76-45e5-9f34-132eb5827453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508564965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1508564965
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.812289986
Short name T644
Test name
Test status
Simulation time 485877073990 ps
CPU time 175.55 seconds
Started Mar 28 01:04:48 PM PDT 24
Finished Mar 28 01:07:44 PM PDT 24
Peak memory 201940 kb
Host smart-e7fd46d2-3abd-456e-8fe9-8c5b8acf0e96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=812289986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.812289986
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2921225059
Short name T648
Test name
Test status
Simulation time 323986942062 ps
CPU time 381.39 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:11:05 PM PDT 24
Peak memory 201980 kb
Host smart-dd7acc23-e0ca-4f2c-8bfe-4aa96dfe4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921225059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2921225059
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1338609014
Short name T634
Test name
Test status
Simulation time 489009300256 ps
CPU time 1159.98 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:24:09 PM PDT 24
Peak memory 201952 kb
Host smart-3ad5fe14-7aa9-4000-8a8b-576fa0106c93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338609014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1338609014
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3847134759
Short name T302
Test name
Test status
Simulation time 532566638226 ps
CPU time 1207.43 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:24:58 PM PDT 24
Peak memory 201964 kb
Host smart-209351f2-12ff-4d40-a1ac-ea7f91e092ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847134759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3847134759
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2232720205
Short name T398
Test name
Test status
Simulation time 585240226848 ps
CPU time 1285.92 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:26:17 PM PDT 24
Peak memory 201880 kb
Host smart-bc10a1cc-c6d2-441e-ab34-eb49cb820464
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232720205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2232720205
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2657998232
Short name T527
Test name
Test status
Simulation time 116259804923 ps
CPU time 471.74 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:12:37 PM PDT 24
Peak memory 202236 kb
Host smart-f4e83bd1-3bfc-4df7-b09d-ffa38476c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657998232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2657998232
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.244845675
Short name T478
Test name
Test status
Simulation time 29020068523 ps
CPU time 17.33 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:05:08 PM PDT 24
Peak memory 201620 kb
Host smart-39015159-a7b4-49e9-8de7-2c9c4e19f521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244845675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.244845675
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3020982937
Short name T415
Test name
Test status
Simulation time 3473315238 ps
CPU time 2.77 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:04:53 PM PDT 24
Peak memory 201700 kb
Host smart-f6908b01-8be2-4913-88bc-45eb96d9bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020982937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3020982937
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2979927825
Short name T757
Test name
Test status
Simulation time 5839110059 ps
CPU time 7.97 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:04:59 PM PDT 24
Peak memory 201576 kb
Host smart-846ae13b-7f65-4651-9f7f-915cf39daf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979927825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2979927825
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1295202470
Short name T329
Test name
Test status
Simulation time 168497529678 ps
CPU time 151.48 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:07:15 PM PDT 24
Peak memory 201844 kb
Host smart-d6a86ca3-5dfc-43ec-8da0-72ea2c867a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295202470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1295202470
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3537776712
Short name T209
Test name
Test status
Simulation time 239834405617 ps
CPU time 388.46 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:11:15 PM PDT 24
Peak memory 218744 kb
Host smart-aade235b-9473-4479-a4cc-9747c41eff63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537776712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3537776712
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1700477561
Short name T449
Test name
Test status
Simulation time 555285252 ps
CPU time 0.88 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:04:46 PM PDT 24
Peak memory 201576 kb
Host smart-502b54c2-2d96-4496-aa5c-eaed4a5a1c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700477561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1700477561
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1722963594
Short name T163
Test name
Test status
Simulation time 415561324839 ps
CPU time 557.27 seconds
Started Mar 28 01:04:46 PM PDT 24
Finished Mar 28 01:14:04 PM PDT 24
Peak memory 201892 kb
Host smart-796eadb3-d913-4cd4-bd90-89c3006ca5f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722963594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1722963594
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.49445045
Short name T188
Test name
Test status
Simulation time 364402486712 ps
CPU time 186.23 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:07:50 PM PDT 24
Peak memory 201864 kb
Host smart-527e7309-64a9-48d0-ac4a-70ff6e7c2890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49445045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.49445045
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3669844953
Short name T505
Test name
Test status
Simulation time 166474740600 ps
CPU time 410.31 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:11:37 PM PDT 24
Peak memory 201892 kb
Host smart-5477b563-e703-4820-be70-25b28158b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669844953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3669844953
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3578568158
Short name T404
Test name
Test status
Simulation time 498151099851 ps
CPU time 75.57 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:06:07 PM PDT 24
Peak memory 201960 kb
Host smart-59d38dee-1045-46f2-9707-97e65ddb65b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578568158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3578568158
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1075746154
Short name T305
Test name
Test status
Simulation time 160151688032 ps
CPU time 360.5 seconds
Started Mar 28 01:04:44 PM PDT 24
Finished Mar 28 01:10:44 PM PDT 24
Peak memory 201964 kb
Host smart-88bc846e-dfad-4256-b35d-71910c4eee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075746154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1075746154
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3473358843
Short name T474
Test name
Test status
Simulation time 326675159087 ps
CPU time 42.99 seconds
Started Mar 28 01:04:42 PM PDT 24
Finished Mar 28 01:05:26 PM PDT 24
Peak memory 201968 kb
Host smart-0192d25a-e9df-40ee-b74f-850601404b31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473358843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3473358843
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3931347743
Short name T650
Test name
Test status
Simulation time 183910769727 ps
CPU time 76.89 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:06:02 PM PDT 24
Peak memory 201980 kb
Host smart-1fb044c8-337b-4592-a7a1-907cfd5b641e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931347743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3931347743
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2126760263
Short name T537
Test name
Test status
Simulation time 631982293269 ps
CPU time 1443.01 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 201820 kb
Host smart-c1a99977-0f5c-4376-b253-453f9fa9e13a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126760263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2126760263
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.4131757011
Short name T697
Test name
Test status
Simulation time 75050821038 ps
CPU time 309.14 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 202156 kb
Host smart-8beb400a-1ae1-46c5-b980-b6da939b9172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131757011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.4131757011
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1319982690
Short name T6
Test name
Test status
Simulation time 38298033030 ps
CPU time 92.08 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:06:24 PM PDT 24
Peak memory 201472 kb
Host smart-99ecedd4-7bf7-4ade-8778-7d64bc137e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319982690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1319982690
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1882102399
Short name T784
Test name
Test status
Simulation time 4105235773 ps
CPU time 11.35 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:05:03 PM PDT 24
Peak memory 201440 kb
Host smart-b6f0fbba-9b0c-415c-83f9-9b874202f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882102399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1882102399
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2969849658
Short name T423
Test name
Test status
Simulation time 5604156221 ps
CPU time 4.42 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:04:52 PM PDT 24
Peak memory 201688 kb
Host smart-4c735946-eb6a-4360-9549-d34f0da1293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969849658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2969849658
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3073225776
Short name T223
Test name
Test status
Simulation time 255880422412 ps
CPU time 545.72 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:13:57 PM PDT 24
Peak memory 211176 kb
Host smart-ea2ea196-2a9a-4a05-8fe1-1f3d545e9fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073225776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3073225776
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.949900879
Short name T22
Test name
Test status
Simulation time 323136372018 ps
CPU time 186.62 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:07:58 PM PDT 24
Peak memory 201796 kb
Host smart-377e1a3d-952f-4162-81c4-a03ea9d717d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949900879 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.949900879
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1897095398
Short name T368
Test name
Test status
Simulation time 469243584 ps
CPU time 1.77 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:04:53 PM PDT 24
Peak memory 201596 kb
Host smart-b9d410f1-06de-4b3c-b05f-4ff0e4a7549b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897095398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1897095398
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3609775718
Short name T65
Test name
Test status
Simulation time 324533472728 ps
CPU time 636.5 seconds
Started Mar 28 01:04:46 PM PDT 24
Finished Mar 28 01:15:23 PM PDT 24
Peak memory 201908 kb
Host smart-d51ac3c7-154d-46a4-a763-53bae6f39713
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609775718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3609775718
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1359707698
Short name T257
Test name
Test status
Simulation time 505443846487 ps
CPU time 293.54 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:09:39 PM PDT 24
Peak memory 201892 kb
Host smart-e2a04eb0-aad1-42ba-8cea-9bbb1444d071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359707698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1359707698
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2243577617
Short name T280
Test name
Test status
Simulation time 494508846815 ps
CPU time 562.3 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:14:08 PM PDT 24
Peak memory 201808 kb
Host smart-28a7916e-9ba4-4a0d-af06-562935b013ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243577617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2243577617
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2139221046
Short name T44
Test name
Test status
Simulation time 488395891761 ps
CPU time 1096.91 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:23:08 PM PDT 24
Peak memory 201860 kb
Host smart-b028c042-ca61-4e3a-8795-fe539d905e76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139221046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2139221046
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1508657145
Short name T549
Test name
Test status
Simulation time 329801919450 ps
CPU time 354.24 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:10:45 PM PDT 24
Peak memory 201652 kb
Host smart-4be537f5-8688-40f8-8626-e86591cba615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508657145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1508657145
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.653778524
Short name T664
Test name
Test status
Simulation time 321376276804 ps
CPU time 723.45 seconds
Started Mar 28 01:04:43 PM PDT 24
Finished Mar 28 01:16:47 PM PDT 24
Peak memory 201852 kb
Host smart-3df6686b-93e1-4f35-9877-61428559d93d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653778524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.653778524
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2159785094
Short name T156
Test name
Test status
Simulation time 186471784128 ps
CPU time 381.39 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:11:13 PM PDT 24
Peak memory 201924 kb
Host smart-1b9b3c57-b88d-47db-8300-56fa0cd36299
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159785094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2159785094
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3830901007
Short name T383
Test name
Test status
Simulation time 388309178808 ps
CPU time 801.46 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:18:12 PM PDT 24
Peak memory 201656 kb
Host smart-c6044e5d-ce02-4b38-a876-70b01cfba5d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830901007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3830901007
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.225443223
Short name T469
Test name
Test status
Simulation time 130297379074 ps
CPU time 440.45 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:12:12 PM PDT 24
Peak memory 202248 kb
Host smart-d2a3b16d-cd08-474c-8e2a-9fcbe7fd9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225443223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.225443223
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2004253898
Short name T351
Test name
Test status
Simulation time 34204564482 ps
CPU time 7.05 seconds
Started Mar 28 01:04:46 PM PDT 24
Finished Mar 28 01:04:53 PM PDT 24
Peak memory 201712 kb
Host smart-b2a07dfd-7e7d-4146-a127-14ca255babf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004253898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2004253898
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1544638859
Short name T605
Test name
Test status
Simulation time 4142715169 ps
CPU time 5.75 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:05:03 PM PDT 24
Peak memory 201644 kb
Host smart-50704b98-4489-490c-b598-7981862904fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544638859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1544638859
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4245759383
Short name T504
Test name
Test status
Simulation time 5854136941 ps
CPU time 15.21 seconds
Started Mar 28 01:04:45 PM PDT 24
Finished Mar 28 01:05:01 PM PDT 24
Peak memory 201716 kb
Host smart-2cdc34c5-cbed-4377-89be-a5d504cf705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245759383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4245759383
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.458301623
Short name T108
Test name
Test status
Simulation time 235400584554 ps
CPU time 501.62 seconds
Started Mar 28 01:04:49 PM PDT 24
Finished Mar 28 01:13:12 PM PDT 24
Peak memory 201828 kb
Host smart-9d011c79-bd68-41b1-b5f4-ff92e3fc5aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458301623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
458301623
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2749596268
Short name T272
Test name
Test status
Simulation time 127972488905 ps
CPU time 146.9 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:07:18 PM PDT 24
Peak memory 210460 kb
Host smart-3459dc03-89de-427f-93c7-717eb92da677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749596268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2749596268
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2806008069
Short name T541
Test name
Test status
Simulation time 438438417 ps
CPU time 1.62 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:05:03 PM PDT 24
Peak memory 201512 kb
Host smart-fc89876b-856a-4f96-8645-ba8482d8372c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806008069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2806008069
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2318926766
Short name T604
Test name
Test status
Simulation time 166209239079 ps
CPU time 61.67 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:05:59 PM PDT 24
Peak memory 201856 kb
Host smart-d7d5bb26-7f1d-45b8-8c0e-f53b49928e66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318926766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2318926766
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2327430298
Short name T694
Test name
Test status
Simulation time 339337523361 ps
CPU time 408.38 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 201860 kb
Host smart-d5c03928-a374-4eb3-85e2-81da2e7cc849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327430298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2327430298
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4036456114
Short name T319
Test name
Test status
Simulation time 493998671251 ps
CPU time 295.65 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:09:53 PM PDT 24
Peak memory 201944 kb
Host smart-c96e84d0-bd4e-4614-aba9-7ea1eddc2a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036456114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4036456114
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3521167910
Short name T652
Test name
Test status
Simulation time 485646237598 ps
CPU time 229.59 seconds
Started Mar 28 01:04:56 PM PDT 24
Finished Mar 28 01:08:46 PM PDT 24
Peak memory 201836 kb
Host smart-d8bed605-f90c-46c7-92f4-cef879080bd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521167910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3521167910
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2045923494
Short name T178
Test name
Test status
Simulation time 325356295093 ps
CPU time 187.88 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:08:06 PM PDT 24
Peak memory 201928 kb
Host smart-14a7e6ba-a408-471c-a9f1-87e019ad8d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045923494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2045923494
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2812509617
Short name T490
Test name
Test status
Simulation time 482802067759 ps
CPU time 1187.97 seconds
Started Mar 28 01:04:47 PM PDT 24
Finished Mar 28 01:24:35 PM PDT 24
Peak memory 201872 kb
Host smart-c97717ad-9344-4599-903c-07f3ba17a99b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812509617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2812509617
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2531161954
Short name T176
Test name
Test status
Simulation time 384904955562 ps
CPU time 212.72 seconds
Started Mar 28 01:04:51 PM PDT 24
Finished Mar 28 01:08:24 PM PDT 24
Peak memory 201896 kb
Host smart-d6c7dfbe-e1a9-47f3-85fc-92c62ca64f4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531161954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2531161954
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2110687466
Short name T577
Test name
Test status
Simulation time 199995667910 ps
CPU time 92.23 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:06:30 PM PDT 24
Peak memory 201824 kb
Host smart-f8537352-2008-4db9-ae1f-eced06e21d6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110687466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2110687466
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3909954219
Short name T433
Test name
Test status
Simulation time 125352351249 ps
CPU time 499.66 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:13:18 PM PDT 24
Peak memory 202188 kb
Host smart-ae0f759d-23a9-4284-85e2-d66f4f7c5348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909954219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3909954219
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1757845989
Short name T589
Test name
Test status
Simulation time 39705112838 ps
CPU time 25.09 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:05:23 PM PDT 24
Peak memory 201684 kb
Host smart-c58ac435-b8be-49bb-b6e8-93a32e7b2304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757845989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1757845989
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1179099758
Short name T43
Test name
Test status
Simulation time 3014264312 ps
CPU time 6.82 seconds
Started Mar 28 01:04:48 PM PDT 24
Finished Mar 28 01:04:54 PM PDT 24
Peak memory 201692 kb
Host smart-72360480-3179-4c1b-9795-17997400d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179099758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1179099758
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2464409350
Short name T665
Test name
Test status
Simulation time 5960977495 ps
CPU time 4.13 seconds
Started Mar 28 01:04:50 PM PDT 24
Finished Mar 28 01:04:55 PM PDT 24
Peak memory 201640 kb
Host smart-7e701d00-5dc0-4d03-a015-a50259fc8899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464409350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2464409350
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.468461049
Short name T475
Test name
Test status
Simulation time 480562797339 ps
CPU time 1400.92 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 212772 kb
Host smart-a7cd5e21-e09d-41f6-98bc-1c4c487d8d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468461049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
468461049
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2935918461
Short name T23
Test name
Test status
Simulation time 29857291807 ps
CPU time 65.78 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:06:04 PM PDT 24
Peak memory 202096 kb
Host smart-0aa36d4e-0555-47fc-b2ab-030e1c63343e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935918461 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2935918461
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.958844671
Short name T440
Test name
Test status
Simulation time 480460394 ps
CPU time 1.86 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:04:59 PM PDT 24
Peak memory 201584 kb
Host smart-6ba380a2-e8b4-43fa-be62-07b49ff32b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958844671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.958844671
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1906620945
Short name T290
Test name
Test status
Simulation time 335235453012 ps
CPU time 387.79 seconds
Started Mar 28 01:05:06 PM PDT 24
Finished Mar 28 01:11:35 PM PDT 24
Peak memory 201956 kb
Host smart-a897c8a2-cc55-4acb-a45c-43c7367eafdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906620945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1906620945
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3579586775
Short name T600
Test name
Test status
Simulation time 206905498832 ps
CPU time 122.78 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:07:01 PM PDT 24
Peak memory 201796 kb
Host smart-ccddaf92-0995-4345-9b69-89e2b319f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579586775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3579586775
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.748576016
Short name T523
Test name
Test status
Simulation time 162708296275 ps
CPU time 38.85 seconds
Started Mar 28 01:05:13 PM PDT 24
Finished Mar 28 01:05:52 PM PDT 24
Peak memory 201912 kb
Host smart-ec21e8c7-08ea-439a-9256-bf0fd06c1d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748576016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.748576016
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2809614714
Short name T439
Test name
Test status
Simulation time 325271557903 ps
CPU time 783.2 seconds
Started Mar 28 01:05:00 PM PDT 24
Finished Mar 28 01:18:04 PM PDT 24
Peak memory 201768 kb
Host smart-8c688c77-1c10-45e2-8fbb-3a29bc8ee102
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809614714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2809614714
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1864786520
Short name T93
Test name
Test status
Simulation time 492248385106 ps
CPU time 1071.47 seconds
Started Mar 28 01:05:01 PM PDT 24
Finished Mar 28 01:22:53 PM PDT 24
Peak memory 201948 kb
Host smart-6789b0b7-4dc5-496a-80ed-35810d20e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864786520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1864786520
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.832153036
Short name T554
Test name
Test status
Simulation time 162356381233 ps
CPU time 381.35 seconds
Started Mar 28 01:05:03 PM PDT 24
Finished Mar 28 01:11:27 PM PDT 24
Peak memory 201864 kb
Host smart-678c9f91-efd4-4067-b6d6-3ef8224a4208
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=832153036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.832153036
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1559741827
Short name T192
Test name
Test status
Simulation time 358563692949 ps
CPU time 845.48 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:19:02 PM PDT 24
Peak memory 201920 kb
Host smart-43c032d6-4bf6-46f9-883c-009d63244a93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559741827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1559741827
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.597537655
Short name T795
Test name
Test status
Simulation time 194422478903 ps
CPU time 115.87 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:06:57 PM PDT 24
Peak memory 201888 kb
Host smart-ac6f7b34-9bbc-42c4-89a5-17ceb081c664
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597537655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.597537655
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2008370303
Short name T649
Test name
Test status
Simulation time 31280919118 ps
CPU time 72.34 seconds
Started Mar 28 01:05:12 PM PDT 24
Finished Mar 28 01:06:25 PM PDT 24
Peak memory 201760 kb
Host smart-39a90b3e-46dc-43ec-8973-b43d5eb0cc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008370303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2008370303
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1910211004
Short name T674
Test name
Test status
Simulation time 4586530408 ps
CPU time 11.49 seconds
Started Mar 28 01:05:12 PM PDT 24
Finished Mar 28 01:05:24 PM PDT 24
Peak memory 201764 kb
Host smart-f731d6b1-e6ca-4261-83e7-9cb8672b4624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910211004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1910211004
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3714483222
Short name T372
Test name
Test status
Simulation time 5722278290 ps
CPU time 4.05 seconds
Started Mar 28 01:05:01 PM PDT 24
Finished Mar 28 01:05:05 PM PDT 24
Peak memory 201716 kb
Host smart-97aad38e-e02b-42a2-ac86-ce776282d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714483222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3714483222
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.191895633
Short name T588
Test name
Test status
Simulation time 670715928473 ps
CPU time 395.74 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:11:34 PM PDT 24
Peak memory 201900 kb
Host smart-b1a086d1-ad5c-4ddf-a322-168344ff4fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191895633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
191895633
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2378780453
Short name T20
Test name
Test status
Simulation time 384552002054 ps
CPU time 227.32 seconds
Started Mar 28 01:05:06 PM PDT 24
Finished Mar 28 01:08:54 PM PDT 24
Peak memory 210592 kb
Host smart-c66f463f-57cd-46ac-b472-49e61787be0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378780453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2378780453
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4139796989
Short name T14
Test name
Test status
Simulation time 392009559 ps
CPU time 1.62 seconds
Started Mar 28 01:05:12 PM PDT 24
Finished Mar 28 01:05:13 PM PDT 24
Peak memory 201640 kb
Host smart-278bbf7a-5436-4145-b848-7dd6c9aaeb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139796989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4139796989
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2319117298
Short name T715
Test name
Test status
Simulation time 172493206386 ps
CPU time 378.2 seconds
Started Mar 28 01:04:56 PM PDT 24
Finished Mar 28 01:11:15 PM PDT 24
Peak memory 201880 kb
Host smart-e0e9a92b-0a82-4885-b117-86a461c54df4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319117298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2319117298
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2005966641
Short name T137
Test name
Test status
Simulation time 355498890530 ps
CPU time 208.94 seconds
Started Mar 28 01:05:02 PM PDT 24
Finished Mar 28 01:08:31 PM PDT 24
Peak memory 201892 kb
Host smart-476878cc-03e2-408e-bd0f-a6bbc51a802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005966641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2005966641
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.845882439
Short name T31
Test name
Test status
Simulation time 165674273839 ps
CPU time 101.73 seconds
Started Mar 28 01:05:01 PM PDT 24
Finished Mar 28 01:06:43 PM PDT 24
Peak memory 201976 kb
Host smart-64c94896-9066-415f-9f32-88db14e24834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845882439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.845882439
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1778570995
Short name T353
Test name
Test status
Simulation time 160560229017 ps
CPU time 181.54 seconds
Started Mar 28 01:05:13 PM PDT 24
Finished Mar 28 01:08:14 PM PDT 24
Peak memory 201920 kb
Host smart-b2824987-3d6c-4d32-a34a-e4c7585fa456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778570995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1778570995
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.335789995
Short name T759
Test name
Test status
Simulation time 492868276412 ps
CPU time 258.9 seconds
Started Mar 28 01:04:58 PM PDT 24
Finished Mar 28 01:09:18 PM PDT 24
Peak memory 201904 kb
Host smart-fdfc7c6d-8ad1-4e8e-bbf1-fb4e07067817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335789995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.335789995
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2936413890
Short name T781
Test name
Test status
Simulation time 165641735983 ps
CPU time 96.35 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:06:37 PM PDT 24
Peak memory 201860 kb
Host smart-67e04d93-791a-4c67-b940-efd25c8cda04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936413890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2936413890
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1793389716
Short name T699
Test name
Test status
Simulation time 567211666233 ps
CPU time 1461.42 seconds
Started Mar 28 01:05:05 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 201924 kb
Host smart-aecc249c-220c-4ec4-9784-5aa6e0e4ed5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793389716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1793389716
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.896557402
Short name T533
Test name
Test status
Simulation time 600078340220 ps
CPU time 627.97 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:15:29 PM PDT 24
Peak memory 201892 kb
Host smart-642fa439-48a4-416b-85fe-ffe709facc4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896557402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.896557402
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1478106211
Short name T737
Test name
Test status
Simulation time 91507072218 ps
CPU time 445.22 seconds
Started Mar 28 01:05:03 PM PDT 24
Finished Mar 28 01:12:31 PM PDT 24
Peak memory 202140 kb
Host smart-27f96a86-2f7d-4702-ae7f-a9a6e571b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478106211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1478106211
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3520910400
Short name T459
Test name
Test status
Simulation time 35276380456 ps
CPU time 20.92 seconds
Started Mar 28 01:05:05 PM PDT 24
Finished Mar 28 01:05:26 PM PDT 24
Peak memory 201696 kb
Host smart-30ce33fc-07e1-41b1-a64e-29d56951f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520910400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3520910400
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3652694381
Short name T666
Test name
Test status
Simulation time 5055129934 ps
CPU time 6.23 seconds
Started Mar 28 01:05:06 PM PDT 24
Finished Mar 28 01:05:13 PM PDT 24
Peak memory 201644 kb
Host smart-6f1ac747-290e-42b8-bbfc-781ca309e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652694381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3652694381
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.4232672869
Short name T461
Test name
Test status
Simulation time 5795991422 ps
CPU time 12.57 seconds
Started Mar 28 01:05:01 PM PDT 24
Finished Mar 28 01:05:14 PM PDT 24
Peak memory 201684 kb
Host smart-75f6ed31-76bf-4b3f-be07-dfde3c80f3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232672869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.4232672869
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4034412360
Short name T631
Test name
Test status
Simulation time 176589437251 ps
CPU time 36.19 seconds
Started Mar 28 01:05:05 PM PDT 24
Finished Mar 28 01:05:42 PM PDT 24
Peak memory 201964 kb
Host smart-70583c34-6478-4b06-8af3-366832bafeab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034412360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4034412360
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3196302316
Short name T342
Test name
Test status
Simulation time 485415838 ps
CPU time 1.65 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:05:20 PM PDT 24
Peak memory 201592 kb
Host smart-c533b47f-458b-48ec-a9e2-6a1a5c29fc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196302316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3196302316
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1001145326
Short name T326
Test name
Test status
Simulation time 363800256591 ps
CPU time 145.74 seconds
Started Mar 28 01:05:02 PM PDT 24
Finished Mar 28 01:07:28 PM PDT 24
Peak memory 201956 kb
Host smart-327db69e-80ad-4f63-9aa6-e91160261bb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001145326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1001145326
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1894195709
Short name T508
Test name
Test status
Simulation time 535049758702 ps
CPU time 315.38 seconds
Started Mar 28 01:05:16 PM PDT 24
Finished Mar 28 01:10:31 PM PDT 24
Peak memory 201900 kb
Host smart-51a611bb-eeec-4d1d-8fcc-fa7d2b6ea6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894195709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1894195709
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3860546055
Short name T615
Test name
Test status
Simulation time 160172864641 ps
CPU time 352.42 seconds
Started Mar 28 01:04:59 PM PDT 24
Finished Mar 28 01:10:51 PM PDT 24
Peak memory 201884 kb
Host smart-6d38c853-42f5-4c06-99b5-01b44de33a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860546055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3860546055
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1382200210
Short name T624
Test name
Test status
Simulation time 502183913571 ps
CPU time 1124.63 seconds
Started Mar 28 01:05:13 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 201948 kb
Host smart-af7a6c9f-955b-4acb-b146-b8a342580a23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382200210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1382200210
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.72169054
Short name T608
Test name
Test status
Simulation time 492361647890 ps
CPU time 1161.68 seconds
Started Mar 28 01:05:13 PM PDT 24
Finished Mar 28 01:24:35 PM PDT 24
Peak memory 201932 kb
Host smart-16d1884f-6b4c-40c9-b138-11d41dbb79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72169054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.72169054
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3652655899
Short name T441
Test name
Test status
Simulation time 493157019399 ps
CPU time 490.4 seconds
Started Mar 28 01:05:05 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 201888 kb
Host smart-c3d9500b-beb5-4362-9641-c1cdc4081842
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652655899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3652655899
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2716594549
Short name T275
Test name
Test status
Simulation time 591866876963 ps
CPU time 1501.12 seconds
Started Mar 28 01:04:57 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 201956 kb
Host smart-be4cd690-6f6d-46d5-945a-5d6e57e75eac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716594549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2716594549
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4290845106
Short name T534
Test name
Test status
Simulation time 393092780909 ps
CPU time 422.03 seconds
Started Mar 28 01:05:12 PM PDT 24
Finished Mar 28 01:12:14 PM PDT 24
Peak memory 201920 kb
Host smart-6e834aa2-d668-4194-834a-de163a4e75f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290845106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4290845106
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3330972043
Short name T222
Test name
Test status
Simulation time 109598027824 ps
CPU time 393.36 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 201948 kb
Host smart-62d43a31-63bd-454b-bbb5-6901d3271348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330972043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3330972043
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3897440635
Short name T400
Test name
Test status
Simulation time 35562633456 ps
CPU time 20.83 seconds
Started Mar 28 01:05:19 PM PDT 24
Finished Mar 28 01:05:40 PM PDT 24
Peak memory 201620 kb
Host smart-810426df-d3a6-4888-92a5-317765e5ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897440635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3897440635
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.358522717
Short name T104
Test name
Test status
Simulation time 4894177095 ps
CPU time 3.51 seconds
Started Mar 28 01:05:15 PM PDT 24
Finished Mar 28 01:05:19 PM PDT 24
Peak memory 201688 kb
Host smart-45d8d32a-7034-437c-8560-aa5758d58162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358522717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.358522717
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.561507893
Short name T582
Test name
Test status
Simulation time 6095826307 ps
CPU time 4.15 seconds
Started Mar 28 01:05:12 PM PDT 24
Finished Mar 28 01:05:16 PM PDT 24
Peak memory 201760 kb
Host smart-85651423-b941-4fb8-a689-cca71950f51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561507893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.561507893
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.479381466
Short name T333
Test name
Test status
Simulation time 167973427070 ps
CPU time 36.16 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:05:54 PM PDT 24
Peak memory 210276 kb
Host smart-986ad7de-bbaa-4fd3-b9c1-3dbbce3d8f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479381466 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.479381466
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1653993627
Short name T708
Test name
Test status
Simulation time 303091312 ps
CPU time 0.73 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:05:18 PM PDT 24
Peak memory 201580 kb
Host smart-2174bb35-aef3-4170-b319-6f45378b678a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653993627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1653993627
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2443570471
Short name T152
Test name
Test status
Simulation time 167100363642 ps
CPU time 385.17 seconds
Started Mar 28 01:05:23 PM PDT 24
Finished Mar 28 01:11:48 PM PDT 24
Peak memory 201940 kb
Host smart-fb5a7a6e-a619-4b4c-a525-933673a4d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443570471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2443570471
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.453912887
Short name T745
Test name
Test status
Simulation time 165919074401 ps
CPU time 207.62 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:08:46 PM PDT 24
Peak memory 201852 kb
Host smart-c6b62b4d-a8ea-4052-af1e-e6a15026418b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=453912887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.453912887
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1189849726
Short name T580
Test name
Test status
Simulation time 491947162679 ps
CPU time 269.27 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:09:47 PM PDT 24
Peak memory 201776 kb
Host smart-a79b90ff-cc59-4ba3-a136-60a418b38582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189849726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1189849726
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2519656152
Short name T563
Test name
Test status
Simulation time 490141293998 ps
CPU time 1270.08 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 201828 kb
Host smart-f72d2200-d5cc-4e2e-b116-506c972d7a9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519656152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2519656152
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1296104646
Short name T679
Test name
Test status
Simulation time 170340107494 ps
CPU time 268.79 seconds
Started Mar 28 01:05:20 PM PDT 24
Finished Mar 28 01:09:50 PM PDT 24
Peak memory 201772 kb
Host smart-c9cf2171-f36c-48a1-a86d-7b14aafafe85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296104646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1296104646
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3917926352
Short name T169
Test name
Test status
Simulation time 613407554832 ps
CPU time 347.75 seconds
Started Mar 28 01:05:20 PM PDT 24
Finished Mar 28 01:11:09 PM PDT 24
Peak memory 201804 kb
Host smart-0a190b72-4e94-4332-b199-461b55dbecb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917926352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3917926352
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.674465735
Short name T519
Test name
Test status
Simulation time 139662223109 ps
CPU time 689.41 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:16:47 PM PDT 24
Peak memory 202136 kb
Host smart-ecc356be-733e-4d5f-a1ea-e35ece69ec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674465735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.674465735
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1312778462
Short name T354
Test name
Test status
Simulation time 28713437664 ps
CPU time 13.31 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:05:30 PM PDT 24
Peak memory 201672 kb
Host smart-54159a6d-6bc5-4eb2-8eaf-c472ceeeae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312778462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1312778462
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2457217706
Short name T785
Test name
Test status
Simulation time 3710501902 ps
CPU time 8.88 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:05:27 PM PDT 24
Peak memory 201700 kb
Host smart-72c7a680-5130-4943-ace3-4dde1d1215d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457217706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2457217706
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3294125866
Short name T386
Test name
Test status
Simulation time 6078047619 ps
CPU time 4.95 seconds
Started Mar 28 01:05:20 PM PDT 24
Finished Mar 28 01:05:26 PM PDT 24
Peak memory 201608 kb
Host smart-0206a451-cf6b-4cf3-b70e-b0da58949967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294125866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3294125866
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3207665620
Short name T224
Test name
Test status
Simulation time 322709298756 ps
CPU time 828.51 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:19:06 PM PDT 24
Peak memory 210484 kb
Host smart-55d66436-34e4-4693-b987-94a72144c795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207665620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3207665620
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2550430940
Short name T17
Test name
Test status
Simulation time 55546841898 ps
CPU time 23.41 seconds
Started Mar 28 01:05:21 PM PDT 24
Finished Mar 28 01:05:45 PM PDT 24
Peak memory 217008 kb
Host smart-8375745f-9519-40fd-bafc-ec192c8c5b41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550430940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2550430940
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.566889272
Short name T515
Test name
Test status
Simulation time 391402706 ps
CPU time 1.57 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:05:46 PM PDT 24
Peak memory 201564 kb
Host smart-b228dbf9-3d7b-42b0-afa8-580c2aacc880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566889272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.566889272
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2299728331
Short name T320
Test name
Test status
Simulation time 565943350737 ps
CPU time 317.34 seconds
Started Mar 28 01:05:25 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 201872 kb
Host smart-42d46a69-8d1e-433e-ad35-860ee7bebff4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299728331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2299728331
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3811329227
Short name T266
Test name
Test status
Simulation time 172658766668 ps
CPU time 102.22 seconds
Started Mar 28 01:05:19 PM PDT 24
Finished Mar 28 01:07:01 PM PDT 24
Peak memory 201916 kb
Host smart-9061250e-93a0-4f92-9987-3339b2f46628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811329227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3811329227
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2542754282
Short name T536
Test name
Test status
Simulation time 169815772071 ps
CPU time 415.77 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:12:14 PM PDT 24
Peak memory 201872 kb
Host smart-cffa6a29-94c2-43c0-a09f-97fd7454442d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542754282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2542754282
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1827149448
Short name T265
Test name
Test status
Simulation time 325756598723 ps
CPU time 385.09 seconds
Started Mar 28 01:05:21 PM PDT 24
Finished Mar 28 01:11:46 PM PDT 24
Peak memory 201952 kb
Host smart-81a67ed9-fd58-44f2-83ce-345b3cd40954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827149448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1827149448
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1275712379
Short name T542
Test name
Test status
Simulation time 162410536919 ps
CPU time 50.89 seconds
Started Mar 28 01:05:18 PM PDT 24
Finished Mar 28 01:06:09 PM PDT 24
Peak memory 201760 kb
Host smart-32391936-4751-4580-ba69-67f9ac1926e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275712379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1275712379
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4201421913
Short name T51
Test name
Test status
Simulation time 454530897541 ps
CPU time 986.8 seconds
Started Mar 28 01:05:24 PM PDT 24
Finished Mar 28 01:21:51 PM PDT 24
Peak memory 201956 kb
Host smart-0f66b51f-f816-44de-a5b3-c71228a636a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201421913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4201421913
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3704529029
Short name T38
Test name
Test status
Simulation time 388307032606 ps
CPU time 938.3 seconds
Started Mar 28 01:05:25 PM PDT 24
Finished Mar 28 01:21:04 PM PDT 24
Peak memory 201868 kb
Host smart-0c66d31d-b6b3-4d31-9867-7dc321c006db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704529029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3704529029
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1262327332
Short name T791
Test name
Test status
Simulation time 101475111537 ps
CPU time 564.95 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:14:43 PM PDT 24
Peak memory 202224 kb
Host smart-f0c18330-fb30-47f1-be55-2b9c32d53476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262327332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1262327332
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.689974709
Short name T146
Test name
Test status
Simulation time 42789652496 ps
CPU time 98.79 seconds
Started Mar 28 01:05:17 PM PDT 24
Finished Mar 28 01:06:56 PM PDT 24
Peak memory 201680 kb
Host smart-c158a3f8-9d8b-4b62-9e19-5c789dfb734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689974709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.689974709
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.109988260
Short name T489
Test name
Test status
Simulation time 2859884267 ps
CPU time 2.41 seconds
Started Mar 28 01:05:20 PM PDT 24
Finished Mar 28 01:05:23 PM PDT 24
Peak memory 201644 kb
Host smart-53e1deed-12b8-42c7-a9ab-5cefd6798137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109988260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.109988260
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2385158035
Short name T690
Test name
Test status
Simulation time 5927205026 ps
CPU time 15.9 seconds
Started Mar 28 01:05:21 PM PDT 24
Finished Mar 28 01:05:37 PM PDT 24
Peak memory 201692 kb
Host smart-4ecdacda-4ed7-4aaf-97ba-1ec02c75f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385158035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2385158035
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.379348283
Short name T685
Test name
Test status
Simulation time 205940729652 ps
CPU time 81.23 seconds
Started Mar 28 01:05:24 PM PDT 24
Finished Mar 28 01:06:46 PM PDT 24
Peak memory 201956 kb
Host smart-5a268eb6-d182-4253-b6d5-dbef068ed8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379348283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
379348283
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1453818688
Short name T413
Test name
Test status
Simulation time 322087746 ps
CPU time 1.03 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:03:44 PM PDT 24
Peak memory 201548 kb
Host smart-c5a41d65-e661-4d05-9558-15706b50ca78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453818688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1453818688
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3963603420
Short name T733
Test name
Test status
Simulation time 161194354865 ps
CPU time 84.94 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:05:08 PM PDT 24
Peak memory 201840 kb
Host smart-6857f614-0099-4923-a456-f57319166f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963603420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3963603420
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.685636488
Short name T334
Test name
Test status
Simulation time 490917119407 ps
CPU time 296.79 seconds
Started Mar 28 01:03:27 PM PDT 24
Finished Mar 28 01:08:24 PM PDT 24
Peak memory 201960 kb
Host smart-44f60489-4ae5-4895-b87b-7565fcc79211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685636488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.685636488
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3908605223
Short name T678
Test name
Test status
Simulation time 488218541894 ps
CPU time 1045.73 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:20:52 PM PDT 24
Peak memory 201924 kb
Host smart-e9b3bb9e-a8df-48eb-a102-e08d0bec60b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908605223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3908605223
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1791135399
Short name T392
Test name
Test status
Simulation time 481866716792 ps
CPU time 1200.15 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:23:26 PM PDT 24
Peak memory 201948 kb
Host smart-9f09ce75-7963-4776-8173-881fd31fa159
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791135399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1791135399
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3517305726
Short name T564
Test name
Test status
Simulation time 185841267882 ps
CPU time 302.54 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:08:47 PM PDT 24
Peak memory 201820 kb
Host smart-a7d27a5d-6b15-4a30-8ab1-e8fcb4ea7198
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517305726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3517305726
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2157274493
Short name T736
Test name
Test status
Simulation time 382495679440 ps
CPU time 253.66 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:07:57 PM PDT 24
Peak memory 201880 kb
Host smart-527f4094-1114-4687-b341-432eba15b269
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157274493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2157274493
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2045387428
Short name T719
Test name
Test status
Simulation time 33515630936 ps
CPU time 4.99 seconds
Started Mar 28 01:03:46 PM PDT 24
Finished Mar 28 01:03:51 PM PDT 24
Peak memory 201688 kb
Host smart-2fef91b4-5156-4253-94a3-f27e9fb6b9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045387428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2045387428
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3200378635
Short name T705
Test name
Test status
Simulation time 3782769762 ps
CPU time 2.95 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:03:47 PM PDT 24
Peak memory 201708 kb
Host smart-286b825f-adb9-4e7b-86c6-b0056a47648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200378635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3200378635
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1905073361
Short name T73
Test name
Test status
Simulation time 8278043770 ps
CPU time 3.48 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:03:46 PM PDT 24
Peak memory 218484 kb
Host smart-23fa8a06-7be6-4e46-8959-0162445304ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905073361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1905073361
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3540691467
Short name T586
Test name
Test status
Simulation time 6065270408 ps
CPU time 13.95 seconds
Started Mar 28 01:03:25 PM PDT 24
Finished Mar 28 01:03:40 PM PDT 24
Peak memory 201700 kb
Host smart-d96bbcd1-022b-42e2-ad8e-08a7c5ca03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540691467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3540691467
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1694671381
Short name T172
Test name
Test status
Simulation time 342129823428 ps
CPU time 377.55 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:10:01 PM PDT 24
Peak memory 201844 kb
Host smart-95347687-fac9-449c-8f56-003713e1dcc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694671381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1694671381
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3366642887
Short name T100
Test name
Test status
Simulation time 5754811917 ps
CPU time 8.05 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:03:52 PM PDT 24
Peak memory 202080 kb
Host smart-38254de3-5bc8-45f4-a0b6-6280bdc80b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366642887 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3366642887
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2319546193
Short name T197
Test name
Test status
Simulation time 299581707 ps
CPU time 1.01 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:05:43 PM PDT 24
Peak memory 201544 kb
Host smart-8d24d0b6-b57b-451a-ae52-4b7594019d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319546193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2319546193
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3582157188
Short name T244
Test name
Test status
Simulation time 162917917858 ps
CPU time 117.51 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:07:38 PM PDT 24
Peak memory 201888 kb
Host smart-38d84b26-67fe-469e-8c3c-b7cf51d097ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582157188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3582157188
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3936497955
Short name T630
Test name
Test status
Simulation time 164176520199 ps
CPU time 101.74 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:07:24 PM PDT 24
Peak memory 201896 kb
Host smart-0f05cec0-62c5-4e58-811d-807537138dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936497955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3936497955
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2924235418
Short name T610
Test name
Test status
Simulation time 489900719499 ps
CPU time 317.3 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:11:01 PM PDT 24
Peak memory 201868 kb
Host smart-0724a7b9-fdad-4fb6-991f-fb462e50045c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924235418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2924235418
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.4251304015
Short name T498
Test name
Test status
Simulation time 158485874040 ps
CPU time 346.36 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:11:30 PM PDT 24
Peak memory 201944 kb
Host smart-663cf44a-83e6-4747-b2d3-3533dba9f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251304015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4251304015
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.124986975
Short name T621
Test name
Test status
Simulation time 325454146087 ps
CPU time 780.39 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:18:41 PM PDT 24
Peak memory 201968 kb
Host smart-011eb58d-670e-46c5-906f-13502517e8db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=124986975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.124986975
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.224040295
Short name T25
Test name
Test status
Simulation time 569830530561 ps
CPU time 86.47 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:07:08 PM PDT 24
Peak memory 201820 kb
Host smart-1e475cfb-e7f3-4628-86a8-c204dd2ed3dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224040295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.224040295
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.833454473
Short name T625
Test name
Test status
Simulation time 193192335321 ps
CPU time 399.87 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:12:22 PM PDT 24
Peak memory 201868 kb
Host smart-4d5f320a-42ba-447d-bdc0-9906fe1c9eb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833454473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.833454473
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2137504486
Short name T393
Test name
Test status
Simulation time 39332966257 ps
CPU time 23.85 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:06:04 PM PDT 24
Peak memory 201672 kb
Host smart-e558dd20-e0a3-45a3-9dce-0c9cd4f9baa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137504486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2137504486
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1413799804
Short name T356
Test name
Test status
Simulation time 3022196229 ps
CPU time 8.19 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:05:52 PM PDT 24
Peak memory 201700 kb
Host smart-f78f01af-b720-483d-9598-244351fb79d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413799804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1413799804
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2036589642
Short name T344
Test name
Test status
Simulation time 5689365843 ps
CPU time 4.13 seconds
Started Mar 28 01:05:43 PM PDT 24
Finished Mar 28 01:05:47 PM PDT 24
Peak memory 201688 kb
Host smart-20ac01e9-91ca-4326-827c-b1b8ded08479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036589642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2036589642
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1309979967
Short name T788
Test name
Test status
Simulation time 458734491497 ps
CPU time 1407.25 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:29:07 PM PDT 24
Peak memory 202184 kb
Host smart-f4a03d8d-ae81-4b5a-965f-6d2cfe3dca8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309979967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1309979967
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.582006079
Short name T298
Test name
Test status
Simulation time 72433824281 ps
CPU time 59.75 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:06:44 PM PDT 24
Peak memory 211228 kb
Host smart-f84adf6f-ca1f-40a7-8767-c84b399e68bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582006079 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.582006079
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1224867740
Short name T41
Test name
Test status
Simulation time 314021321 ps
CPU time 0.82 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:05:41 PM PDT 24
Peak memory 201608 kb
Host smart-21a4faec-5703-44b7-a0c5-a6e7d9950a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224867740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1224867740
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.892099544
Short name T229
Test name
Test status
Simulation time 175830199121 ps
CPU time 263.54 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:10:06 PM PDT 24
Peak memory 201772 kb
Host smart-c8de1137-7d7a-4ab0-ad6c-37c60c22211e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892099544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.892099544
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.429199318
Short name T135
Test name
Test status
Simulation time 164168355255 ps
CPU time 384.6 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:12:05 PM PDT 24
Peak memory 201888 kb
Host smart-afa9f840-3259-4785-a8f4-bac611d5400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429199318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.429199318
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1990941951
Short name T277
Test name
Test status
Simulation time 327232955108 ps
CPU time 716.74 seconds
Started Mar 28 01:05:39 PM PDT 24
Finished Mar 28 01:17:36 PM PDT 24
Peak memory 201848 kb
Host smart-b5838eb5-33b1-44cd-ac78-c1295d767c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990941951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1990941951
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1007187987
Short name T39
Test name
Test status
Simulation time 160846211770 ps
CPU time 372.83 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:11:54 PM PDT 24
Peak memory 201932 kb
Host smart-d7e26909-7ef1-431e-bc2f-4d485755efc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007187987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1007187987
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3684895936
Short name T727
Test name
Test status
Simulation time 318284211355 ps
CPU time 136.16 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:07:57 PM PDT 24
Peak memory 201820 kb
Host smart-fdcca96c-8586-4f0e-a7fd-18c945e1025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684895936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3684895936
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2182020754
Short name T438
Test name
Test status
Simulation time 326842875652 ps
CPU time 396.56 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:12:18 PM PDT 24
Peak memory 201944 kb
Host smart-f73f7ff5-3933-4ce7-8fab-e6a4844285c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182020754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2182020754
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3480544848
Short name T54
Test name
Test status
Simulation time 379364585528 ps
CPU time 232.15 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:09:33 PM PDT 24
Peak memory 201976 kb
Host smart-77a5337e-14f8-407a-b023-ac69a224528f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480544848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3480544848
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.197457496
Short name T614
Test name
Test status
Simulation time 605974480967 ps
CPU time 491.68 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:13:53 PM PDT 24
Peak memory 201872 kb
Host smart-aea27f56-e1c3-4ca3-9e2d-58a8ef8cbb23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197457496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.197457496
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2160108558
Short name T761
Test name
Test status
Simulation time 124241331265 ps
CPU time 652.37 seconds
Started Mar 28 01:05:43 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 202136 kb
Host smart-759be4dd-6bdb-4f6f-b3c8-2a370161f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160108558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2160108558
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2677132515
Short name T568
Test name
Test status
Simulation time 31705712201 ps
CPU time 14.71 seconds
Started Mar 28 01:05:40 PM PDT 24
Finished Mar 28 01:05:55 PM PDT 24
Peak memory 201464 kb
Host smart-35d479d5-526d-40ab-a219-6a9664a4846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677132515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2677132515
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.558753344
Short name T103
Test name
Test status
Simulation time 4461649785 ps
CPU time 1.47 seconds
Started Mar 28 01:05:44 PM PDT 24
Finished Mar 28 01:05:46 PM PDT 24
Peak memory 201700 kb
Host smart-e2e053d5-66b0-412d-94ca-ffb3daae3165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558753344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.558753344
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1891032069
Short name T371
Test name
Test status
Simulation time 6027750200 ps
CPU time 3.03 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:05:46 PM PDT 24
Peak memory 201652 kb
Host smart-4f4236d2-5d11-4c74-9ca0-57dd48ec8a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891032069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1891032069
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1390686758
Short name T471
Test name
Test status
Simulation time 39897462520 ps
CPU time 18.64 seconds
Started Mar 28 01:05:41 PM PDT 24
Finished Mar 28 01:06:00 PM PDT 24
Peak memory 201620 kb
Host smart-d985e4e8-153e-4030-a6f7-ee1611df9dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390686758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1390686758
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2974081217
Short name T250
Test name
Test status
Simulation time 42986553023 ps
CPU time 48.05 seconds
Started Mar 28 01:05:42 PM PDT 24
Finished Mar 28 01:06:31 PM PDT 24
Peak memory 210632 kb
Host smart-00147d72-32ba-4855-8f48-3e4ac13b2303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974081217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2974081217
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1041046087
Short name T82
Test name
Test status
Simulation time 516098210 ps
CPU time 0.91 seconds
Started Mar 28 01:06:04 PM PDT 24
Finished Mar 28 01:06:05 PM PDT 24
Peak memory 201592 kb
Host smart-9cb95df9-9f2e-4d21-a5e9-9445773759e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041046087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1041046087
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.915748646
Short name T754
Test name
Test status
Simulation time 544643538351 ps
CPU time 1279.85 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 201780 kb
Host smart-d1cf8f20-80ea-4a1b-b57a-79ffea1f6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915748646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.915748646
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4235547444
Short name T149
Test name
Test status
Simulation time 500557025801 ps
CPU time 333.14 seconds
Started Mar 28 01:06:07 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 201964 kb
Host smart-31478261-683c-47f4-8d27-32286164e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235547444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4235547444
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3113221951
Short name T348
Test name
Test status
Simulation time 328302729704 ps
CPU time 195.35 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:09:17 PM PDT 24
Peak memory 201808 kb
Host smart-d4201c48-54d2-4f84-8df1-34f54e7eb56d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113221951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3113221951
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2897669807
Short name T180
Test name
Test status
Simulation time 329894702012 ps
CPU time 200.42 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:09:22 PM PDT 24
Peak memory 201916 kb
Host smart-d88a0d6a-30ad-40ba-8d07-f7dcd82ba149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897669807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2897669807
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3949763248
Short name T511
Test name
Test status
Simulation time 322885465925 ps
CPU time 316.11 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:11:19 PM PDT 24
Peak memory 201884 kb
Host smart-c344331a-6df1-4568-945e-d7878acde7d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949763248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3949763248
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.92562045
Short name T540
Test name
Test status
Simulation time 205653728676 ps
CPU time 120.27 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:08:02 PM PDT 24
Peak memory 201872 kb
Host smart-25683097-d2df-436d-bd56-7853fb138624
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92562045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
dc_ctrl_filters_wakeup_fixed.92562045
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2796748981
Short name T742
Test name
Test status
Simulation time 73657285908 ps
CPU time 388.49 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:12:32 PM PDT 24
Peak memory 202184 kb
Host smart-6c14c7ea-b871-46a1-917e-917f1f0556be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796748981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2796748981
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3504388525
Short name T365
Test name
Test status
Simulation time 28769630027 ps
CPU time 18.03 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:06:19 PM PDT 24
Peak memory 201696 kb
Host smart-048fc6ff-0f16-40ce-89d9-dcf7069d1ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504388525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3504388525
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2530042898
Short name T445
Test name
Test status
Simulation time 4437765349 ps
CPU time 11.6 seconds
Started Mar 28 01:06:00 PM PDT 24
Finished Mar 28 01:06:12 PM PDT 24
Peak memory 201676 kb
Host smart-5fe801f7-200a-4795-bfc9-9ba7f249340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530042898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2530042898
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1317245138
Short name T746
Test name
Test status
Simulation time 6157646476 ps
CPU time 13.45 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:06:15 PM PDT 24
Peak memory 201696 kb
Host smart-69d53863-386b-4191-b1c5-3426aba0caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317245138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1317245138
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2925396368
Short name T633
Test name
Test status
Simulation time 102985463561 ps
CPU time 349.05 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 202280 kb
Host smart-b8bd7c31-afd5-49d4-bb2b-8dbd4bf67fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925396368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2925396368
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3000530289
Short name T70
Test name
Test status
Simulation time 68119835014 ps
CPU time 114.99 seconds
Started Mar 28 01:06:04 PM PDT 24
Finished Mar 28 01:07:59 PM PDT 24
Peak memory 218700 kb
Host smart-2c8f81ae-24cc-4c78-846f-3ddd0032cf91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000530289 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3000530289
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1015979702
Short name T680
Test name
Test status
Simulation time 320953148 ps
CPU time 1.27 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:06:03 PM PDT 24
Peak memory 201608 kb
Host smart-68fbae2a-6275-4f92-8cba-49363e14d9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015979702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1015979702
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3438690830
Short name T655
Test name
Test status
Simulation time 167181504745 ps
CPU time 198.27 seconds
Started Mar 28 01:06:00 PM PDT 24
Finished Mar 28 01:09:19 PM PDT 24
Peak memory 201884 kb
Host smart-b979a8a3-0de6-410a-a300-6c11542f2711
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438690830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3438690830
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.859111806
Short name T300
Test name
Test status
Simulation time 328557615926 ps
CPU time 681.04 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:17:23 PM PDT 24
Peak memory 202024 kb
Host smart-8eaceaea-d795-4cdc-81ab-632a8aa11553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859111806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.859111806
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2473930460
Short name T408
Test name
Test status
Simulation time 164796915844 ps
CPU time 95.99 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:07:37 PM PDT 24
Peak memory 201816 kb
Host smart-32f3da19-2d61-4a5c-b60c-4b90857bffb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473930460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2473930460
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2016596765
Short name T514
Test name
Test status
Simulation time 163762511277 ps
CPU time 178.27 seconds
Started Mar 28 01:06:04 PM PDT 24
Finished Mar 28 01:09:02 PM PDT 24
Peak memory 201948 kb
Host smart-9a94c171-8d6a-44d7-8f77-4df80129f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016596765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2016596765
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.646298596
Short name T453
Test name
Test status
Simulation time 490316792106 ps
CPU time 1180.15 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:25:42 PM PDT 24
Peak memory 201936 kb
Host smart-79fd7cd7-b1a3-4ff3-9249-e73d85b9e033
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646298596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.646298596
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.398327951
Short name T268
Test name
Test status
Simulation time 348655341611 ps
CPU time 204.19 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:09:26 PM PDT 24
Peak memory 201976 kb
Host smart-4e867ff7-aa2d-40c6-92bc-14fcbdc7002f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398327951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.398327951
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3637700803
Short name T507
Test name
Test status
Simulation time 209758463474 ps
CPU time 271.46 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:10:34 PM PDT 24
Peak memory 201788 kb
Host smart-d0c50953-2817-4a69-81ce-03b02bad2b8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637700803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3637700803
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3606203526
Short name T718
Test name
Test status
Simulation time 78207826400 ps
CPU time 288.52 seconds
Started Mar 28 01:05:59 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 202248 kb
Host smart-825a9ea9-5f7c-4742-8711-625c6759126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606203526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3606203526
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.40413225
Short name T700
Test name
Test status
Simulation time 27627284009 ps
CPU time 63.9 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 201708 kb
Host smart-d7247c74-dfc6-4db4-9043-fa86b11bbc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40413225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.40413225
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3033247321
Short name T692
Test name
Test status
Simulation time 4150184394 ps
CPU time 3.08 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:06:05 PM PDT 24
Peak memory 201644 kb
Host smart-7bd3ba5d-501d-4330-8b09-645f140c70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033247321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3033247321
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2238180250
Short name T484
Test name
Test status
Simulation time 6037427366 ps
CPU time 2.39 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:06:04 PM PDT 24
Peak memory 201668 kb
Host smart-a49c0c0b-511b-4936-9a76-472f52df3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238180250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2238180250
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.581981692
Short name T321
Test name
Test status
Simulation time 237809080436 ps
CPU time 338.54 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:11:40 PM PDT 24
Peak memory 210344 kb
Host smart-d0a5ee79-779f-4cb3-ab99-523854982d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581981692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
581981692
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4196052433
Short name T24
Test name
Test status
Simulation time 50189613440 ps
CPU time 154.76 seconds
Started Mar 28 01:06:00 PM PDT 24
Finished Mar 28 01:08:35 PM PDT 24
Peak memory 218424 kb
Host smart-6be0faed-4a15-4b8d-a1c7-175faae25658
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196052433 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4196052433
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.569615085
Short name T81
Test name
Test status
Simulation time 504005081 ps
CPU time 0.91 seconds
Started Mar 28 01:06:18 PM PDT 24
Finished Mar 28 01:06:20 PM PDT 24
Peak memory 201584 kb
Host smart-1326d81e-1f51-46c6-8c34-d0400fdb6e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569615085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.569615085
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2907975170
Short name T770
Test name
Test status
Simulation time 193363375645 ps
CPU time 81.9 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:07:23 PM PDT 24
Peak memory 201996 kb
Host smart-e963b168-1115-4764-b4da-df709a1f569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907975170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2907975170
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1076320014
Short name T322
Test name
Test status
Simulation time 490890301444 ps
CPU time 609.08 seconds
Started Mar 28 01:06:01 PM PDT 24
Finished Mar 28 01:16:10 PM PDT 24
Peak memory 201868 kb
Host smart-1dc99f32-03c9-4da6-9608-b72d28395003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076320014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1076320014
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2188191414
Short name T749
Test name
Test status
Simulation time 326801656477 ps
CPU time 744.76 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:18:27 PM PDT 24
Peak memory 201924 kb
Host smart-1b6466ad-7ffb-4758-9e2c-5e89de4c3ce4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188191414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2188191414
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3575395922
Short name T651
Test name
Test status
Simulation time 493866152917 ps
CPU time 615.26 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:16:19 PM PDT 24
Peak memory 201904 kb
Host smart-52b943c8-e937-4157-918c-99208c268d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575395922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3575395922
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4030067859
Short name T139
Test name
Test status
Simulation time 169023927039 ps
CPU time 108.31 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:07:52 PM PDT 24
Peak memory 201952 kb
Host smart-763aa2a3-4400-45d3-ac4e-178fd820bc65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030067859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4030067859
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1224086038
Short name T611
Test name
Test status
Simulation time 190239843211 ps
CPU time 116.22 seconds
Started Mar 28 01:06:07 PM PDT 24
Finished Mar 28 01:08:03 PM PDT 24
Peak memory 201888 kb
Host smart-77200000-7ff7-46e0-8841-0b98eaa3717d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224086038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1224086038
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.365948228
Short name T522
Test name
Test status
Simulation time 98403676576 ps
CPU time 374.03 seconds
Started Mar 28 01:06:02 PM PDT 24
Finished Mar 28 01:12:16 PM PDT 24
Peak memory 202144 kb
Host smart-c435410a-7ab0-470e-bd9e-80ad87aaa63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365948228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.365948228
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2697354446
Short name T792
Test name
Test status
Simulation time 41747445583 ps
CPU time 8.18 seconds
Started Mar 28 01:06:04 PM PDT 24
Finished Mar 28 01:06:12 PM PDT 24
Peak memory 201680 kb
Host smart-9d0d6fd0-5b6f-40cb-9073-f6d16043a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697354446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2697354446
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1447761468
Short name T165
Test name
Test status
Simulation time 3486448154 ps
CPU time 9.07 seconds
Started Mar 28 01:06:03 PM PDT 24
Finished Mar 28 01:06:12 PM PDT 24
Peak memory 201644 kb
Host smart-86b8d52c-96b4-400e-a603-f17c08f2fb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447761468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1447761468
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3772073504
Short name T482
Test name
Test status
Simulation time 5883253358 ps
CPU time 3.34 seconds
Started Mar 28 01:05:58 PM PDT 24
Finished Mar 28 01:06:01 PM PDT 24
Peak memory 201716 kb
Host smart-dfe70b73-f95c-44d4-9e1c-68fdae1bf299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772073504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3772073504
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1833090307
Short name T5
Test name
Test status
Simulation time 184696560566 ps
CPU time 638.42 seconds
Started Mar 28 01:06:17 PM PDT 24
Finished Mar 28 01:16:55 PM PDT 24
Peak memory 210488 kb
Host smart-87b4acfd-3e4e-479a-91c4-6700e1d5b0c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833090307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1833090307
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.545222522
Short name T369
Test name
Test status
Simulation time 297622616 ps
CPU time 0.79 seconds
Started Mar 28 01:06:18 PM PDT 24
Finished Mar 28 01:06:19 PM PDT 24
Peak memory 201580 kb
Host smart-01be42bc-b4b8-4b91-92fc-394427e251ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545222522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.545222522
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3286571585
Short name T538
Test name
Test status
Simulation time 191273419816 ps
CPU time 214.44 seconds
Started Mar 28 01:06:21 PM PDT 24
Finished Mar 28 01:09:56 PM PDT 24
Peak memory 201888 kb
Host smart-8ac85279-7501-4959-a81e-a86ee8c7d5d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286571585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3286571585
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1624969177
Short name T744
Test name
Test status
Simulation time 497816725243 ps
CPU time 368.49 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:12:28 PM PDT 24
Peak memory 201800 kb
Host smart-b7817907-2fef-484d-8bf6-2ca24fb44cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624969177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1624969177
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.185517454
Short name T623
Test name
Test status
Simulation time 168930872410 ps
CPU time 108.35 seconds
Started Mar 28 01:06:20 PM PDT 24
Finished Mar 28 01:08:08 PM PDT 24
Peak memory 201784 kb
Host smart-29e7607e-30da-42f1-a875-5e11548b84c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=185517454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.185517454
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2871101788
Short name T437
Test name
Test status
Simulation time 498057129746 ps
CPU time 312.37 seconds
Started Mar 28 01:06:20 PM PDT 24
Finished Mar 28 01:11:32 PM PDT 24
Peak memory 201832 kb
Host smart-60d029d9-d8c8-417f-9167-90ae67a79dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871101788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2871101788
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1050503824
Short name T512
Test name
Test status
Simulation time 498655017358 ps
CPU time 551.01 seconds
Started Mar 28 01:06:18 PM PDT 24
Finished Mar 28 01:15:29 PM PDT 24
Peak memory 201784 kb
Host smart-dadc0c87-5872-4e5d-8b21-b93526c90090
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050503824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1050503824
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3474400245
Short name T509
Test name
Test status
Simulation time 534921204252 ps
CPU time 1200.19 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:26:19 PM PDT 24
Peak memory 201888 kb
Host smart-cc788f82-5d69-490a-8dac-73d44b1e6512
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474400245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3474400245
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1906855133
Short name T55
Test name
Test status
Simulation time 205613909384 ps
CPU time 185.62 seconds
Started Mar 28 01:06:18 PM PDT 24
Finished Mar 28 01:09:23 PM PDT 24
Peak memory 201896 kb
Host smart-6de6b541-01eb-48f3-95d9-d8e535f88d9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906855133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1906855133
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2135575030
Short name T712
Test name
Test status
Simulation time 79052516959 ps
CPU time 268.52 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:10:48 PM PDT 24
Peak memory 202168 kb
Host smart-2b641989-c8d2-42b6-bdbd-018f90d4d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135575030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2135575030
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1895265491
Short name T147
Test name
Test status
Simulation time 27467544151 ps
CPU time 15.51 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:06:35 PM PDT 24
Peak memory 201688 kb
Host smart-fc4acda8-3f29-423b-8d1d-f898bc936c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895265491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1895265491
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2340927580
Short name T629
Test name
Test status
Simulation time 5115047365 ps
CPU time 2.42 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:06:22 PM PDT 24
Peak memory 201668 kb
Host smart-fb1dab92-90a7-4963-b6c6-2bd5eb248ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340927580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2340927580
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2972836839
Short name T751
Test name
Test status
Simulation time 5730803161 ps
CPU time 7.55 seconds
Started Mar 28 01:06:23 PM PDT 24
Finished Mar 28 01:06:31 PM PDT 24
Peak memory 201704 kb
Host smart-1e9b5035-fe79-4204-93e6-39444a7d74b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972836839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2972836839
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2454884017
Short name T521
Test name
Test status
Simulation time 385466505 ps
CPU time 0.83 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:06:37 PM PDT 24
Peak memory 201544 kb
Host smart-a9cfee47-cf8e-43dc-a8c9-44ec3327af4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454884017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2454884017
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2952300901
Short name T587
Test name
Test status
Simulation time 175966227303 ps
CPU time 109.38 seconds
Started Mar 28 01:06:22 PM PDT 24
Finished Mar 28 01:08:12 PM PDT 24
Peak memory 201960 kb
Host smart-82480276-692a-4d9c-9e1b-13994c866de2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952300901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2952300901
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.764573760
Short name T325
Test name
Test status
Simulation time 494476437238 ps
CPU time 303.51 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:11:23 PM PDT 24
Peak memory 202024 kb
Host smart-2aeee13b-c706-4123-86bb-d7a184eec50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764573760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.764573760
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.860080889
Short name T619
Test name
Test status
Simulation time 159987534243 ps
CPU time 104.02 seconds
Started Mar 28 01:06:24 PM PDT 24
Finished Mar 28 01:08:08 PM PDT 24
Peak memory 201860 kb
Host smart-7724bcb8-2a23-43c0-a2d9-0d92aa244190
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=860080889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.860080889
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3840271744
Short name T148
Test name
Test status
Simulation time 162189775720 ps
CPU time 92.76 seconds
Started Mar 28 01:06:17 PM PDT 24
Finished Mar 28 01:07:50 PM PDT 24
Peak memory 201944 kb
Host smart-d2f1ac9f-b97f-4650-885a-96454f052587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840271744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3840271744
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2638543970
Short name T391
Test name
Test status
Simulation time 166825549497 ps
CPU time 353.71 seconds
Started Mar 28 01:06:25 PM PDT 24
Finished Mar 28 01:12:19 PM PDT 24
Peak memory 201876 kb
Host smart-5284cf4c-ab22-4828-9a1b-8feb210bcc23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638543970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2638543970
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1563425845
Short name T243
Test name
Test status
Simulation time 541534601230 ps
CPU time 333.83 seconds
Started Mar 28 01:06:17 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 201948 kb
Host smart-c5a1865d-0acd-4959-8f30-44f6728f6528
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563425845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1563425845
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2785490581
Short name T466
Test name
Test status
Simulation time 414195539791 ps
CPU time 234.08 seconds
Started Mar 28 01:06:22 PM PDT 24
Finished Mar 28 01:10:16 PM PDT 24
Peak memory 201968 kb
Host smart-832be314-c21d-42f0-875a-184f292ca2d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785490581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2785490581
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4200089180
Short name T406
Test name
Test status
Simulation time 104794235761 ps
CPU time 383.43 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:12:43 PM PDT 24
Peak memory 202284 kb
Host smart-e4543da7-dbd6-4f02-b919-5ed4e110f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200089180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4200089180
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2147568444
Short name T397
Test name
Test status
Simulation time 30940703116 ps
CPU time 35.78 seconds
Started Mar 28 01:06:17 PM PDT 24
Finished Mar 28 01:06:53 PM PDT 24
Peak memory 201624 kb
Host smart-6f495629-7768-4696-80c2-bfb6b005271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147568444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2147568444
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3516189590
Short name T3
Test name
Test status
Simulation time 3568904800 ps
CPU time 8.82 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:06:28 PM PDT 24
Peak memory 201704 kb
Host smart-07ba4ac0-6c97-4a69-b9ca-c49684a05e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516189590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3516189590
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4250510173
Short name T366
Test name
Test status
Simulation time 5832303578 ps
CPU time 14.27 seconds
Started Mar 28 01:06:19 PM PDT 24
Finished Mar 28 01:06:33 PM PDT 24
Peak memory 201688 kb
Host smart-3f729d94-1f69-46b8-81e7-5e01d760f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250510173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4250510173
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3578825827
Short name T593
Test name
Test status
Simulation time 496135081052 ps
CPU time 142.36 seconds
Started Mar 28 01:06:36 PM PDT 24
Finished Mar 28 01:08:58 PM PDT 24
Peak memory 201852 kb
Host smart-045370f4-4726-47bf-87c6-e09cab9b8164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578825827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3578825827
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3419366645
Short name T763
Test name
Test status
Simulation time 380834264 ps
CPU time 1.52 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:06:37 PM PDT 24
Peak memory 201584 kb
Host smart-dce6a1ac-f0fe-4b5c-a6c5-f43f958cafe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419366645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3419366645
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2277682959
Short name T284
Test name
Test status
Simulation time 180181250666 ps
CPU time 54.76 seconds
Started Mar 28 01:06:34 PM PDT 24
Finished Mar 28 01:07:29 PM PDT 24
Peak memory 201940 kb
Host smart-4a159639-b8ed-4864-ad41-0bbd2fd159fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277682959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2277682959
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1497089704
Short name T293
Test name
Test status
Simulation time 347137644318 ps
CPU time 566.45 seconds
Started Mar 28 01:06:34 PM PDT 24
Finished Mar 28 01:16:01 PM PDT 24
Peak memory 201648 kb
Host smart-64c8269e-235f-4617-a198-23f9954380c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497089704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1497089704
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1336951453
Short name T205
Test name
Test status
Simulation time 491840394512 ps
CPU time 268.08 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:11:03 PM PDT 24
Peak memory 201884 kb
Host smart-21bc5187-d74b-430b-a555-b45ea4d4ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336951453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1336951453
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.508580400
Short name T363
Test name
Test status
Simulation time 323119184699 ps
CPU time 758.82 seconds
Started Mar 28 01:06:34 PM PDT 24
Finished Mar 28 01:19:14 PM PDT 24
Peak memory 201844 kb
Host smart-a5b946e2-13a7-4c83-a386-0270e526fe30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=508580400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.508580400
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2037220001
Short name T672
Test name
Test status
Simulation time 323042752926 ps
CPU time 703.87 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:18:19 PM PDT 24
Peak memory 201860 kb
Host smart-7416191f-6f16-4f5b-b267-15a931051d8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037220001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2037220001
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3170882744
Short name T661
Test name
Test status
Simulation time 277626722055 ps
CPU time 594.39 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:16:30 PM PDT 24
Peak memory 201896 kb
Host smart-213fb84d-62ef-46a3-a2aa-51c03d6e5399
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170882744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3170882744
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3576733461
Short name T394
Test name
Test status
Simulation time 400389619931 ps
CPU time 902.25 seconds
Started Mar 28 01:06:37 PM PDT 24
Finished Mar 28 01:21:41 PM PDT 24
Peak memory 201844 kb
Host smart-bebd7ee9-04fb-46b3-97ea-5d6c2e14ee8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576733461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3576733461
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1803509619
Short name T773
Test name
Test status
Simulation time 103493844759 ps
CPU time 446.44 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:14:02 PM PDT 24
Peak memory 202224 kb
Host smart-8515fcde-afa8-49aa-90be-f8a80a671c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803509619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1803509619
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2036748634
Short name T343
Test name
Test status
Simulation time 25237080894 ps
CPU time 6.29 seconds
Started Mar 28 01:06:34 PM PDT 24
Finished Mar 28 01:06:41 PM PDT 24
Peak memory 201592 kb
Host smart-0cc6f9c3-58fa-4394-9b2f-6e54d124c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036748634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2036748634
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1276222820
Short name T448
Test name
Test status
Simulation time 3358670871 ps
CPU time 8.92 seconds
Started Mar 28 01:06:37 PM PDT 24
Finished Mar 28 01:06:46 PM PDT 24
Peak memory 201708 kb
Host smart-ef22ff5f-aa81-4083-b049-df06ff116bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276222820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1276222820
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.855741395
Short name T358
Test name
Test status
Simulation time 5878112647 ps
CPU time 13.84 seconds
Started Mar 28 01:06:36 PM PDT 24
Finished Mar 28 01:06:50 PM PDT 24
Peak memory 201696 kb
Host smart-156557f1-ea53-4d9e-9f48-c3cac15e11cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855741395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.855741395
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2269590378
Short name T324
Test name
Test status
Simulation time 172271774928 ps
CPU time 44.96 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:07:20 PM PDT 24
Peak memory 201956 kb
Host smart-3e108cf2-9e14-4831-abe1-1cc56aed721b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269590378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2269590378
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3233697961
Short name T410
Test name
Test status
Simulation time 445330012 ps
CPU time 1.06 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:06:57 PM PDT 24
Peak memory 201568 kb
Host smart-7ff27ef9-b923-4426-839f-a86168eeb81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233697961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3233697961
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2203858984
Short name T656
Test name
Test status
Simulation time 375937612328 ps
CPU time 229.57 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:10:46 PM PDT 24
Peak memory 201876 kb
Host smart-829ed8a6-0a60-4da3-a8c7-ea2f8894ac50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203858984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2203858984
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3445409644
Short name T776
Test name
Test status
Simulation time 168506612980 ps
CPU time 424.89 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:13:41 PM PDT 24
Peak memory 201824 kb
Host smart-fef9b56c-c425-49e8-ac5c-36c9860fc2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445409644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3445409644
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.25475250
Short name T485
Test name
Test status
Simulation time 497665854517 ps
CPU time 609.3 seconds
Started Mar 28 01:06:35 PM PDT 24
Finished Mar 28 01:16:44 PM PDT 24
Peak memory 201808 kb
Host smart-a111994b-6c45-4f0f-ad95-c9ba64cb6ad6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25475250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt
_fixed.25475250
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3487360836
Short name T232
Test name
Test status
Simulation time 324930544883 ps
CPU time 67.15 seconds
Started Mar 28 01:06:37 PM PDT 24
Finished Mar 28 01:07:44 PM PDT 24
Peak memory 201868 kb
Host smart-fa4c6af8-4fce-4d16-a4e9-f7eec3ec74e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487360836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3487360836
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3349747617
Short name T743
Test name
Test status
Simulation time 495954242802 ps
CPU time 116.02 seconds
Started Mar 28 01:06:36 PM PDT 24
Finished Mar 28 01:08:33 PM PDT 24
Peak memory 201868 kb
Host smart-4e32f505-dd9c-41dc-b18b-429bc1ab79f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349747617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3349747617
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2303995341
Short name T177
Test name
Test status
Simulation time 426312000097 ps
CPU time 151.81 seconds
Started Mar 28 01:06:37 PM PDT 24
Finished Mar 28 01:09:09 PM PDT 24
Peak memory 201992 kb
Host smart-11dc4529-d40a-40ca-937b-313e234492a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303995341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2303995341
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3728608379
Short name T530
Test name
Test status
Simulation time 206938780483 ps
CPU time 118.66 seconds
Started Mar 28 01:06:34 PM PDT 24
Finished Mar 28 01:08:34 PM PDT 24
Peak memory 202000 kb
Host smart-2293bc80-0c0f-42ea-a405-d457be97bbd7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728608379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3728608379
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3461825797
Short name T338
Test name
Test status
Simulation time 143391350366 ps
CPU time 454.38 seconds
Started Mar 28 01:06:58 PM PDT 24
Finished Mar 28 01:14:32 PM PDT 24
Peak memory 202240 kb
Host smart-ece31fdb-4473-41d7-9d1b-4ea1f2b05cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461825797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3461825797
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1285709163
Short name T411
Test name
Test status
Simulation time 43974869855 ps
CPU time 35.6 seconds
Started Mar 28 01:06:58 PM PDT 24
Finished Mar 28 01:07:33 PM PDT 24
Peak memory 201668 kb
Host smart-a7bbca28-e473-4373-9278-d54f71388b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285709163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1285709163
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4215047559
Short name T675
Test name
Test status
Simulation time 3418853257 ps
CPU time 3.03 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:06:59 PM PDT 24
Peak memory 201672 kb
Host smart-4b54915f-6ea9-4875-9baa-3ccb2574dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215047559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4215047559
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.123468783
Short name T491
Test name
Test status
Simulation time 5548878193 ps
CPU time 12.92 seconds
Started Mar 28 01:06:36 PM PDT 24
Finished Mar 28 01:06:49 PM PDT 24
Peak memory 201760 kb
Host smart-8deb3ee2-a1eb-4e0c-a7af-66c94f64814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123468783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.123468783
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.168148384
Short name T35
Test name
Test status
Simulation time 173389428475 ps
CPU time 57.49 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:07:53 PM PDT 24
Peak memory 201960 kb
Host smart-a92dc861-7428-4107-bc65-c89a0eea2ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168148384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
168148384
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2862309376
Short name T212
Test name
Test status
Simulation time 191660014195 ps
CPU time 158.44 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:09:35 PM PDT 24
Peak memory 211536 kb
Host smart-ac8dd2cb-9842-45f0-8e36-ec75dce60404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862309376 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2862309376
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1315866773
Short name T194
Test name
Test status
Simulation time 542529940 ps
CPU time 0.91 seconds
Started Mar 28 01:06:59 PM PDT 24
Finished Mar 28 01:07:01 PM PDT 24
Peak memory 201564 kb
Host smart-b478fb54-e6c7-476e-82a0-262b65645482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315866773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1315866773
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1720257603
Short name T33
Test name
Test status
Simulation time 496862359040 ps
CPU time 508.49 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:15:24 PM PDT 24
Peak memory 201952 kb
Host smart-e7475c6c-e276-46aa-8889-914fb9cfe021
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720257603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1720257603
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2311080881
Short name T203
Test name
Test status
Simulation time 515750079379 ps
CPU time 314.47 seconds
Started Mar 28 01:06:57 PM PDT 24
Finished Mar 28 01:12:12 PM PDT 24
Peak memory 201764 kb
Host smart-02eef957-3bed-4f75-9236-528ae9166e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311080881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2311080881
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3519899378
Short name T174
Test name
Test status
Simulation time 499197934158 ps
CPU time 311.4 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:12:07 PM PDT 24
Peak memory 201972 kb
Host smart-11ee5240-2c6e-4ff8-acac-fd2e34f11327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519899378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3519899378
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.151992555
Short name T370
Test name
Test status
Simulation time 331785383279 ps
CPU time 385.54 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:13:21 PM PDT 24
Peak memory 201872 kb
Host smart-74cc8619-18e7-4458-b4a8-14acc9d14894
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151992555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.151992555
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2300979925
Short name T271
Test name
Test status
Simulation time 490793609415 ps
CPU time 1133.98 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:25:51 PM PDT 24
Peak memory 201916 kb
Host smart-57cd26d0-51ec-4abb-a823-e49c81634e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300979925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2300979925
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2059530572
Short name T362
Test name
Test status
Simulation time 503755682231 ps
CPU time 305.57 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:11:59 PM PDT 24
Peak memory 201860 kb
Host smart-543a9395-6e29-48b4-b8b0-200aec88c26b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059530572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2059530572
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2032349065
Short name T245
Test name
Test status
Simulation time 556848774898 ps
CPU time 319.27 seconds
Started Mar 28 01:06:57 PM PDT 24
Finished Mar 28 01:12:17 PM PDT 24
Peak memory 201932 kb
Host smart-4b6b3e51-dfc8-416c-9fd8-3cd93874956f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032349065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2032349065
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2996520754
Short name T583
Test name
Test status
Simulation time 208068843284 ps
CPU time 128.73 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:09:05 PM PDT 24
Peak memory 201868 kb
Host smart-f1f0fbe5-d006-4bd0-a6b5-3b311e90aadc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996520754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2996520754
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.735994245
Short name T559
Test name
Test status
Simulation time 104236154502 ps
CPU time 460.03 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:14:36 PM PDT 24
Peak memory 202140 kb
Host smart-9d4d9daf-f2a7-40a9-9241-e7b22e36316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735994245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.735994245
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2349538586
Short name T446
Test name
Test status
Simulation time 22466577989 ps
CPU time 9.46 seconds
Started Mar 28 01:06:59 PM PDT 24
Finished Mar 28 01:07:08 PM PDT 24
Peak memory 201664 kb
Host smart-9ede933f-5d85-459b-ade6-1b19c7f5b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349538586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2349538586
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.238333388
Short name T359
Test name
Test status
Simulation time 4145484173 ps
CPU time 2.93 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:06:59 PM PDT 24
Peak memory 201648 kb
Host smart-2c234fbb-e303-4bfb-afda-3712ae803ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238333388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.238333388
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.869974605
Short name T602
Test name
Test status
Simulation time 6086209035 ps
CPU time 1.7 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:06:58 PM PDT 24
Peak memory 201720 kb
Host smart-4bdf4c03-4f6f-467d-b592-145e303bcdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869974605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.869974605
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2391765127
Short name T704
Test name
Test status
Simulation time 424267676172 ps
CPU time 1219.46 seconds
Started Mar 28 01:06:54 PM PDT 24
Finished Mar 28 01:27:15 PM PDT 24
Peak memory 202252 kb
Host smart-6326f02a-376a-4a57-859d-76606c7f61fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391765127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2391765127
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.281783845
Short name T175
Test name
Test status
Simulation time 1291663395405 ps
CPU time 913.86 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:22:10 PM PDT 24
Peak memory 210592 kb
Host smart-3ef139ff-9100-4b3f-a7ab-6a830cd4e0d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281783845 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.281783845
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1622038526
Short name T558
Test name
Test status
Simulation time 442402368 ps
CPU time 0.82 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:03:46 PM PDT 24
Peak memory 201548 kb
Host smart-817b9311-08ee-42de-a82f-5437a54cbebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622038526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1622038526
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2149515236
Short name T716
Test name
Test status
Simulation time 329455384383 ps
CPU time 161.23 seconds
Started Mar 28 01:03:47 PM PDT 24
Finished Mar 28 01:06:28 PM PDT 24
Peak memory 201984 kb
Host smart-e3f529f8-0b6c-42d8-920c-da94b2e709f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149515236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2149515236
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.851021788
Short name T196
Test name
Test status
Simulation time 162295299689 ps
CPU time 363.51 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:09:46 PM PDT 24
Peak memory 201944 kb
Host smart-49c1e58a-8a2d-449c-ac72-8f2cc105b224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851021788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.851021788
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3151736063
Short name T572
Test name
Test status
Simulation time 161545879638 ps
CPU time 61.94 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:04:45 PM PDT 24
Peak memory 201868 kb
Host smart-89db7d98-4869-4681-b5c0-276e45f82329
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151736063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3151736063
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3461621163
Short name T706
Test name
Test status
Simulation time 334219393032 ps
CPU time 207.44 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:07:09 PM PDT 24
Peak memory 201788 kb
Host smart-cd95dac3-7deb-49b7-b2c2-35e2668d1067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461621163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3461621163
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.994584921
Short name T409
Test name
Test status
Simulation time 333091283849 ps
CPU time 259.06 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:08:13 PM PDT 24
Peak memory 201880 kb
Host smart-e32f9ad7-7430-4555-b5e6-673fc57175ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994584921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.994584921
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2322775814
Short name T190
Test name
Test status
Simulation time 359353130450 ps
CPU time 149.11 seconds
Started Mar 28 01:03:46 PM PDT 24
Finished Mar 28 01:06:15 PM PDT 24
Peak memory 201956 kb
Host smart-7289566f-5594-45de-a997-82bd14590327
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322775814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2322775814
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.359248014
Short name T473
Test name
Test status
Simulation time 599896412675 ps
CPU time 162.65 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:06:27 PM PDT 24
Peak memory 201868 kb
Host smart-7932386a-a49a-4034-abf9-e43160aa5efd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359248014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.359248014
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3017665481
Short name T60
Test name
Test status
Simulation time 124955485726 ps
CPU time 435.16 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:10:58 PM PDT 24
Peak memory 202184 kb
Host smart-df5cf4eb-cf07-421b-9bdc-0c973020d24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017665481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3017665481
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2967451667
Short name T452
Test name
Test status
Simulation time 43856831321 ps
CPU time 24.88 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:04:19 PM PDT 24
Peak memory 201708 kb
Host smart-9e2f20b8-6e11-40c2-929e-b3bab393bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967451667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2967451667
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1897998816
Short name T592
Test name
Test status
Simulation time 2801247141 ps
CPU time 4.17 seconds
Started Mar 28 01:03:46 PM PDT 24
Finished Mar 28 01:03:50 PM PDT 24
Peak memory 201720 kb
Host smart-abe5d930-2ad5-43f1-9691-6623b1f79c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897998816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1897998816
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3102482169
Short name T87
Test name
Test status
Simulation time 3673891600 ps
CPU time 5.41 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:03:47 PM PDT 24
Peak memory 217500 kb
Host smart-c5ad2144-ddd1-4912-8b85-9144476a0070
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102482169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3102482169
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.89166882
Short name T771
Test name
Test status
Simulation time 5886778152 ps
CPU time 4.72 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:03:48 PM PDT 24
Peak memory 201704 kb
Host smart-aa151e7a-1611-4c72-957b-f5f3bea2c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89166882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.89166882
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3481719651
Short name T566
Test name
Test status
Simulation time 170575726886 ps
CPU time 98.34 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:05:20 PM PDT 24
Peak memory 201940 kb
Host smart-f809395a-28af-4d87-88bd-540ab5fd5a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481719651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3481719651
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2992091217
Short name T731
Test name
Test status
Simulation time 81276319295 ps
CPU time 258.66 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:08:01 PM PDT 24
Peak memory 211528 kb
Host smart-5302e187-cbf6-414c-b37a-cf0a5f8338cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992091217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2992091217
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1475804608
Short name T603
Test name
Test status
Simulation time 458714375 ps
CPU time 0.83 seconds
Started Mar 28 01:07:14 PM PDT 24
Finished Mar 28 01:07:15 PM PDT 24
Peak memory 201564 kb
Host smart-d9ce1239-0359-48e7-bd4b-b79ad1c29c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475804608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1475804608
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1550391390
Short name T724
Test name
Test status
Simulation time 189659247525 ps
CPU time 443.48 seconds
Started Mar 28 01:07:10 PM PDT 24
Finished Mar 28 01:14:34 PM PDT 24
Peak memory 201848 kb
Host smart-ad6749b9-5797-462d-bcbb-4abbe0f6fa34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550391390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1550391390
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3626148336
Short name T27
Test name
Test status
Simulation time 172086921842 ps
CPU time 392.23 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:13:29 PM PDT 24
Peak memory 201856 kb
Host smart-7ef09be8-2b9b-49a6-9810-f24dd54ae344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626148336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3626148336
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.826148422
Short name T714
Test name
Test status
Simulation time 328647337863 ps
CPU time 190.83 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:10:07 PM PDT 24
Peak memory 201920 kb
Host smart-de8c1913-a5c1-47fb-ad7e-c5f251699845
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=826148422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.826148422
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1831117941
Short name T496
Test name
Test status
Simulation time 161799888698 ps
CPU time 170.48 seconds
Started Mar 28 01:06:57 PM PDT 24
Finished Mar 28 01:09:48 PM PDT 24
Peak memory 201876 kb
Host smart-e855dfb8-6b6a-403b-a2df-d754be90a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831117941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1831117941
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3823430075
Short name T543
Test name
Test status
Simulation time 331144858878 ps
CPU time 53.45 seconds
Started Mar 28 01:06:57 PM PDT 24
Finished Mar 28 01:07:51 PM PDT 24
Peak memory 201968 kb
Host smart-969fb561-894d-42a2-9059-0fcd84fa8925
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823430075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3823430075
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2640536049
Short name T263
Test name
Test status
Simulation time 185527663871 ps
CPU time 104.27 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:08:40 PM PDT 24
Peak memory 201956 kb
Host smart-56529cc3-ef8f-47e4-bb6a-30599107655e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640536049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2640536049
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.361401735
Short name T347
Test name
Test status
Simulation time 393685019188 ps
CPU time 839.78 seconds
Started Mar 28 01:06:55 PM PDT 24
Finished Mar 28 01:20:56 PM PDT 24
Peak memory 201884 kb
Host smart-259992a6-2166-4fd4-8171-1b7b423b00bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361401735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.361401735
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2767220444
Short name T463
Test name
Test status
Simulation time 78993900142 ps
CPU time 279.72 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:11:51 PM PDT 24
Peak memory 202308 kb
Host smart-fcc3b5a4-9af7-4025-b956-55642d8611b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767220444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2767220444
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1870732006
Short name T472
Test name
Test status
Simulation time 23832823915 ps
CPU time 27.65 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:07:40 PM PDT 24
Peak memory 201700 kb
Host smart-40f0e783-3ee6-46ec-b855-9476bb7f2294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870732006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1870732006
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2428134025
Short name T412
Test name
Test status
Simulation time 5129238279 ps
CPU time 3.44 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:07:15 PM PDT 24
Peak memory 201692 kb
Host smart-0bea9bce-ab93-4f78-99fc-6e64e0228585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428134025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2428134025
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1722213143
Short name T734
Test name
Test status
Simulation time 5899257851 ps
CPU time 13.4 seconds
Started Mar 28 01:06:56 PM PDT 24
Finished Mar 28 01:07:10 PM PDT 24
Peak memory 201716 kb
Host smart-0f4f2447-2ea5-41c0-a844-95818964e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722213143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1722213143
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3194878238
Short name T19
Test name
Test status
Simulation time 79586090483 ps
CPU time 58.88 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:08:12 PM PDT 24
Peak memory 202076 kb
Host smart-71d7c43b-bcff-42d8-9644-87009f00c526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194878238 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3194878238
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.340869501
Short name T401
Test name
Test status
Simulation time 455029084 ps
CPU time 0.84 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:07:13 PM PDT 24
Peak memory 201528 kb
Host smart-593745d7-d06a-4f16-92d9-b958e75c2e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340869501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.340869501
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2769533596
Short name T670
Test name
Test status
Simulation time 160940296921 ps
CPU time 96.61 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:08:50 PM PDT 24
Peak memory 201724 kb
Host smart-792e2323-d491-45ae-abe1-aef92a3144dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769533596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2769533596
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3280942052
Short name T142
Test name
Test status
Simulation time 330150211781 ps
CPU time 420.48 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 201956 kb
Host smart-08c48db0-de92-4d76-9c1f-42311ed17db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280942052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3280942052
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2517371770
Short name T10
Test name
Test status
Simulation time 499753921453 ps
CPU time 552.54 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:16:25 PM PDT 24
Peak memory 201844 kb
Host smart-4f98a621-0167-4f00-8baa-a187c00f1250
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517371770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2517371770
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1457328288
Short name T323
Test name
Test status
Simulation time 331083181390 ps
CPU time 326.42 seconds
Started Mar 28 01:07:14 PM PDT 24
Finished Mar 28 01:12:41 PM PDT 24
Peak memory 201932 kb
Host smart-3e0a6169-f6d9-4074-a226-cdbdc8bddd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457328288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1457328288
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3393758166
Short name T779
Test name
Test status
Simulation time 331849709862 ps
CPU time 389.23 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:13:40 PM PDT 24
Peak memory 201912 kb
Host smart-4a77ffb1-0452-4427-bcc8-b103c573c62c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393758166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3393758166
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3073246895
Short name T684
Test name
Test status
Simulation time 566034913117 ps
CPU time 1210.43 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 201916 kb
Host smart-c7a87ae6-4fa6-4480-8304-c3f8e2024fca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073246895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3073246895
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4102298888
Short name T382
Test name
Test status
Simulation time 411737267122 ps
CPU time 449.48 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:14:41 PM PDT 24
Peak memory 201852 kb
Host smart-a5ab4e1b-95d7-43ea-a320-6cd46884097e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102298888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4102298888
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.441475596
Short name T13
Test name
Test status
Simulation time 83493706161 ps
CPU time 427.88 seconds
Started Mar 28 01:07:14 PM PDT 24
Finished Mar 28 01:14:22 PM PDT 24
Peak memory 202228 kb
Host smart-9fabd122-ad92-4c07-af7a-f3adb7fb43cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441475596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.441475596
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3798915241
Short name T653
Test name
Test status
Simulation time 42151199903 ps
CPU time 51.86 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:08:05 PM PDT 24
Peak memory 201700 kb
Host smart-684a4191-6e3a-426b-a534-bf063eacc2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798915241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3798915241
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2897245892
Short name T434
Test name
Test status
Simulation time 4419571653 ps
CPU time 3.11 seconds
Started Mar 28 01:07:12 PM PDT 24
Finished Mar 28 01:07:16 PM PDT 24
Peak memory 201676 kb
Host smart-dc0b06ea-ced2-4af4-a435-edaa8b3809c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897245892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2897245892
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3362580492
Short name T37
Test name
Test status
Simulation time 5920152415 ps
CPU time 8.17 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:07:21 PM PDT 24
Peak memory 201684 kb
Host smart-80ec12c3-79b9-46ce-8f50-f4d7169e4711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362580492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3362580492
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.511862405
Short name T96
Test name
Test status
Simulation time 331610276288 ps
CPU time 122.76 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:09:13 PM PDT 24
Peak memory 201888 kb
Host smart-37bac349-eeec-477b-977f-ce0b97bbf031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511862405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
511862405
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4200690368
Short name T455
Test name
Test status
Simulation time 421940500 ps
CPU time 0.78 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:07:32 PM PDT 24
Peak memory 201580 kb
Host smart-1c3333dc-dee7-422c-805a-67fea2e005d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200690368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4200690368
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1958798356
Short name T758
Test name
Test status
Simulation time 178855897151 ps
CPU time 47.33 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:08:19 PM PDT 24
Peak memory 201880 kb
Host smart-634d7dd9-bd8e-40d1-abc1-0eb22d6f8ec2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958798356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1958798356
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2545037315
Short name T238
Test name
Test status
Simulation time 165191111716 ps
CPU time 109.48 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:09:19 PM PDT 24
Peak memory 201856 kb
Host smart-4487ad8b-2a39-46e4-affa-061240529e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545037315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2545037315
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.375981421
Short name T790
Test name
Test status
Simulation time 159883910759 ps
CPU time 178.85 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:10:31 PM PDT 24
Peak memory 201976 kb
Host smart-875e063b-62a5-4208-a16f-6550f2c2cab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375981421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.375981421
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2788870214
Short name T562
Test name
Test status
Simulation time 324924170521 ps
CPU time 355.52 seconds
Started Mar 28 01:07:29 PM PDT 24
Finished Mar 28 01:13:24 PM PDT 24
Peak memory 201936 kb
Host smart-7614d85c-9f31-4699-a800-7e9bf41a2b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788870214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2788870214
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1375903143
Short name T199
Test name
Test status
Simulation time 326679912523 ps
CPU time 61.35 seconds
Started Mar 28 01:07:13 PM PDT 24
Finished Mar 28 01:08:15 PM PDT 24
Peak memory 201856 kb
Host smart-ed5edadd-c408-4647-aae4-16e941e62ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375903143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1375903143
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4196369961
Short name T376
Test name
Test status
Simulation time 488919072277 ps
CPU time 1097.49 seconds
Started Mar 28 01:07:11 PM PDT 24
Finished Mar 28 01:25:29 PM PDT 24
Peak memory 201708 kb
Host smart-4d6387b6-2a9e-430b-821b-b4afc52ef211
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196369961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4196369961
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.293484643
Short name T332
Test name
Test status
Simulation time 545972672053 ps
CPU time 330.55 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:13:02 PM PDT 24
Peak memory 201976 kb
Host smart-7fda3aac-b4ff-44a4-90b9-bad864eef8b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293484643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.293484643
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1790688470
Short name T638
Test name
Test status
Simulation time 204360602653 ps
CPU time 420.53 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:14:32 PM PDT 24
Peak memory 201868 kb
Host smart-29b963a7-51c5-48f9-af1a-02cfb90207ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790688470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1790688470
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1432414258
Short name T101
Test name
Test status
Simulation time 31466515322 ps
CPU time 70.25 seconds
Started Mar 28 01:07:32 PM PDT 24
Finished Mar 28 01:08:42 PM PDT 24
Peak memory 201752 kb
Host smart-7fe0f1d2-0e15-41b6-9c82-fd6beedb9e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432414258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1432414258
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.944864487
Short name T658
Test name
Test status
Simulation time 3928905154 ps
CPU time 10.24 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:07:42 PM PDT 24
Peak memory 201688 kb
Host smart-e1d12a34-9585-4aa0-b898-f53c78f4a5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944864487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.944864487
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1949116176
Short name T747
Test name
Test status
Simulation time 5684518963 ps
CPU time 2.59 seconds
Started Mar 28 01:07:14 PM PDT 24
Finished Mar 28 01:07:16 PM PDT 24
Peak memory 201472 kb
Host smart-4957b915-ceea-42e6-ba3e-0ebe0d0a7c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949116176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1949116176
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.826845466
Short name T766
Test name
Test status
Simulation time 375828795952 ps
CPU time 845.02 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:21:37 PM PDT 24
Peak memory 201808 kb
Host smart-aea1827e-d455-4481-b76d-e66e282c57ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826845466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
826845466
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1640573473
Short name T570
Test name
Test status
Simulation time 82692932295 ps
CPU time 178.19 seconds
Started Mar 28 01:07:29 PM PDT 24
Finished Mar 28 01:10:27 PM PDT 24
Peak memory 202060 kb
Host smart-08a05b4e-dab5-4e48-9ed1-18c35473165b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640573473 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1640573473
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1877310137
Short name T503
Test name
Test status
Simulation time 341535908 ps
CPU time 1.33 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:07:33 PM PDT 24
Peak memory 201484 kb
Host smart-14bc6e47-1872-4714-b935-e14ef8cdc6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877310137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1877310137
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1953751332
Short name T264
Test name
Test status
Simulation time 165700306566 ps
CPU time 306.54 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:12:38 PM PDT 24
Peak memory 201788 kb
Host smart-058e1f58-2eb6-4e81-946e-d7ff82407775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953751332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1953751332
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2576635149
Short name T328
Test name
Test status
Simulation time 332114255724 ps
CPU time 424.97 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:14:37 PM PDT 24
Peak memory 201828 kb
Host smart-d44c85f7-fd7d-4c1e-81d0-8a726cbb00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576635149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2576635149
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.511239815
Short name T4
Test name
Test status
Simulation time 326327781810 ps
CPU time 364.55 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:13:34 PM PDT 24
Peak memory 201940 kb
Host smart-71d55843-eb22-4838-a2af-94495a9f50bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=511239815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.511239815
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2838444438
Short name T420
Test name
Test status
Simulation time 328434469019 ps
CPU time 226.06 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 201856 kb
Host smart-dda2fbcf-1edb-41d8-9897-6dd831ea1db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838444438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2838444438
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.25209091
Short name T464
Test name
Test status
Simulation time 327100430785 ps
CPU time 53.79 seconds
Started Mar 28 01:07:35 PM PDT 24
Finished Mar 28 01:08:29 PM PDT 24
Peak memory 201860 kb
Host smart-bd1b2efe-6840-4911-9e52-d5f04ce77d3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed
.25209091
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.163750343
Short name T318
Test name
Test status
Simulation time 525600272896 ps
CPU time 1240.37 seconds
Started Mar 28 01:07:34 PM PDT 24
Finished Mar 28 01:28:14 PM PDT 24
Peak memory 201952 kb
Host smart-fe5c20b8-b5cc-4a9e-bf0d-9b0f0f0a79a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163750343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.163750343
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2542338753
Short name T660
Test name
Test status
Simulation time 603226160755 ps
CPU time 352.27 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:13:24 PM PDT 24
Peak memory 201872 kb
Host smart-2b7c4100-653f-4ff1-9e75-b2241e9279ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542338753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2542338753
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2240989382
Short name T399
Test name
Test status
Simulation time 86060536757 ps
CPU time 316.38 seconds
Started Mar 28 01:07:31 PM PDT 24
Finished Mar 28 01:12:48 PM PDT 24
Peak memory 202116 kb
Host smart-1cb99ff7-4b7f-4c00-8576-a6da19f9b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240989382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2240989382
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3442313453
Short name T352
Test name
Test status
Simulation time 33147087805 ps
CPU time 80.03 seconds
Started Mar 28 01:07:29 PM PDT 24
Finished Mar 28 01:08:49 PM PDT 24
Peak memory 201692 kb
Host smart-e83cb430-5f37-43c6-a63d-f1ba1cb4667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442313453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3442313453
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.215906415
Short name T435
Test name
Test status
Simulation time 3472444797 ps
CPU time 2.96 seconds
Started Mar 28 01:07:29 PM PDT 24
Finished Mar 28 01:07:32 PM PDT 24
Peak memory 201680 kb
Host smart-4e5bf26a-afa6-49b1-88b0-780445464404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215906415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.215906415
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3326969937
Short name T418
Test name
Test status
Simulation time 6004155943 ps
CPU time 7.82 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:07:39 PM PDT 24
Peak memory 201704 kb
Host smart-8fd9083d-9c84-4c89-a835-84b2bab6995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326969937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3326969937
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.134364873
Short name T531
Test name
Test status
Simulation time 215475496482 ps
CPU time 34.51 seconds
Started Mar 28 01:07:30 PM PDT 24
Finished Mar 28 01:08:04 PM PDT 24
Peak memory 201876 kb
Host smart-03f6f0f7-760f-41d3-817d-6748cc800870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134364873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
134364873
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3083041215
Short name T91
Test name
Test status
Simulation time 360307039 ps
CPU time 1.41 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:08:01 PM PDT 24
Peak memory 201596 kb
Host smart-a78a4fc4-871a-4569-98c6-71e6dc151137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083041215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3083041215
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.422112111
Short name T307
Test name
Test status
Simulation time 345603566571 ps
CPU time 388.31 seconds
Started Mar 28 01:07:58 PM PDT 24
Finished Mar 28 01:14:27 PM PDT 24
Peak memory 201956 kb
Host smart-317496a6-b9b9-495a-960e-8955cb159425
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422112111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.422112111
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2307223131
Short name T90
Test name
Test status
Simulation time 182407131012 ps
CPU time 43.22 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 201904 kb
Host smart-8bc22cb6-b721-47d8-99f8-1cf63912e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307223131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2307223131
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3490317448
Short name T740
Test name
Test status
Simulation time 490367093156 ps
CPU time 1178.06 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:27:38 PM PDT 24
Peak memory 201840 kb
Host smart-8b83697f-9d47-48d4-8d12-636ee3eb8f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490317448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3490317448
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1485507227
Short name T500
Test name
Test status
Simulation time 167723538163 ps
CPU time 197.72 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:11:18 PM PDT 24
Peak memory 201808 kb
Host smart-9648352d-5c43-4bed-871b-c2e4a5bebe92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485507227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1485507227
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2878444299
Short name T775
Test name
Test status
Simulation time 319971534312 ps
CPU time 318.55 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:13:18 PM PDT 24
Peak memory 201640 kb
Host smart-138670ee-f00e-439c-9f7b-20985e8ea963
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878444299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2878444299
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2900366430
Short name T601
Test name
Test status
Simulation time 171707972559 ps
CPU time 380.24 seconds
Started Mar 28 01:08:01 PM PDT 24
Finished Mar 28 01:14:21 PM PDT 24
Peak memory 201944 kb
Host smart-3caff1c6-94cd-4a2c-bd56-c5d9e0e4b670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900366430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2900366430
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2851423226
Short name T30
Test name
Test status
Simulation time 589118554867 ps
CPU time 666.09 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:19:06 PM PDT 24
Peak memory 201976 kb
Host smart-f4b34a1e-31cc-489d-aa94-7d2cf8e4a9e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851423226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2851423226
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3821913270
Short name T396
Test name
Test status
Simulation time 80910808663 ps
CPU time 317.97 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:13:18 PM PDT 24
Peak memory 202228 kb
Host smart-fb131d6a-6852-4928-91a1-725ac8f08da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821913270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3821913270
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4241003835
Short name T422
Test name
Test status
Simulation time 33353230419 ps
CPU time 20.83 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:08:21 PM PDT 24
Peak memory 201652 kb
Host smart-1b7f7171-bb99-4759-8094-fc621da4c1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241003835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4241003835
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1441792515
Short name T193
Test name
Test status
Simulation time 3468538864 ps
CPU time 2.76 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:08:02 PM PDT 24
Peak memory 201584 kb
Host smart-53ca0447-6b31-4ca7-90ef-fe2adcbe0f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441792515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1441792515
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.670839804
Short name T421
Test name
Test status
Simulation time 5983600145 ps
CPU time 14.53 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:08:14 PM PDT 24
Peak memory 201660 kb
Host smart-cb421de6-bef1-4bcd-be69-161e4628368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670839804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.670839804
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3701776228
Short name T217
Test name
Test status
Simulation time 447420445780 ps
CPU time 1436.27 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:31:56 PM PDT 24
Peak memory 202212 kb
Host smart-ad20c1be-3c3f-4c25-830f-1a7f0950818b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701776228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3701776228
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1866585450
Short name T267
Test name
Test status
Simulation time 307623487521 ps
CPU time 178.94 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:10:58 PM PDT 24
Peak memory 218740 kb
Host smart-ade9a8ca-f0cb-4e25-be56-18bed49cc2bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866585450 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1866585450
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3246621333
Short name T385
Test name
Test status
Simulation time 305918081 ps
CPU time 0.97 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:08:28 PM PDT 24
Peak memory 201604 kb
Host smart-62ec685e-037f-48e2-97ac-63419eb4a6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246621333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3246621333
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1972077272
Short name T632
Test name
Test status
Simulation time 518972978614 ps
CPU time 627.44 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:18:27 PM PDT 24
Peak memory 201804 kb
Host smart-a1e037fd-b4ed-4db8-8db6-2e0afbd64329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972077272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1972077272
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1332474763
Short name T133
Test name
Test status
Simulation time 490700536464 ps
CPU time 414.6 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:14:54 PM PDT 24
Peak memory 201872 kb
Host smart-96e99f08-eaa9-43bc-b197-bbfb87982921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332474763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1332474763
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2794869399
Short name T636
Test name
Test status
Simulation time 327601272048 ps
CPU time 197.64 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:11:17 PM PDT 24
Peak memory 201876 kb
Host smart-c8000c6b-026a-4b6c-9fa5-7cd6ae6959ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794869399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2794869399
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.81681160
Short name T561
Test name
Test status
Simulation time 487944302270 ps
CPU time 1103.48 seconds
Started Mar 28 01:07:58 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 201908 kb
Host smart-b9e89e3f-abaf-4f48-8df3-a7d9cb87d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81681160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.81681160
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.562985452
Short name T683
Test name
Test status
Simulation time 164754851897 ps
CPU time 390.78 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:14:31 PM PDT 24
Peak memory 201844 kb
Host smart-bf68485b-d788-4d49-83d1-afa49ea346e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=562985452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.562985452
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1858549329
Short name T450
Test name
Test status
Simulation time 197448547818 ps
CPU time 174.4 seconds
Started Mar 28 01:08:02 PM PDT 24
Finished Mar 28 01:10:57 PM PDT 24
Peak memory 201884 kb
Host smart-2bd2ac6d-b15b-417d-b18b-697bb61fa004
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858549329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1858549329
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3302993425
Short name T480
Test name
Test status
Simulation time 76710711007 ps
CPU time 374.5 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:14:40 PM PDT 24
Peak memory 202184 kb
Host smart-426b3c1d-15cb-4912-9521-ac20c5c6629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302993425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3302993425
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1505746452
Short name T777
Test name
Test status
Simulation time 26539247902 ps
CPU time 15.11 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:08:41 PM PDT 24
Peak memory 201592 kb
Host smart-0d3a76ff-24d6-4548-97fa-477b15169b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505746452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1505746452
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.109282549
Short name T465
Test name
Test status
Simulation time 3514062262 ps
CPU time 8.72 seconds
Started Mar 28 01:07:59 PM PDT 24
Finished Mar 28 01:08:08 PM PDT 24
Peak memory 201692 kb
Host smart-f6658aef-b394-4a0f-b843-690834bf444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109282549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.109282549
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3000423277
Short name T40
Test name
Test status
Simulation time 5802512557 ps
CPU time 4.86 seconds
Started Mar 28 01:08:00 PM PDT 24
Finished Mar 28 01:08:05 PM PDT 24
Peak memory 201624 kb
Host smart-ee116d10-a161-45b6-b868-9f1fe4a8ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000423277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3000423277
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2801614293
Short name T642
Test name
Test status
Simulation time 14741600790 ps
CPU time 9.72 seconds
Started Mar 28 01:08:24 PM PDT 24
Finished Mar 28 01:08:34 PM PDT 24
Peak memory 201684 kb
Host smart-ba9930f1-7183-4b20-8890-f04f992f3116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801614293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2801614293
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1036519547
Short name T231
Test name
Test status
Simulation time 96586555835 ps
CPU time 87.54 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 210556 kb
Host smart-7b5606f2-725d-4d3d-bd82-c962c580c40d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036519547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1036519547
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4079811016
Short name T553
Test name
Test status
Simulation time 470192196 ps
CPU time 1.14 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:08:27 PM PDT 24
Peak memory 201576 kb
Host smart-8571992a-551f-49c8-b469-11912e5d8c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079811016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4079811016
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1044049022
Short name T424
Test name
Test status
Simulation time 159396776370 ps
CPU time 60.52 seconds
Started Mar 28 01:08:29 PM PDT 24
Finished Mar 28 01:09:29 PM PDT 24
Peak memory 201796 kb
Host smart-c477b29a-bf5d-4168-9a09-6c65394b9cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044049022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1044049022
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.164237252
Short name T499
Test name
Test status
Simulation time 493205630671 ps
CPU time 555.57 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:17:43 PM PDT 24
Peak memory 201764 kb
Host smart-e47f8362-4a96-47c8-9af3-db95bb5cb9bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=164237252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.164237252
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1494969035
Short name T695
Test name
Test status
Simulation time 323783546923 ps
CPU time 179.94 seconds
Started Mar 28 01:08:24 PM PDT 24
Finished Mar 28 01:11:25 PM PDT 24
Peak memory 201860 kb
Host smart-d1cf741c-5175-4b90-8be9-f2833617c9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494969035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1494969035
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3586847150
Short name T701
Test name
Test status
Simulation time 501002589785 ps
CPU time 1167.64 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 201864 kb
Host smart-835cefa7-da3d-48c9-857f-4780e22373ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586847150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3586847150
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3716060313
Short name T56
Test name
Test status
Simulation time 404798290176 ps
CPU time 494.05 seconds
Started Mar 28 01:08:24 PM PDT 24
Finished Mar 28 01:16:39 PM PDT 24
Peak memory 201968 kb
Host smart-a1431e9e-b878-4b49-ae20-46bf294a00d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716060313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3716060313
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2864588967
Short name T756
Test name
Test status
Simulation time 615661440482 ps
CPU time 86.91 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:09:54 PM PDT 24
Peak memory 201884 kb
Host smart-bffe1861-7b41-4779-92bd-0054c4a1c66b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864588967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2864588967
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3553212122
Short name T168
Test name
Test status
Simulation time 24455688745 ps
CPU time 14.67 seconds
Started Mar 28 01:08:23 PM PDT 24
Finished Mar 28 01:08:38 PM PDT 24
Peak memory 201660 kb
Host smart-f47eca07-e4d8-437f-92e3-b98f90ffead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553212122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3553212122
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1375114314
Short name T794
Test name
Test status
Simulation time 3124515164 ps
CPU time 2.56 seconds
Started Mar 28 01:08:29 PM PDT 24
Finished Mar 28 01:08:32 PM PDT 24
Peak memory 201596 kb
Host smart-7f570e51-ff22-40f9-b5cc-3bf909962590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375114314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1375114314
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3684534418
Short name T639
Test name
Test status
Simulation time 5530646322 ps
CPU time 13.3 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:08:39 PM PDT 24
Peak memory 201640 kb
Host smart-15a3db07-299a-40ba-a531-ae97a4ef5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684534418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3684534418
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1934539468
Short name T18
Test name
Test status
Simulation time 267158464254 ps
CPU time 491.43 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:16:37 PM PDT 24
Peak memory 210508 kb
Host smart-423d0ae8-fce9-4732-8b43-2b6ebfd5a0f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934539468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1934539468
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1072272413
Short name T764
Test name
Test status
Simulation time 507928087 ps
CPU time 1.26 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:08:27 PM PDT 24
Peak memory 201524 kb
Host smart-9bc4dae4-091d-495c-b45d-e01e27236c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072272413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1072272413
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4197306323
Short name T286
Test name
Test status
Simulation time 505825442883 ps
CPU time 290.33 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:13:17 PM PDT 24
Peak memory 201856 kb
Host smart-1f3f8c3f-176d-4995-9556-673f1c6c9af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197306323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4197306323
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.823132095
Short name T155
Test name
Test status
Simulation time 324261618323 ps
CPU time 185.17 seconds
Started Mar 28 01:08:28 PM PDT 24
Finished Mar 28 01:11:33 PM PDT 24
Peak memory 201888 kb
Host smart-d55b7749-6218-4bb8-86d4-c2632c20d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823132095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.823132095
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2856265162
Short name T29
Test name
Test status
Simulation time 329448252042 ps
CPU time 711.06 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:20:17 PM PDT 24
Peak memory 201860 kb
Host smart-9e0a80ce-9896-4a7d-9c4d-8561df0c405e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856265162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2856265162
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3740307368
Short name T310
Test name
Test status
Simulation time 165187917800 ps
CPU time 201.56 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:11:48 PM PDT 24
Peak memory 201884 kb
Host smart-7ca405b7-e402-4063-b99a-05d0d3269f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740307368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3740307368
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.763652137
Short name T641
Test name
Test status
Simulation time 325123615813 ps
CPU time 373.73 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:14:40 PM PDT 24
Peak memory 201884 kb
Host smart-c3b5c419-552b-4425-b41d-a876c668232d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=763652137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.763652137
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.151244614
Short name T657
Test name
Test status
Simulation time 404842575347 ps
CPU time 155.51 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:11:02 PM PDT 24
Peak memory 201828 kb
Host smart-28354eb3-cc47-49df-8b71-36d703a35cc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151244614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.151244614
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1721013976
Short name T213
Test name
Test status
Simulation time 110449187014 ps
CPU time 347.56 seconds
Started Mar 28 01:08:23 PM PDT 24
Finished Mar 28 01:14:11 PM PDT 24
Peak memory 202188 kb
Host smart-c51fca88-ba83-4c19-86f1-c9615e1a69fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721013976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1721013976
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.525006742
Short name T703
Test name
Test status
Simulation time 23920698592 ps
CPU time 14.66 seconds
Started Mar 28 01:08:29 PM PDT 24
Finished Mar 28 01:08:44 PM PDT 24
Peak memory 201620 kb
Host smart-7f0724a4-4023-4854-a3a5-e1fac9da8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525006742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.525006742
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3145002110
Short name T506
Test name
Test status
Simulation time 5154634304 ps
CPU time 3.24 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:08:30 PM PDT 24
Peak memory 201712 kb
Host smart-3fd55db1-15de-4a97-9440-633e8774766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145002110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3145002110
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3834387130
Short name T728
Test name
Test status
Simulation time 5900936330 ps
CPU time 3.03 seconds
Started Mar 28 01:08:28 PM PDT 24
Finished Mar 28 01:08:31 PM PDT 24
Peak memory 201704 kb
Host smart-c06eb252-4c17-47aa-ad2f-e0520bdb3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834387130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3834387130
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1560196884
Short name T59
Test name
Test status
Simulation time 74794090149 ps
CPU time 253.72 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:12:39 PM PDT 24
Peak memory 202124 kb
Host smart-b75cee91-b92f-49ce-8a48-cfe3f125b08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560196884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1560196884
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.916663539
Short name T567
Test name
Test status
Simulation time 29751609092 ps
CPU time 115.12 seconds
Started Mar 28 01:08:23 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 210540 kb
Host smart-ff1a45f0-3ca9-4c5b-bcd1-6fd48a13d86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916663539 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.916663539
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1897621426
Short name T375
Test name
Test status
Simulation time 445977799 ps
CPU time 1.71 seconds
Started Mar 28 01:08:43 PM PDT 24
Finished Mar 28 01:08:45 PM PDT 24
Peak memory 201536 kb
Host smart-87fa42de-ff2c-47c7-8795-d35eaa82dd16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897621426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1897621426
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3229918961
Short name T613
Test name
Test status
Simulation time 331539274406 ps
CPU time 216.27 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:12:16 PM PDT 24
Peak memory 201904 kb
Host smart-9f1a8e26-70e6-4614-9693-853430828523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229918961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3229918961
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2227124011
Short name T145
Test name
Test status
Simulation time 498894675062 ps
CPU time 206.1 seconds
Started Mar 28 01:08:26 PM PDT 24
Finished Mar 28 01:11:52 PM PDT 24
Peak memory 201832 kb
Host smart-663298fd-2a4f-476f-922e-873d25bbd612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227124011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2227124011
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.487537882
Short name T346
Test name
Test status
Simulation time 161836746496 ps
CPU time 170.41 seconds
Started Mar 28 01:08:24 PM PDT 24
Finished Mar 28 01:11:15 PM PDT 24
Peak memory 201872 kb
Host smart-67541e74-47c5-417c-aa32-4067fc790023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=487537882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.487537882
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1804099844
Short name T12
Test name
Test status
Simulation time 163983354295 ps
CPU time 98.23 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:10:04 PM PDT 24
Peak memory 201952 kb
Host smart-8b2e2ffc-215f-409d-ba20-304055bc621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804099844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1804099844
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3745698714
Short name T110
Test name
Test status
Simulation time 327026235597 ps
CPU time 783.36 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:21:31 PM PDT 24
Peak memory 201816 kb
Host smart-7fa3fbbd-1e50-4f65-abf3-68d0ae98f640
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745698714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3745698714
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1861024111
Short name T201
Test name
Test status
Simulation time 374229385716 ps
CPU time 191.2 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:11:36 PM PDT 24
Peak memory 201980 kb
Host smart-d5ac4099-38f9-4e39-8a02-20f6171ebd9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861024111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1861024111
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1095948866
Short name T729
Test name
Test status
Simulation time 392059246552 ps
CPU time 80.3 seconds
Started Mar 28 01:08:27 PM PDT 24
Finished Mar 28 01:09:47 PM PDT 24
Peak memory 201956 kb
Host smart-6896a891-58fe-48d2-a58d-1ab8d77317b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095948866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1095948866
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.337339893
Short name T220
Test name
Test status
Simulation time 132916138263 ps
CPU time 534.78 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:17:36 PM PDT 24
Peak memory 202184 kb
Host smart-bc470f9e-db1b-4876-a00f-7755ae582926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337339893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.337339893
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2393589226
Short name T635
Test name
Test status
Simulation time 26172713422 ps
CPU time 29.19 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:09:09 PM PDT 24
Peak memory 201680 kb
Host smart-fe64569d-03a7-42ab-90ce-5dccce27f122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393589226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2393589226
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2789187598
Short name T462
Test name
Test status
Simulation time 3113068833 ps
CPU time 2.41 seconds
Started Mar 28 01:08:39 PM PDT 24
Finished Mar 28 01:08:41 PM PDT 24
Peak memory 201472 kb
Host smart-3f0d51bb-abd0-48d0-a364-715cc08a6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789187598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2789187598
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3777224261
Short name T667
Test name
Test status
Simulation time 6070933653 ps
CPU time 3.77 seconds
Started Mar 28 01:08:25 PM PDT 24
Finished Mar 28 01:08:30 PM PDT 24
Peak memory 201620 kb
Host smart-d4496c39-d9b4-4ed3-88b4-e81dca1385f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777224261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3777224261
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.127925180
Short name T288
Test name
Test status
Simulation time 258257919918 ps
CPU time 188.64 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:11:49 PM PDT 24
Peak memory 217856 kb
Host smart-5905b33d-300c-48f4-ad13-7fbff115c74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127925180 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.127925180
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.478269653
Short name T539
Test name
Test status
Simulation time 490951618 ps
CPU time 1.65 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:08:42 PM PDT 24
Peak memory 201552 kb
Host smart-df06fff0-d93a-4448-b9b6-b62df2a8497e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478269653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.478269653
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1699862317
Short name T226
Test name
Test status
Simulation time 546385165172 ps
CPU time 823.86 seconds
Started Mar 28 01:08:39 PM PDT 24
Finished Mar 28 01:22:23 PM PDT 24
Peak memory 201908 kb
Host smart-c0e14ba8-1818-47bb-9ca0-7f31e5cd254f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699862317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1699862317
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2881232375
Short name T297
Test name
Test status
Simulation time 163517411491 ps
CPU time 96.08 seconds
Started Mar 28 01:08:42 PM PDT 24
Finished Mar 28 01:10:19 PM PDT 24
Peak memory 201912 kb
Host smart-2ad66bb2-cadb-465e-89be-cfd6daee253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881232375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2881232375
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1189874182
Short name T387
Test name
Test status
Simulation time 492767623360 ps
CPU time 580.92 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:18:22 PM PDT 24
Peak memory 201940 kb
Host smart-2bb55974-8c99-4327-845a-50c2619d05fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189874182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1189874182
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1058348838
Short name T578
Test name
Test status
Simulation time 162902609530 ps
CPU time 360.87 seconds
Started Mar 28 01:08:39 PM PDT 24
Finished Mar 28 01:14:40 PM PDT 24
Peak memory 201828 kb
Host smart-9ed26020-2e16-4005-91e1-8f31e5491e9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058348838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1058348838
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3287027505
Short name T483
Test name
Test status
Simulation time 201907535048 ps
CPU time 469.68 seconds
Started Mar 28 01:08:43 PM PDT 24
Finished Mar 28 01:16:33 PM PDT 24
Peak memory 201916 kb
Host smart-0facb4d3-5bec-4819-aec0-139f2b33c71d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287027505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3287027505
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3404252602
Short name T687
Test name
Test status
Simulation time 134046631781 ps
CPU time 474.7 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:16:35 PM PDT 24
Peak memory 202188 kb
Host smart-f508b44d-ca72-4e5a-8dce-8f8c4e3db6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404252602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3404252602
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2461510880
Short name T659
Test name
Test status
Simulation time 36173771539 ps
CPU time 21.31 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:09:02 PM PDT 24
Peak memory 201668 kb
Host smart-4e1b2690-451c-4fba-9788-8a1248a2ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461510880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2461510880
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3571703
Short name T548
Test name
Test status
Simulation time 3023062320 ps
CPU time 2.57 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:08:43 PM PDT 24
Peak memory 201628 kb
Host smart-c1ef6359-2f04-4e0c-aa02-6473eb494dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3571703
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2515976353
Short name T364
Test name
Test status
Simulation time 5925726842 ps
CPU time 12.88 seconds
Started Mar 28 01:08:38 PM PDT 24
Finished Mar 28 01:08:51 PM PDT 24
Peak memory 201688 kb
Host smart-693c0b98-a105-4fed-9a67-fde2622b57e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515976353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2515976353
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2849454917
Short name T132
Test name
Test status
Simulation time 10643245826 ps
CPU time 13.14 seconds
Started Mar 28 01:08:40 PM PDT 24
Finished Mar 28 01:08:53 PM PDT 24
Peak memory 201680 kb
Host smart-3e73e76b-319f-4380-ba8a-32c3a69a7d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849454917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2849454917
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2226768844
Short name T314
Test name
Test status
Simulation time 149021299452 ps
CPU time 97 seconds
Started Mar 28 01:08:41 PM PDT 24
Finished Mar 28 01:10:18 PM PDT 24
Peak memory 210228 kb
Host smart-b99443af-9234-4ed4-a405-051cf9364c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226768844 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2226768844
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2951407872
Short name T590
Test name
Test status
Simulation time 386667770 ps
CPU time 1.1 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:03:45 PM PDT 24
Peak memory 201548 kb
Host smart-4d45dcd5-c877-45fc-a54a-6fabcf5f6a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951407872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2951407872
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1200835624
Short name T331
Test name
Test status
Simulation time 508114610494 ps
CPU time 227.61 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:07:30 PM PDT 24
Peak memory 201852 kb
Host smart-f6ee64af-ce23-43b9-bfc2-fe677e6bb06a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200835624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1200835624
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3439665843
Short name T309
Test name
Test status
Simulation time 498850612568 ps
CPU time 1235.45 seconds
Started Mar 28 01:03:46 PM PDT 24
Finished Mar 28 01:24:22 PM PDT 24
Peak memory 201856 kb
Host smart-ebb4c6ad-8d12-432a-a8d7-8cf62f2963b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439665843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3439665843
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1279031160
Short name T431
Test name
Test status
Simulation time 497094185164 ps
CPU time 1201.24 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:23:45 PM PDT 24
Peak memory 201860 kb
Host smart-9010ef01-f61d-4035-9f6f-255c17dbd10a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279031160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1279031160
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.874141421
Short name T693
Test name
Test status
Simulation time 329095955490 ps
CPU time 201.61 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:07:05 PM PDT 24
Peak memory 201900 kb
Host smart-ba572056-8229-45d0-a6fa-ca6ff63a3418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874141421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.874141421
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3107786895
Short name T153
Test name
Test status
Simulation time 328198680287 ps
CPU time 348.94 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:09:32 PM PDT 24
Peak memory 201796 kb
Host smart-c008ff1b-546d-4be0-999d-3fbf1dd7eb60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107786895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3107786895
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1884041609
Short name T760
Test name
Test status
Simulation time 603445561301 ps
CPU time 364.61 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:09:59 PM PDT 24
Peak memory 201876 kb
Host smart-4a408483-8a74-4757-88fc-9f12895d837c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884041609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1884041609
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.251718722
Short name T403
Test name
Test status
Simulation time 75296159911 ps
CPU time 277.34 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:08:20 PM PDT 24
Peak memory 202188 kb
Host smart-3ce3ec41-655c-4935-9556-bb36d9cf7509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251718722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.251718722
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2602984138
Short name T419
Test name
Test status
Simulation time 30489599951 ps
CPU time 65.41 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:04:49 PM PDT 24
Peak memory 201692 kb
Host smart-473c7ef1-7fb9-4e18-9a15-edac1a0f033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602984138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2602984138
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2942966359
Short name T416
Test name
Test status
Simulation time 4124233534 ps
CPU time 7.35 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:03:49 PM PDT 24
Peak memory 201724 kb
Host smart-0c1743c0-a4af-47a2-a861-063f5a3b91f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942966359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2942966359
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3354154126
Short name T26
Test name
Test status
Simulation time 5546688909 ps
CPU time 6.79 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:03:50 PM PDT 24
Peak memory 201704 kb
Host smart-9ab53632-b17e-4074-9d2c-c075c5ecbcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354154126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3354154126
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2334025129
Short name T646
Test name
Test status
Simulation time 154561597639 ps
CPU time 648.5 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:14:32 PM PDT 24
Peak memory 202208 kb
Host smart-f550c253-710a-415a-b026-afacfa23b339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334025129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2334025129
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.492862356
Short name T647
Test name
Test status
Simulation time 25280385640 ps
CPU time 63.44 seconds
Started Mar 28 01:03:55 PM PDT 24
Finished Mar 28 01:04:58 PM PDT 24
Peak memory 210620 kb
Host smart-c27baa3c-5de1-4222-9944-2b42ea97c3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492862356 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.492862356
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.832351209
Short name T493
Test name
Test status
Simulation time 469040019 ps
CPU time 0.88 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:03:43 PM PDT 24
Peak memory 201516 kb
Host smart-65f96294-7ddd-4162-b5c5-bda75a36746a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832351209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.832351209
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1605424439
Short name T173
Test name
Test status
Simulation time 330461756657 ps
CPU time 158.36 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:06:21 PM PDT 24
Peak memory 201868 kb
Host smart-7c2deafa-6be6-41f8-81f0-50622b437a60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605424439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1605424439
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.256589399
Short name T622
Test name
Test status
Simulation time 164654804869 ps
CPU time 205.13 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 201892 kb
Host smart-b665374d-1ac8-42f8-8b54-d0ea2f17dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256589399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.256589399
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.478327941
Short name T281
Test name
Test status
Simulation time 497511124402 ps
CPU time 570.05 seconds
Started Mar 28 01:03:46 PM PDT 24
Finished Mar 28 01:13:16 PM PDT 24
Peak memory 201888 kb
Host smart-1c1d1b0d-dada-47d2-a703-7fc91e6e10ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478327941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.478327941
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.386359293
Short name T427
Test name
Test status
Simulation time 160768770818 ps
CPU time 155.6 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:06:21 PM PDT 24
Peak memory 201836 kb
Host smart-65400107-2998-499d-9fe4-68fdfe9e62a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=386359293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.386359293
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3167907959
Short name T140
Test name
Test status
Simulation time 495005204513 ps
CPU time 1103.37 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:22:08 PM PDT 24
Peak memory 201796 kb
Host smart-a35e87cb-e87a-4842-b809-20dfa958f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167907959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3167907959
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2979929340
Short name T513
Test name
Test status
Simulation time 161292679019 ps
CPU time 179.34 seconds
Started Mar 28 01:03:41 PM PDT 24
Finished Mar 28 01:06:40 PM PDT 24
Peak memory 201848 kb
Host smart-ed8eea4d-586c-4005-ad06-75ba9db68dc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979929340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2979929340
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3933827750
Short name T598
Test name
Test status
Simulation time 392467028378 ps
CPU time 202.27 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:07:07 PM PDT 24
Peak memory 201928 kb
Host smart-fa31e0b9-02da-43f8-b448-313b57bf9246
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933827750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3933827750
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.72910423
Short name T720
Test name
Test status
Simulation time 108752502049 ps
CPU time 477.05 seconds
Started Mar 28 01:03:44 PM PDT 24
Finished Mar 28 01:11:41 PM PDT 24
Peak memory 202252 kb
Host smart-57123001-48f1-4597-aa76-a38344ea97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72910423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.72910423
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2177863331
Short name T378
Test name
Test status
Simulation time 34819750229 ps
CPU time 16.93 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:04:02 PM PDT 24
Peak memory 201568 kb
Host smart-b62bd3d2-1048-4eb7-8cb1-98110ef6c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177863331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2177863331
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2209922288
Short name T107
Test name
Test status
Simulation time 4916051558 ps
CPU time 3.56 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:03:49 PM PDT 24
Peak memory 201672 kb
Host smart-62e578c5-1239-4990-9b07-2ae62553bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209922288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2209922288
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3785989171
Short name T726
Test name
Test status
Simulation time 5959123955 ps
CPU time 14.98 seconds
Started Mar 28 01:03:43 PM PDT 24
Finished Mar 28 01:03:58 PM PDT 24
Peak memory 201724 kb
Host smart-62ccd287-7fd0-431b-9bfd-6f4ca8f98df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785989171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3785989171
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1214541808
Short name T106
Test name
Test status
Simulation time 191998784470 ps
CPU time 234.9 seconds
Started Mar 28 01:03:42 PM PDT 24
Finished Mar 28 01:07:37 PM PDT 24
Peak memory 201964 kb
Host smart-9c1dfd50-cc36-44dc-aba8-6ade7f99c374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214541808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1214541808
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4084425473
Short name T486
Test name
Test status
Simulation time 27912163311 ps
CPU time 69.46 seconds
Started Mar 28 01:03:54 PM PDT 24
Finished Mar 28 01:05:04 PM PDT 24
Peak memory 210316 kb
Host smart-c9eda835-b16b-4880-83bc-bb6c2cc82664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084425473 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4084425473
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1498747367
Short name T447
Test name
Test status
Simulation time 519000570 ps
CPU time 1.89 seconds
Started Mar 28 01:04:02 PM PDT 24
Finished Mar 28 01:04:04 PM PDT 24
Peak memory 201500 kb
Host smart-5a244fa3-8d7a-4e48-8283-d4769146aa0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498747367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1498747367
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.830295011
Short name T296
Test name
Test status
Simulation time 172409184814 ps
CPU time 63 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:05:06 PM PDT 24
Peak memory 201876 kb
Host smart-188cfa88-d702-487f-9d67-2a802aff7b27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830295011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.830295011
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3418424893
Short name T308
Test name
Test status
Simulation time 172036708406 ps
CPU time 388.05 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:10:33 PM PDT 24
Peak memory 201776 kb
Host smart-6a027c14-4125-4ea4-8e8d-259f762c12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418424893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3418424893
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.411403973
Short name T285
Test name
Test status
Simulation time 501722270009 ps
CPU time 1081.29 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:22:06 PM PDT 24
Peak memory 201964 kb
Host smart-141a9efb-a613-45f3-a4cf-c2054b5f0fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411403973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.411403973
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3896196618
Short name T170
Test name
Test status
Simulation time 166438400983 ps
CPU time 101.13 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:05:46 PM PDT 24
Peak memory 201816 kb
Host smart-977dd8bb-341c-4a47-a6f4-9c7e118ca13f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896196618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3896196618
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.352996590
Short name T762
Test name
Test status
Simulation time 164954621510 ps
CPU time 355.03 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:09:59 PM PDT 24
Peak memory 201936 kb
Host smart-4ee003ed-3f31-488f-8051-005ccd9e5634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352996590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.352996590
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3675777826
Short name T405
Test name
Test status
Simulation time 487485496523 ps
CPU time 1184.63 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:23:51 PM PDT 24
Peak memory 201856 kb
Host smart-4178664a-9a0c-4558-93f0-c1ccce5e2202
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675777826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3675777826
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3985326595
Short name T181
Test name
Test status
Simulation time 543205008950 ps
CPU time 322.5 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:09:28 PM PDT 24
Peak memory 201988 kb
Host smart-7fca4b85-9325-4bfe-a196-61c412cfa219
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985326595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3985326595
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3920671475
Short name T520
Test name
Test status
Simulation time 615599419693 ps
CPU time 270 seconds
Started Mar 28 01:04:02 PM PDT 24
Finished Mar 28 01:08:32 PM PDT 24
Peak memory 201864 kb
Host smart-167f8a84-49a5-40e2-979c-9c81bafbb2ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920671475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3920671475
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3785171992
Short name T518
Test name
Test status
Simulation time 85276715438 ps
CPU time 350.97 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:09:55 PM PDT 24
Peak memory 202256 kb
Host smart-178174a9-7153-4dac-bcea-6e87ccf21fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785171992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3785171992
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3349230375
Short name T102
Test name
Test status
Simulation time 23791734350 ps
CPU time 29.82 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:04:34 PM PDT 24
Peak memory 201676 kb
Host smart-d0f7fe4d-487e-4953-afe7-c3cab4922a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349230375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3349230375
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2259206371
Short name T722
Test name
Test status
Simulation time 4639181520 ps
CPU time 6.04 seconds
Started Mar 28 01:04:09 PM PDT 24
Finished Mar 28 01:04:15 PM PDT 24
Peak memory 201656 kb
Host smart-d0c02081-2443-41f5-9511-aeb3b1699c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259206371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2259206371
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2039363274
Short name T425
Test name
Test status
Simulation time 5676079371 ps
CPU time 15.14 seconds
Started Mar 28 01:03:45 PM PDT 24
Finished Mar 28 01:04:01 PM PDT 24
Peak memory 201676 kb
Host smart-c3fdf235-1928-4460-9421-4dd3d726fa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039363274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2039363274
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.876684603
Short name T299
Test name
Test status
Simulation time 281744190301 ps
CPU time 652.71 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:14:58 PM PDT 24
Peak memory 202204 kb
Host smart-4d48345e-1255-4f56-975e-67e79e7deca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876684603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.876684603
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1431426510
Short name T645
Test name
Test status
Simulation time 421923028016 ps
CPU time 370.96 seconds
Started Mar 28 01:04:02 PM PDT 24
Finished Mar 28 01:10:13 PM PDT 24
Peak memory 210584 kb
Host smart-fce0ca6c-a05b-42f8-89a0-75fcd430b6f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431426510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1431426510
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.478289888
Short name T487
Test name
Test status
Simulation time 417441439 ps
CPU time 0.87 seconds
Started Mar 28 01:04:07 PM PDT 24
Finished Mar 28 01:04:08 PM PDT 24
Peak memory 201484 kb
Host smart-2091b9f8-cc7b-452e-a929-2c7642d4d2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478289888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.478289888
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.82280658
Short name T488
Test name
Test status
Simulation time 178446847146 ps
CPU time 398.5 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:10:43 PM PDT 24
Peak memory 201876 kb
Host smart-64473a7f-078a-4ca2-a26b-190224afd1e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82280658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating
.82280658
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4065432805
Short name T287
Test name
Test status
Simulation time 321277465855 ps
CPU time 796.71 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:17:23 PM PDT 24
Peak memory 201864 kb
Host smart-da39dbb0-4afb-4068-a6ea-ed042a3232d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065432805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4065432805
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3981629501
Short name T765
Test name
Test status
Simulation time 317357578580 ps
CPU time 740.6 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:16:27 PM PDT 24
Peak memory 201980 kb
Host smart-3802b19d-a25d-4ebc-b1ca-fe51817f7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981629501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3981629501
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.395278597
Short name T654
Test name
Test status
Simulation time 329746875347 ps
CPU time 187.64 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:07:13 PM PDT 24
Peak memory 201888 kb
Host smart-a5cc1932-0863-401a-bc89-9c0f9a641465
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395278597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.395278597
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2856422155
Short name T525
Test name
Test status
Simulation time 483212498495 ps
CPU time 890.14 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:18:53 PM PDT 24
Peak memory 201904 kb
Host smart-ce52626e-6f85-45dc-a1e2-1465a88d1726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856422155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2856422155
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3807454667
Short name T444
Test name
Test status
Simulation time 335065293267 ps
CPU time 127.51 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:06:11 PM PDT 24
Peak memory 201884 kb
Host smart-1c89db08-7d09-4757-906e-185efb1b73b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807454667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3807454667
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4271162265
Short name T468
Test name
Test status
Simulation time 178614817006 ps
CPU time 33.02 seconds
Started Mar 28 01:04:02 PM PDT 24
Finished Mar 28 01:04:35 PM PDT 24
Peak memory 201868 kb
Host smart-7095cb30-44d3-43f5-8a65-59182f65a016
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271162265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4271162265
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1608673456
Short name T618
Test name
Test status
Simulation time 195587678013 ps
CPU time 451.8 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:11:38 PM PDT 24
Peak memory 201880 kb
Host smart-a660b272-a07e-4d3d-89df-33e99a5ab29a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608673456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1608673456
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1315599940
Short name T214
Test name
Test status
Simulation time 129976038804 ps
CPU time 496.95 seconds
Started Mar 28 01:04:03 PM PDT 24
Finished Mar 28 01:12:20 PM PDT 24
Peak memory 202220 kb
Host smart-bbd798f2-86e2-4efe-864f-f6d9a2c9e97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315599940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1315599940
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.733008612
Short name T516
Test name
Test status
Simulation time 47814286289 ps
CPU time 67.6 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:05:11 PM PDT 24
Peak memory 201680 kb
Host smart-35be0e1e-ee1c-41c3-9c63-97805fee46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733008612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.733008612
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.376639936
Short name T637
Test name
Test status
Simulation time 5100807778 ps
CPU time 3.74 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:04:09 PM PDT 24
Peak memory 201708 kb
Host smart-eb260747-9c43-445e-ba62-450c65e82837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376639936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.376639936
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2228456096
Short name T576
Test name
Test status
Simulation time 5862392751 ps
CPU time 4.56 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:04:11 PM PDT 24
Peak memory 201700 kb
Host smart-b78d717c-1d3a-4625-af6a-bcc6a6653221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228456096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2228456096
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1178130409
Short name T279
Test name
Test status
Simulation time 88519161171 ps
CPU time 96.46 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:05:42 PM PDT 24
Peak memory 202120 kb
Host smart-ff421d14-f410-4e40-8ec9-59878f8f3320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178130409 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1178130409
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3398772737
Short name T384
Test name
Test status
Simulation time 285279991 ps
CPU time 1.39 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:04:08 PM PDT 24
Peak memory 201584 kb
Host smart-def80a91-9183-40e9-b8f8-e025bd62e4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398772737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3398772737
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3013341427
Short name T276
Test name
Test status
Simulation time 331546307998 ps
CPU time 212.19 seconds
Started Mar 28 01:04:09 PM PDT 24
Finished Mar 28 01:07:42 PM PDT 24
Peak memory 201840 kb
Host smart-173d544b-4c99-4abb-a6d9-6aea465c15b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013341427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3013341427
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.302146604
Short name T739
Test name
Test status
Simulation time 329143063008 ps
CPU time 717.57 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:16:04 PM PDT 24
Peak memory 201880 kb
Host smart-397c2587-2bf8-498a-9b3a-8554cffd5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302146604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.302146604
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.270601862
Short name T47
Test name
Test status
Simulation time 170101268117 ps
CPU time 233.14 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:08:00 PM PDT 24
Peak memory 201820 kb
Host smart-a7369c86-90c9-46d5-bad9-48361c6a57ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=270601862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.270601862
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.652817489
Short name T532
Test name
Test status
Simulation time 164690340402 ps
CPU time 387.9 seconds
Started Mar 28 01:04:08 PM PDT 24
Finished Mar 28 01:10:36 PM PDT 24
Peak memory 201920 kb
Host smart-8ac2ddd7-4709-468c-a6a9-33532e18adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652817489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.652817489
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3330098288
Short name T609
Test name
Test status
Simulation time 333580918885 ps
CPU time 199.22 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:07:24 PM PDT 24
Peak memory 201904 kb
Host smart-383a81a0-2a47-408f-91de-1400a7958f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330098288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3330098288
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2431278778
Short name T717
Test name
Test status
Simulation time 377632352365 ps
CPU time 477.09 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:12:02 PM PDT 24
Peak memory 201968 kb
Host smart-3b47439d-8cea-4d31-b33d-c5fbaf06afba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431278778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2431278778
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.35138420
Short name T688
Test name
Test status
Simulation time 202256321809 ps
CPU time 102.61 seconds
Started Mar 28 01:04:04 PM PDT 24
Finished Mar 28 01:05:47 PM PDT 24
Peak memory 201860 kb
Host smart-380f860e-446b-4b49-b062-a7b7781a7dc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35138420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.ad
c_ctrl_filters_wakeup_fixed.35138420
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2556727018
Short name T337
Test name
Test status
Simulation time 102612869309 ps
CPU time 547.51 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:13:14 PM PDT 24
Peak memory 202156 kb
Host smart-d0e04735-c67e-42f7-827e-6b5a33426138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556727018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2556727018
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2065027383
Short name T528
Test name
Test status
Simulation time 38298262973 ps
CPU time 23.09 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:04:28 PM PDT 24
Peak memory 201712 kb
Host smart-31a83507-b6e1-4b85-9a83-b62c5675e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065027383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2065027383
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.430453094
Short name T730
Test name
Test status
Simulation time 5495191431 ps
CPU time 7.29 seconds
Started Mar 28 01:04:05 PM PDT 24
Finished Mar 28 01:04:12 PM PDT 24
Peak memory 201628 kb
Host smart-cf63d58b-6791-4f08-825b-787773fa8b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430453094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.430453094
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3075061827
Short name T545
Test name
Test status
Simulation time 5749609850 ps
CPU time 8.16 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:04:14 PM PDT 24
Peak memory 201712 kb
Host smart-6a4d4662-5288-40b3-a672-3d85ab637e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075061827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3075061827
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3733919620
Short name T671
Test name
Test status
Simulation time 83637434255 ps
CPU time 199.48 seconds
Started Mar 28 01:04:06 PM PDT 24
Finished Mar 28 01:07:26 PM PDT 24
Peak memory 201664 kb
Host smart-b902c2e5-6823-421f-a94b-5bd674a661e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733919620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3733919620
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.569533843
Short name T627
Test name
Test status
Simulation time 29360740459 ps
CPU time 82.58 seconds
Started Mar 28 01:04:02 PM PDT 24
Finished Mar 28 01:05:25 PM PDT 24
Peak memory 210520 kb
Host smart-28442a2c-84c6-48c4-b5ba-2f2687369afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569533843 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.569533843
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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