Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6734	1			T3	44		T7	52		T48	60
testmodes[AdcCtrlTestmodeNormal]	5547	1			T1	1		T2	3		T3	47
testmodes[AdcCtrlTestmodeLowpower]	5534	1			T1	1		T3	39		T7	54
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3518	1			T3	13		T7	19		T48	35
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1776	1			T3	15		T7	17		T48	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1329	1			T3	15		T7	16		T48	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1796	1			T3	17		T7	15		T48	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2060	1			T2	2		T3	17		T7	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1351	1			T3	13		T7	16		T12	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1309	1			T3	13		T7	17		T48	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1373	1			T1	1		T3	15		T7	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2603	1			T3	11		T7	22		T48	17