Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22294

1

T1

16

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3941

1

T1

23

T2

2

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20267

1

T1

23

T2

2

T3

130

auto[1]

5968

1

T1

16

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T108	12		T206	1		-	-
values[0]	46	1			T149	6		T143	1		T207	1
values[1]	690	1			T56	25		T156	9		T147	13
values[2]	2827	1			T2	1		T5	11		T9	29
values[3]	789	1			T134	17		T208	1		T209	12
values[4]	773	1			T139	15		T96	1		T72	20
values[5]	640	1			T12	11		T60	16		T71	11
values[6]	680	1			T1	23		T49	8		T210	1
values[7]	732	1			T1	16		T2	1		T6	18
values[8]	803	1			T2	1		T12	15		T59	11
values[9]	1362	1			T12	16		T49	6		T64	7
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	941	1			T56	12		T156	9		T147	13
values[1]	2863	1			T2	1		T5	11		T9	29
values[2]	682	1			T134	17		T139	15		T96	1
values[3]	766	1			T12	11		T50	19		T72	20
values[4]	655	1			T60	16		T71	11		T210	1
values[5]	588	1			T1	23		T2	1		T49	8
values[6]	854	1			T1	16		T6	18		T8	1
values[7]	857	1			T2	1		T12	15		T64	25
values[8]	899	1			T49	6		T135	22		T143	1
values[9]	248	1			T12	16		T135	19		T29	9
minimum	16882	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T56	12		T147	1		T72	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T156	1		T152	10		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T2	1		T5	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T56	13		T208	1		T209	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	9		T52	3		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T139	1		T96	1		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T141	10		T157	1		T41	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	11		T50	12		T72	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	8		T51	2		T211	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T71	3		T210	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	2		T135	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	12		T2	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	13		T6	9		T59	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	1		T48	2		T140	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	13		T99	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T64	25		T147	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T135	11		T158	17		T212	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T49	4		T143	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T108	1		T213	15		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T12	12		T135	11		T29	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T208	1		T51	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	12		T72	10		T149	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T156	8		T215	8		T191	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T5	10		T9	26		T10	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	27		T216	8		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T134	8		T141	9		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	14		T99	8		T215	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	13		T157	13		T43	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T50	7		T72	9		T27	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T60	8		T51	8		T107	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T71	8		T157	16		T191	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	6		T135	12		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	11		T139	12		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	3		T6	9		T53	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T140	11		T141	6		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	2		T99	9		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T147	13		T140	13		T215	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T135	11		T158	15		T43	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	2		T40	11		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T108	11		T213	13		T214	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T12	4		T135	8		T29	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T108	1		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T149	1		T143	1		T207	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T218	1		T219	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T56	12		T147	1		T144	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T56	13		T156	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T2	1		T5	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T99	1		T142	15		T191	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T134	9		T51	13		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T208	1		T209	12		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T141	10		T143	1		T41	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T139	1		T96	1		T72	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	8		T51	2		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	11		T71	3		T50	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	2		T135	12		T150	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	12		T210	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	13		T6	9		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T8	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	13		T59	11		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T64	18		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T135	11		T158	17		T212	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T12	12		T49	4		T64	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T108	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T149	5		T220	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T218	10		T219	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T147	12		T144	12		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T156	8		T215	8		T221	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T5	10		T9	26		T10	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	14		T191	21		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T134	8		T51	12		T72	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T99	8		T215	14		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T141	13		T43	6		T222	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T139	14		T72	9		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T60	8		T51	8		T157	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T71	8		T50	7		T157	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	6		T135	12		T29	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	11		T51	3		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	3		T6	9		T53	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	12		T140	24		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T99	9		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T147	11		T141	6		T215	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T135	11		T158	15		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	4		T49	2		T135	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T56	1		T147	13		T72	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T156	9		T152	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T2	1		T5	11		T9	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T56	1		T208	1		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T134	9		T52	2		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	15		T96	1		T99	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	14		T157	14		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	1		T50	16		T72	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T60	9		T51	10		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T71	9		T210	1		T157	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	8		T135	13		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	12		T2	1		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	4		T6	10		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T8	1		T48	2		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	3		T99	10		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T64	2		T147	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T135	12		T158	17		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T49	5		T143	1		T40	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T108	12		T213	14		T214	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T12	5		T135	9		T29	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T208	1		T51	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T56	11		T72	11		T144	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T152	9		T215	8		T191	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T63	29		T134	7		T223	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T56	12		T209	11		T142	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T134	8		T52	1		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T215	11		T158	2		T224	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	9		T41	14		T43	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	10		T50	3		T72	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T60	7		T211	12		T107	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T71	2		T211	14		T45	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	11		T29	3		T163	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	11		T152	8		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	12		T6	8		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T140	2		T209	7		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	12		T154	7		T225	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T64	23		T140	14		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T135	10		T158	15		T212	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	1		T35	11		T226	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T213	14		T202	15		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T12	11		T135	10		T29	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T108	12		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T149	6		T143	1		T207	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T218	11		T219	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	1		T147	13		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T56	1		T156	9		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T2	1		T5	11		T9	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T99	1		T142	15		T191	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T134	9		T51	16		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T208	1		T209	1		T99	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T141	14		T143	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T139	15		T96	1		T72	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T60	9		T51	10		T157	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T71	9		T50	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	8		T135	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	12		T210	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	4		T6	10		T53	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	1		T8	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	3		T59	1		T99	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	1		T64	1		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T135	12		T158	17		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T12	5		T49	5		T64	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T56	11		T144	6		T154	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T56	12		T152	9		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T63	29		T134	7		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	14		T191	18		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	8		T51	9		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T209	11		T215	11		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T141	9		T41	14		T43	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T72	10		T29	7		T228	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T60	7		T107	16		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	10		T71	2		T50	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T135	11		T150	8		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	11		T152	8		T51	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	12		T6	8		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T140	16		T209	7		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	12		T59	10		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T64	17		T141	11		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T135	10		T158	15		T212	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	11		T49	1		T64	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22778

1

T1

23

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3457

1

T1

16

T2

2

T12

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20098

1

T1

23

T2

2

T3

130

auto[1]

6137

1

T1

16

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T209	12		T206	1		-	-
values[0]	54	1			T230	13		T168	1		T181	1
values[1]	715	1			T64	18		T139	15		T156	9
values[2]	695	1			T1	16		T6	18		T71	11
values[3]	694	1			T1	23		T48	1		T49	8
values[4]	661	1			T59	11		T64	7		T135	22
values[5]	881	1			T2	1		T60	16		T156	1
values[6]	693	1			T2	1		T134	16		T140	14
values[7]	596	1			T12	15		T48	1		T134	17
values[8]	3189	1			T5	11		T9	29		T10	32
values[9]	1164	1			T2	1		T8	1		T12	27
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T1	16		T64	18		T71	11
values[1]	699	1			T48	1		T49	8		T135	24
values[2]	743	1			T1	23		T6	18		T135	22
values[3]	632	1			T59	11		T64	7		T51	25
values[4]	893	1			T2	2		T60	16		T134	16
values[5]	596	1			T48	1		T135	19		T140	14
values[6]	3035	1			T5	11		T9	29		T10	32
values[7]	903	1			T56	25		T134	17		T152	9
values[8]	754	1			T2	1		T8	1		T12	11
values[9]	195	1			T12	16		T154	14		T170	4
minimum	16906	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T71	3		T139	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	13		T64	18		T147	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	1		T153	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T49	2		T135	12		T162	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	12		T6	9		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	11		T140	15		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T59	11		T64	7		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	13		T150	10		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T134	8		T156	1		T152	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	2		T60	8		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T135	11		T51	1		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	1		T140	3		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T5	1		T9	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T215	21		T143	1		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T56	25		T152	9		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T134	9		T209	8		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T8	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	11		T49	4		T209	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T12	12		T170	1		T38	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T154	7		T230	5		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16722	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T24	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T71	8		T139	12		T156	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	3		T147	13		T72	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T221	12		T31	11		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	6		T135	12		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	11		T6	9		T51	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T135	11		T140	13		T141	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T141	9		T40	11		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	12		T144	12		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T134	8		T72	9		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T60	8		T159	7		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T135	8		T215	15		T43	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	11		T233	12		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T5	10		T9	26		T10	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T215	22		T217	12		T29	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T99	9		T191	21		T154	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	8		T142	14		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	12		T157	16		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	2		T51	3		T99	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T12	4		T170	3		T38	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T154	7		T231	7		T234	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	1		T60	1		T49	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T209	12		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T168	1		T181	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T230	1		T236	1		T237	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T139	1		T156	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T64	18		T147	1		T72	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	9		T71	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	13		T135	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	12		T48	1		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	2		T140	15		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T59	11		T64	7		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T135	11		T51	13		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T156	1		T152	10		T72	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T60	8		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T134	8		T51	1		T53	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	1		T140	3		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	13		T135	11		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	1		T134	9		T215	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1687	1			T5	1		T9	3		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T209	8		T96	1		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T2	1		T8	1		T12	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T12	11		T49	4		T51	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T230	12		T237	19		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T139	14		T156	8		T72	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T147	11		T72	10		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	9		T71	8		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T1	3		T135	12		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	11		T51	8		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	6		T140	13		T157	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T141	9		T34	11		T27	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	11		T51	12		T141	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T72	9		T155	9		T40	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T60	8		T154	8		T232	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T134	8		T53	4		T215	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T140	11		T233	12		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	2		T135	8		T141	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	8		T215	22		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T5	10		T9	26		T10	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T142	14		T191	1		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	4		T99	9		T191	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T49	2		T51	3		T99	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3