Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22752

1

T1

23

T2

2

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3483

1

T1

16

T2

1

T12

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20152

1

T1

23

T2

1

T3

130

auto[1]

6083

1

T1

16

T2

2

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	245	1			T2	1		T12	16		T51	7
values[0]	21	1			T235	1		T236	1		T237	19
values[1]	695	1			T64	18		T139	15		T156	9
values[2]	797	1			T1	16		T6	18		T71	11
values[3]	573	1			T1	23		T48	1		T49	8
values[4]	743	1			T59	11		T64	7		T135	22
values[5]	866	1			T2	2		T60	16		T156	1
values[6]	691	1			T134	16		T140	14		T51	1
values[7]	598	1			T12	15		T48	1		T134	17
values[8]	3162	1			T5	11		T9	29		T10	32
values[9]	964	1			T8	1		T12	11		T49	6
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	635	1			T1	16		T64	18		T71	11
values[1]	723	1			T6	18		T48	1		T135	24
values[2]	706	1			T1	23		T49	8		T135	22
values[3]	726	1			T59	11		T64	7		T51	25
values[4]	885	1			T2	2		T60	16		T134	16
values[5]	547	1			T48	1		T135	19		T140	14
values[6]	3030	1			T5	11		T9	29		T10	32
values[7]	916	1			T56	25		T147	13		T152	9
values[8]	827	1			T2	1		T8	1		T12	27
values[9]	99	1			T154	14		T170	4		T230	5
minimum	17141	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T71	3		T139	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	13		T64	18		T147	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	9		T48	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T135	12		T162	12		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	12		T51	2		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T49	2		T135	11		T140	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T59	11		T64	7		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T51	13		T150	10		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T2	1		T134	8		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T60	8		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T135	11		T51	1		T53	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T48	1		T140	3		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T5	1		T9	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	9		T215	21		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T56	25		T147	1		T152	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T209	8		T96	1		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T8	1		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	11		T49	4		T209	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T170	1		T38	15		T294	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T154	7		T230	5		T234	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16837	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T149	1		T212	7		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T71	8		T139	12		T156	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	3		T147	13		T72	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	9		T31	11		T216	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T135	12		T162	11		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	11		T51	8		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	6		T135	11		T140	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T141	9		T40	11		T27	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T51	12		T144	12		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T134	8		T72	9		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T60	8		T159	7		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T135	8		T53	4		T215	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T140	11		T233	12		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T5	10		T9	26		T10	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	8		T215	22		T217	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T147	12		T99	9		T191	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	14		T191	1		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	4		T217	12		T242	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T49	2		T51	3		T99	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T170	3		T38	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T154	7		T234	5		T261	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T149	9		T237	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T2	1		T12	12		T217	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T51	4		T154	7		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T235	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T236	1		T237	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T139	1		T156	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T64	18		T147	1		T72	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	9		T71	3		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	13		T135	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	12		T48	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	2		T52	3		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T59	11		T64	7		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	11		T140	15		T51	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	1		T156	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T60	8		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T134	8		T51	1		T53	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T140	3		T47	1		T233	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	13		T135	11		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	1		T134	9		T215	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1708	1			T5	1		T9	3		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T209	8		T96	1		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T8	1		T210	1		T152	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	11		T49	4		T209	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T12	4		T217	12		T38	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T51	3		T154	7		T155	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T237	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T139	14		T156	8		T72	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T147	11		T72	10		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	9		T71	8		T139	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	3		T135	12		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T1	11		T149	5		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	6		T157	15		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T51	8		T141	9		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	11		T140	13		T51	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T72	9		T155	9		T40	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T60	8		T154	8		T232	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T134	8		T53	4		T215	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	11		T233	12		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	2		T135	8		T141	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	8		T215	22		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T5	10		T9	26		T10	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T142	14		T191	1		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T99	9		T191	21		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T49	2		T99	8		T157	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T71	9		T139	13		T156	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	4		T64	1		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	10		T48	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	13		T162	12		T217	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	12		T51	10		T149	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T49	8		T135	12		T140	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	1		T64	1		T141	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T51	16		T150	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	1		T134	9		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T60	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T135	9		T51	1		T53	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	1		T140	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T5	11		T9	29		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T134	9		T215	24		T217	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T56	2		T147	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T209	1		T96	1		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T8	1		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	1		T49	5		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T170	4		T38	17		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T154	8		T230	1		T234	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16984	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T149	10		T212	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T71	2		T50	3		T158	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T1	12		T64	17		T72	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	8		T166	12		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T135	11		T162	11		T212	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	11		T150	8		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	10		T140	14		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T59	10		T64	6		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	9		T150	9		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T134	7		T152	9		T72	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T60	7		T240	11		T241	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T135	10		T53	1		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T140	2		T233	7		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T12	12		T63	29		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T134	8		T215	19		T29	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T56	23		T152	8		T191	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T209	7		T142	14		T238	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	11		T211	12		T224	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	10		T49	1		T209	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T38	14		T294	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T154	6		T230	4		T234	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T24	7		T29	7		T280	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T212	6		T229	7		T180	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T2	1		T12	5		T217	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T51	4		T154	8		T155	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T235	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T236	1		T237	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T139	15		T156	9		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T64	1		T147	12		T72	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	10		T71	9		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	4		T135	13		T147	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	12		T48	1		T149	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	8		T52	2		T157	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T59	1		T64	1		T51	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T135	12		T140	14		T51	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	1		T156	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T60	9		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T134	9		T51	1		T53	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T140	12		T47	1		T233	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	3		T135	9		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	1		T134	9		T215	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T5	11		T9	29		T10	32
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T209	1		T96	1		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T210	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T12	1		T49	5		T209	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T12	11		T38	14		T295	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T51	3		T154	6		T155	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T237	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	2		T155	9		T24	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T64	17		T72	11		T212	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	8		T71	2		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	12		T135	11		T211	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	11		T150	8		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T52	1		T158	6		T279	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T59	10		T64	6		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	10		T140	14		T51	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T152	9		T72	10		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T60	7		T246	7		T241	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	7		T53	1		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T140	2		T233	7		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	12		T135	10		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T134	8		T215	19		T29	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T56	23		T63	29		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T209	7		T142	14		T238	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T152	8		T191	18		T211	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	10		T49	1		T209	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33