Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22265

1

T1

16

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3970

1

T1

23

T2

2

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20290

1

T1

23

T2

2

T3

130

auto[1]

5945

1

T1

16

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	228	1			T12	16		T143	1		T24	8
values[0]	45	1			T51	1		T149	6		T143	1
values[1]	624	1			T56	25		T156	9		T147	13
values[2]	2917	1			T2	1		T5	11		T9	29
values[3]	780	1			T134	17		T209	12		T51	25
values[4]	797	1			T12	11		T139	15		T96	1
values[5]	618	1			T60	16		T71	11		T50	19
values[6]	624	1			T1	23		T2	1		T49	8
values[7]	719	1			T1	16		T6	18		T8	1
values[8]	898	1			T2	1		T12	15		T59	11
values[9]	1105	1			T49	6		T64	7		T135	41
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	625	1			T56	25		T147	13		T208	1
values[1]	2904	1			T2	1		T5	11		T9	29
values[2]	714	1			T134	17		T139	15		T141	12
values[3]	789	1			T12	11		T50	19		T96	1
values[4]	628	1			T60	16		T71	11		T51	10
values[5]	586	1			T1	23		T2	1		T49	8
values[6]	832	1			T1	16		T6	18		T8	1
values[7]	840	1			T2	1		T12	15		T64	25
values[8]	1058	1			T49	6		T135	41		T147	12
values[9]	129	1			T12	16		T163	23		T108	12
minimum	17130	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T56	12		T147	1		T72	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T56	13		T208	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	1		T5	1		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T208	1		T209	12		T142	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T134	9		T141	3		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T139	1		T215	12		T158	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T141	10		T157	1		T41	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	11		T50	12		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T60	8		T51	2		T211	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T71	3		T157	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	2		T135	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	12		T2	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	13		T6	9		T59	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	1		T48	2		T140	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	13		T99	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T64	25		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T135	11		T158	17		T212	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T49	4		T135	11		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T108	1		T214	1		T202	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	12		T163	12		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16745	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T156	1		T152	10		T51	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T147	12		T72	10		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T191	21		T221	12		T155	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T5	10		T9	26		T10	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	27		T155	13		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	8		T141	9		T165	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T139	14		T215	14		T158	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T141	13		T157	13		T43	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	7		T99	8		T72	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T60	8		T51	8		T107	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T71	8		T157	16		T191	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	6		T135	12		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	11		T139	12		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	3		T6	9		T53	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T140	11		T141	6		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T99	9		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T147	2		T140	13		T215	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T135	11		T158	15		T43	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T49	2		T135	8		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T108	11		T214	4		T202	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T12	4		T163	11		T179	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T156	8		T215	8		T154	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T24	8		T108	1		T296	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	12		T143	1		T29	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T149	1		T143	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T51	1		T218	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T56	12		T147	1		T144	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T56	13		T156	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T2	1		T5	1		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T208	1		T99	1		T142	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T134	9		T51	13		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T209	12		T99	1		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T141	10		T157	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	11		T139	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	8		T51	2		T211	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T71	3		T50	12		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	2		T135	12		T29	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	12		T2	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	13		T6	9		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	1		T48	2		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	13		T59	11		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	1		T64	18		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T135	11		T158	17		T212	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T49	4		T64	7		T135	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T108	11		T240	13		T297	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T12	4		T29	3		T163	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T149	5		T220	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T218	10		T219	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T147	12		T144	12		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T156	8		T215	8		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T5	10		T9	26		T10	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T142	27		T191	21		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T134	8		T51	12		T141	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T99	8		T215	14		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T141	13		T157	13		T43	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T139	14		T72	9		T29	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T60	8		T51	8		T107	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T71	8		T50	7		T157	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	6		T135	12		T29	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	11		T51	3		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	3		T6	9		T53	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	12		T140	11		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	2		T99	9		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T147	11		T140	13		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T135	11		T158	15		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	2		T135	8		T147	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T56	1		T147	13		T72	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T56	1		T208	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	1		T5	11		T9	29
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T208	1		T209	1		T142	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T134	9		T141	10		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	15		T215	15		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	14		T157	14		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T50	16		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T60	9		T51	10		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T71	9		T157	17		T191	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	8		T135	13		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	12		T2	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	4		T6	10		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T8	1		T48	2		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	3		T99	10		T149	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T64	2		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T135	12		T158	17		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T49	5		T135	9		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T108	12		T214	5		T202	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T12	5		T163	12		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16920	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T156	9		T152	1		T51	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T56	11		T72	11		T144	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T56	12		T191	18		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T63	29		T134	7		T223	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T209	11		T142	23		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T134	8		T141	2		T165	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T215	11		T158	2		T224	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	9		T41	14		T43	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	10		T50	3		T72	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T60	7		T211	12		T107	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T71	2		T211	14		T45	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	11		T29	3		T163	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	11		T152	8		T209	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	12		T6	8		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T140	2		T141	11		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	12		T154	7		T225	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T64	23		T140	14		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T135	10		T158	15		T212	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	1		T135	10		T29	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T202	15		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T12	11		T163	11		T179	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T34	3		T286	5		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T152	9		T215	8		T155	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T24	1		T108	12		T296	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	5		T143	1		T29	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T149	6		T143	1		T220	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T51	1		T218	11		T219	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T56	1		T147	13		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T56	1		T156	9		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	1		T5	11		T9	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T208	1		T99	1		T142	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T134	9		T51	16		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T209	1		T99	9		T215	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	14		T157	14		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	1		T139	15		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	9		T51	10		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T71	9		T50	16		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T49	8		T135	13		T29	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	12		T2	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	4		T6	10		T53	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T48	2		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	3		T59	1		T99	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T2	1		T64	1		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T135	12		T158	17		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T49	5		T64	1		T135	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T24	7		T240	12		T299	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T12	11		T29	5		T163	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T56	11		T144	6		T154	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	12		T152	9		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T63	29		T134	7		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	23		T191	18		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T134	8		T51	9		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T209	11		T215	11		T158	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T141	9		T41	14		T43	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	10		T72	10		T29	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T60	7		T211	12		T107	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T71	2		T50	3		T211	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T135	11		T29	3		T163	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	11		T152	8		T51	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	12		T6	8		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T140	2		T209	7		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	12		T59	10		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T64	17		T140	14		T141	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T135	10		T158	15		T212	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T49	1		T64	6		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33