Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20313

1

T1

16

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

5922

1

T1

23

T2

2

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20269

1

T2

2

T3

130

T6

18

auto[1]

5966

1

T1

39

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T27	13		T300	12		T248	6
values[0]	32	1			T301	1		T160	9		T302	7
values[1]	746	1			T12	15		T48	1		T152	10
values[2]	687	1			T1	23		T2	1		T60	16
values[3]	440	1			T64	7		T147	3		T51	1
values[4]	882	1			T139	15		T135	22		T147	12
values[5]	652	1			T56	13		T156	9		T221	13
values[6]	860	1			T1	16		T2	1		T8	1
values[7]	723	1			T56	12		T59	11		T147	13
values[8]	681	1			T2	1		T12	16		T49	8
values[9]	3621	1			T5	11		T6	18		T9	29
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935	1			T1	23		T12	15		T48	1
values[1]	3002	1			T2	1		T5	11		T9	29
values[2]	494	1			T64	7		T135	22		T72	2
values[3]	832	1			T139	15		T147	15		T208	1
values[4]	674	1			T2	1		T56	13		T156	9
values[5]	816	1			T1	16		T8	1		T135	24
values[6]	705	1			T2	1		T12	16		T56	12
values[7]	757	1			T49	8		T64	18		T210	1
values[8]	901	1			T6	18		T48	1		T49	6
values[9]	231	1			T12	11		T140	28		T184	1
minimum	16888	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T12	13		T152	10		T51	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	12		T48	1		T141	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T60	8		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1519	1			T5	1		T9	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T144	7		T283	1		T228	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T64	7		T135	11		T72	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T147	1		T34	4		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	1		T147	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	13		T155	3		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T156	1		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	13		T187	1		T154	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T8	1		T135	12		T72	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	12		T147	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T56	12		T59	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T210	1		T156	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T49	2		T64	18		T209	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	9		T48	1		T49	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T139	1		T50	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	11		T155	10		T43	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T140	15		T184	1		T211	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T47	1		T302	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	2		T51	3		T191	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	11		T141	15		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T60	8		T134	8		T51	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1017	1			T5	10		T9	26		T10	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T144	12		T228	14		T252	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T135	11		T72	1		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T147	2		T34	3		T254	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	14		T147	11		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T155	8		T31	11		T226	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T156	8		T142	13		T43	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	3		T154	7		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T135	12		T72	9		T191	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	4		T147	12		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T135	8		T99	8		T109	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T157	15		T158	11		T29	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T49	6		T53	4		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	9		T49	2		T71	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	12		T50	7		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T155	13		T43	8		T27	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T140	13		T158	6		T217	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T27	1		T300	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T248	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T301	1		T160	5		T303	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T302	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	13		T152	10		T51	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	1		T141	15		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T60	8		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	12		T51	13		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	1		T51	1		T52	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T64	7		T143	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T144	7		T34	4		T28	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T139	1		T135	11		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	13		T14	3		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T156	1		T221	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	13		T154	7		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T2	1		T8	1		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T147	1		T215	21		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T56	12		T59	11		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	12		T210	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T49	2		T135	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T6	9		T12	11		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1720	1			T5	1		T9	3		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T27	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T248	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T160	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	2		T51	3		T191	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T141	15		T217	10		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T60	8		T134	8		T51	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	11		T51	12		T154	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	2		T108	10		T252	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T163	2		T165	3		T286	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T144	12		T34	3		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T139	14		T135	11		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T254	6		T238	13		T109	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T156	8		T221	12		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	3		T154	7		T155	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T135	12		T191	21		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T147	12		T215	22		T157	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T72	9		T109	4		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T12	4		T149	5		T29	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T49	6		T135	8		T99	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T6	9		T49	2		T71	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1180	1			T5	10		T9	26		T10	29
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	3		T152	1		T51	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	12		T48	1		T141	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	1		T60	9		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1359	1			T5	11		T9	29		T10	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T144	13		T283	1		T228	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T64	1		T135	12		T72	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T147	3		T34	4		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	15		T147	12		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	1		T155	9		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T156	9		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	4		T187	1		T154	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	1		T135	13		T72	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	5		T147	13		T149	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	1		T56	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T210	1		T156	1		T157	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T49	8		T64	1		T209	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T6	10		T48	1		T49	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T139	13		T50	16		T149	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	1		T155	14		T43	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T140	14		T184	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T47	1		T302	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	12		T152	9		T51	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	11		T141	13		T212	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T60	7		T134	8		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1177	1			T63	29		T223	14		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	6		T228	12		T252	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T64	6		T135	10		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	3		T254	2		T247	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T152	8		T155	9		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T56	12		T155	2		T226	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	9		T142	9		T43	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	12		T154	6		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T135	11		T72	10		T191	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	11		T215	19		T45	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	11		T59	10		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T158	11		T29	8		T233	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T64	17		T209	18		T53	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	8		T49	1		T71	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	3		T150	8		T269	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T12	10		T155	9		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	14		T211	14		T158	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T27	13		T300	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T248	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T301	1		T160	5		T303	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T302	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	3		T152	1		T51	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	1		T141	17		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	1		T60	9		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	12		T51	16		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T147	3		T51	1		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T64	1		T143	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T144	13		T34	4		T28	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T139	15		T135	12		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	1		T14	3		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T156	9		T221	13		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	4		T154	8		T155	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T2	1		T8	1		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T147	13		T215	24		T157	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T56	1		T59	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	5		T210	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T2	1		T49	8		T135	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T6	10		T12	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1562	1			T5	11		T9	29		T10	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T160	4		T304	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	12		T152	9		T51	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	13		T212	16		T224	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	7		T134	8		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	11		T51	9		T154	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T52	1		T252	11		T104	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T64	6		T165	3		T286	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T144	6		T34	3		T247	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T135	10		T152	8		T142	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T56	12		T254	2		T238	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T155	9		T43	7		T29	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	12		T154	6		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T135	11		T150	9		T191	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T215	19		T158	11		T45	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T56	11		T59	10		T72	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	11		T29	8		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T135	10		T209	18		T53	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T6	8		T12	10		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T63	29		T64	17		T223	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33