Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22585

1

T1

39

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3650

1

T2

2

T8

1

T12

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20292

1

T1

39

T2

1

T3

130

auto[1]

5943

1

T2

2

T5

11

T9

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T158	5		T305	16		T206	1
values[0]	57	1			T255	7		T282	20		T218	11
values[1]	757	1			T2	1		T59	11		T135	19
values[2]	705	1			T134	16		T156	9		T147	13
values[3]	634	1			T2	1		T56	13		T209	12
values[4]	602	1			T12	11		T56	12		T135	22
values[5]	3005	1			T2	1		T5	11		T9	29
values[6]	799	1			T1	16		T64	18		T134	17
values[7]	707	1			T1	23		T6	18		T49	14
values[8]	882	1			T48	1		T64	7		T139	15
values[9]	1185	1			T8	1		T12	15		T60	16
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	860	1			T2	1		T59	11		T135	19
values[1]	701	1			T2	1		T134	16		T147	13
values[2]	676	1			T56	25		T156	9		T52	3
values[3]	2920	1			T5	11		T9	29		T10	32
values[4]	837	1			T1	16		T2	1		T135	24
values[5]	631	1			T12	16		T49	6		T64	18
values[6]	860	1			T1	23		T6	18		T49	8
values[7]	793	1			T48	1		T64	7		T140	28
values[8]	884	1			T8	1		T12	15		T71	11
values[9]	146	1			T60	16		T269	6		T225	19
minimum	16927	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	12		T141	12		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	1		T59	11		T135	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T147	1		T142	1		T211	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T134	8		T209	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T56	25		T99	2		T212	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T156	1		T52	3		T286	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T5	1		T9	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	11		T210	1		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	13		T2	1		T135	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T157	1		T150	9		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	12		T134	9		T152	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	4		T64	18		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	12		T6	9		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	1		T140	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	1		T215	12		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T48	1		T64	7		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T12	13		T71	3		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T139	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T225	9		T111	5		T239	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T60	8		T269	6		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16725	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T99	1		T279	1		T306	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	7		T141	6		T158	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T135	8		T147	11		T155	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T147	12		T29	3		T109	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	8		T51	12		T27	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T99	9		T307	13		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T156	8		T286	1		T246	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T5	10		T9	26		T10	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T215	15		T279	15		T228	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	3		T135	12		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T157	16		T233	12		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	4		T134	8		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T49	2		T144	12		T158	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	11		T6	9		T49	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T139	14		T140	11		T157	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T72	1		T215	14		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	13		T72	10		T43	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	2		T71	8		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T139	12		T147	2		T72	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T225	10		T111	5		T186	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T60	8		T231	9		T308	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T99	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T305	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T158	3		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T255	5		T218	1		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	9		T310	1		T288	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	12		T141	12		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T59	11		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T147	1		T184	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T134	8		T156	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T56	13		T51	2		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T209	12		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T56	12		T135	11		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	11		T52	3		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T2	1		T5	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T210	1		T157	1		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	13		T134	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T64	18		T208	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	12		T6	9		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	4		T157	1		T158	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	1		T215	12		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T48	1		T64	7		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T12	13		T71	3		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T8	1		T60	8		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T305	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T158	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T255	2		T218	10		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	11		T288	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	7		T141	6		T154	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T135	8		T147	11		T99	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T147	12		T34	11		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	8		T156	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T51	8		T29	3		T307	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T226	11		T311	10		T170	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T135	11		T99	9		T274	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T215	15		T279	15		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T5	10		T9	26		T10	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T157	16		T233	12		T280	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	3		T134	8		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	12		T35	11		T169	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	11		T6	9		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	2		T157	13		T158	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T72	1		T215	14		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T139	14		T140	24		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	2		T71	8		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T60	8		T139	12		T147	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	16		T141	7		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	1		T59	1		T135	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	13		T142	1		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T134	9		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T56	2		T99	11		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T156	9		T52	2		T286	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T5	11		T9	29		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T210	1		T215	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	4		T2	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T157	17		T150	1		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	5		T134	9		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	5		T64	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	12		T6	10		T49	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T139	15		T140	12		T157	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T72	2		T215	15		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	1		T64	1		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T12	3		T71	9		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	1		T139	13		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T225	11		T111	9		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T60	9		T269	1		T231	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16891	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T99	9		T279	1		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T50	3		T141	11		T150	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T59	10		T135	10		T155	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T211	14		T29	5		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	7		T209	11		T51	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T56	23		T212	6		T41	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	1		T286	5		T246	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T63	29		T223	14		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	10		T215	11		T279	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	12		T135	11		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	8		T233	7		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	11		T134	8		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	1		T64	17		T144	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	11		T6	8		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	2		T155	9		T224	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T215	11		T142	14		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T64	6		T140	14		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	12		T71	2		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T72	10		T211	12		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T225	8		T111	1		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T60	7		T269	5		T308	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T154	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T306	18		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T305	16		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T158	3		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T255	5		T218	11		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T282	12		T310	1		T288	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	16		T141	7		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T59	1		T135	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	13		T184	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T134	9		T156	9		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	1		T51	10		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	1		T209	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	1		T135	12		T99	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T52	2		T215	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T2	1		T5	11		T9	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T210	1		T157	17		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	4		T134	9		T149	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T64	1		T208	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	12		T6	10		T49	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T49	5		T157	14		T158	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T72	2		T215	15		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T48	1		T64	1		T139	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T12	3		T71	9		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T8	1		T60	9		T139	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T158	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T255	2		T33	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T282	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	3		T141	11		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T59	10		T135	10		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T211	14		T34	11		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	7		T51	9		T247	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T56	12		T212	6		T41	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T209	11		T226	10		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	11		T135	10		T274	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	10		T52	1		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T12	11		T63	29		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T233	7		T280	9		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T134	8		T292	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T64	17		T150	8		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	11		T6	8		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T49	1		T158	4		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T215	11		T142	14		T34	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T64	6		T140	16		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	12		T71	2		T51	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T60	7		T72	21		T211	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33