Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22533

1

T1

16

T2

2

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3702

1

T1

23

T2

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20318

1

T1

16

T2

2

T3

130

auto[1]

5917

1

T1

23

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T139	13		T147	3		T51	8
values[0]	78	1			T282	20		T299	25		T33	9
values[1]	713	1			T2	1		T59	11		T135	19
values[2]	698	1			T134	16		T156	9		T147	13
values[3]	634	1			T2	1		T56	13		T209	12
values[4]	651	1			T12	11		T56	12		T210	1
values[5]	2996	1			T2	1		T5	11		T9	29
values[6]	801	1			T1	16		T64	18		T134	17
values[7]	700	1			T1	23		T49	14		T139	15
values[8]	885	1			T6	18		T48	1		T64	7
values[9]	917	1			T8	1		T12	15		T60	16
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	701	1			T135	19		T147	12		T50	19
values[1]	722	1			T2	1		T134	16		T156	9
values[2]	659	1			T56	25		T52	3		T99	11
values[3]	2949	1			T5	11		T9	29		T10	32
values[4]	884	1			T1	16		T2	1		T12	16
values[5]	568	1			T49	6		T64	18		T134	17
values[6]	831	1			T1	23		T6	18		T49	8
values[7]	801	1			T48	1		T64	7		T156	1
values[8]	940	1			T8	1		T12	15		T71	11
values[9]	109	1			T60	16		T29	16		T269	6
minimum	17071	1			T2	1		T3	130		T7	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T141	12		T184	1		T150	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T135	11		T147	1		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T147	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	8		T156	1		T209	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	13		T99	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T56	12		T52	3		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T5	1		T9	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	11		T210	1		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	13		T2	1		T12	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T157	1		T150	9		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	4		T64	18		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T208	1		T144	7		T158	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	9		T49	2		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	12		T139	1		T140	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T209	8		T72	1		T215	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T48	1		T64	7		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T12	13		T71	3		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T139	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T60	8		T239	11		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T29	8		T269	6		T225	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16756	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T2	1		T59	11		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T141	6		T158	17		T34	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	8		T147	11		T50	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T147	12		T29	3		T247	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T134	8		T156	8		T51	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T99	9		T307	13		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T286	1		T262	13		T246	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T5	10		T9	26		T10	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T215	15		T163	11		T279	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	3		T12	4		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T157	16		T31	10		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	2		T134	8		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	12		T158	4		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	9		T49	6		T157	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	11		T139	14		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T72	1		T215	14		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	13		T72	10		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	2		T71	8		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	12		T147	2		T72	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T60	8		T186	8		T260	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T29	8		T225	2		T312	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T154	10		T155	8		T282	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T51	4		T149	1		T155	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T139	1		T147	1		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T33	6		T313	10		T314	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T282	9		T299	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T141	12		T150	10		T158	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T59	11		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T147	1		T184	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T134	8		T156	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	1		T56	13		T41	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T209	12		T99	1		T212	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T135	11		T51	2		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	11		T56	12		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T2	1		T5	1		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T157	1		T14	3		T233	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	13		T64	18		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	9		T144	7		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	6		T53	4		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	12		T139	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	9		T209	8		T72	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T48	1		T64	7		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	13		T60	8		T71	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T96	1		T72	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T51	3		T155	9		T233	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T139	12		T147	2		T158	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T33	3		T313	7		T314	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T282	11		T299	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T141	6		T158	17		T27	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T135	8		T147	11		T50	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T147	12		T34	11		T247	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	8		T156	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T29	3		T307	13		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T226	11		T311	10		T286	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T135	11		T51	8		T99	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T215	15		T279	15		T228	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T5	10		T9	26		T10	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T157	16		T233	12		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	3		T134	8		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T144	12		T31	10		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	8		T53	4		T157	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	11		T139	14		T157	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	9		T72	1		T215	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T140	24		T142	14		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	2		T60	8		T71	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T72	19		T191	1		T29	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	7		T184	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	9		T147	12		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T147	13		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T134	9		T156	9		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	1		T99	10		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T56	1		T52	2		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T5	11		T9	29		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T210	1		T215	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	4		T2	1		T12	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T157	17		T150	1		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	5		T64	1		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T208	1		T144	13		T158	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	10		T49	8		T157	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T1	12		T139	15		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T209	1		T72	2		T215	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T48	1		T64	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T12	3		T71	9		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	1		T139	13		T147	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T60	9		T239	1		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T29	9		T269	1		T225	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16934	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T2	1		T59	1		T154	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	11		T150	9		T158	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	10		T50	3		T41	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T211	14		T29	5		T247	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	7		T209	11		T51	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T56	12		T41	14		T107	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T56	11		T52	1		T212	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T63	29		T223	14		T145	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	10		T215	11		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	12		T12	11		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	8		T233	7		T242	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	1		T64	17		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T144	6		T158	4		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	8		T155	9		T29	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	11		T140	2		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T209	7		T215	11		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T64	6		T140	14		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	12		T71	2		T51	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T72	10		T211	12		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T60	7		T239	10		T186	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T29	7		T269	5		T225	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T165	2		T104	1		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T59	10		T154	7		T155	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T51	4		T149	1		T155	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T139	13		T147	3		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T33	5		T313	8		T314	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T282	12		T299	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	7		T150	1		T158	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T59	1		T135	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T147	13		T184	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T134	9		T156	9		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T56	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T209	1		T99	1		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	12		T51	10		T99	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T56	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T2	1		T5	11		T9	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T157	17		T14	3		T233	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	4		T64	1		T134	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	1		T144	13		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	13		T53	7		T157	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	12		T139	15		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	10		T209	1		T72	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T48	1		T64	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	3		T60	9		T71	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T96	1		T72	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T51	3		T155	9		T233	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T211	12		T158	2		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T33	4		T313	9		T314	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T282	8		T299	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	11		T150	9		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T59	10		T135	10		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T211	14		T34	11		T247	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T134	7		T51	9		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T56	12		T41	14		T29	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T209	11		T212	6		T226	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T135	10		T230	4		T274	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	10		T56	11		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T12	11		T63	29		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T233	7		T163	11		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	12		T64	17		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T150	8		T144	6		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T53	1		T247	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	11		T158	4		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	8		T209	7		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T64	6		T140	16		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	12		T60	7		T71	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T72	21		T29	7		T269	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33