Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22513

1

T1

16

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3722

1

T1

23

T2

2

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20106

1

T2

2

T3

130

T6

18

auto[1]

6129

1

T1

39

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T1	16		T71	11		T152	9
values[0]	68	1			T60	16		T171	21		T268	17
values[1]	626	1			T12	11		T48	1		T49	8
values[2]	529	1			T2	1		T156	9		T149	10
values[3]	778	1			T1	23		T6	18		T210	1
values[4]	669	1			T12	15		T48	1		T135	24
values[5]	862	1			T2	1		T56	12		T209	12
values[6]	964	1			T59	11		T49	6		T139	13
values[7]	612	1			T12	16		T64	7		T99	10
values[8]	709	1			T2	1		T56	13		T64	18
values[9]	3234	1			T5	11		T8	1		T9	29
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	656	1			T12	11		T60	16		T49	8
values[1]	559	1			T2	1		T6	18		T156	9
values[2]	696	1			T1	23		T210	1		T208	1
values[3]	751	1			T12	15		T48	1		T135	24
values[4]	821	1			T2	1		T56	12		T209	20
values[5]	1022	1			T59	11		T49	6		T139	13
values[6]	2885	1			T5	11		T9	29		T10	32
values[7]	710	1			T2	1		T64	18		T139	15
values[8]	885	1			T1	16		T71	11		T134	16
values[9]	172	1			T8	1		T157	16		T217	13
minimum	17078	1			T3	130		T7	150		T48	126

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	2		T134	9		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	11		T60	8		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T141	12		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	9		T156	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T208	1		T51	2		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	12		T210	1		T154	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	1		T135	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	13		T144	7		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T209	20		T158	5		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T2	1		T56	12		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T139	1		T135	11		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T59	11		T49	4		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T5	1		T9	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T56	13		T64	7		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T64	18		T156	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T139	1		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	13		T147	1		T152	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T71	3		T134	8		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T157	1		T217	1		T292	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T8	1		T29	4		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16804	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T241	9		T180	10		T284	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	6		T134	8		T157	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T60	8		T149	5		T254	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T141	6		T29	8		T35	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	9		T156	8		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T51	8		T43	8		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	11		T154	7		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T135	12		T147	11		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	2		T144	12		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T158	4		T31	11		T109	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T215	15		T155	8		T43	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	12		T135	11		T147	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T49	2		T135	8		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T5	10		T9	26		T10	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T72	1		T40	11		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T141	13		T142	14		T247	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T139	14		T140	13		T215	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	3		T147	2		T51	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T71	8		T134	8		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T157	15		T217	12		T292	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T29	6		T185	7		T316	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T241	3		T284	12		T317	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	13		T152	9		T141	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T71	3		T162	12		T225	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T171	10		T268	6		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T60	8		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	1		T49	2		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	11		T51	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	1		T157	1		T150	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T156	1		T149	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T208	1		T51	2		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	12		T6	9		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	1		T135	12		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	13		T144	7		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T209	12		T50	12		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	1		T56	12		T52	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T139	1		T135	11		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T59	11		T49	4		T135	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	12		T99	1		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T64	7		T72	23		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T64	18		T141	10		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T56	13		T140	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T5	1		T9	3		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T8	1		T134	8		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	3		T141	9		T157	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T71	8		T162	11		T225	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T171	11		T268	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T60	8		T284	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	6		T134	8		T99	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T149	5		T254	6		T247	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T157	13		T167	1		T257	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T156	8		T149	9		T157	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T51	8		T141	6		T43	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	11		T6	9		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	12		T147	11		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	2		T144	12		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	7		T158	4		T31	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T215	15		T43	6		T29	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	12		T135	11		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	2		T135	8		T51	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	4		T99	9		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T72	19		T40	11		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	13		T142	14		T27	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	13		T72	1		T215	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T5	10		T9	26		T10	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T134	8		T139	14		T154	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T49	8		T134	9		T157	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T60	9		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T2	1		T141	7		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	10		T156	9		T149	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T208	1		T51	10		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	12		T210	1		T154	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	1		T135	13		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	3		T144	13		T221	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T209	2		T158	5		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	1		T56	1		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T139	13		T135	12		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T59	1		T49	5		T135	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T5	11		T9	29		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	1		T64	1		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T64	1		T156	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T139	15		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	4		T147	3		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T71	9		T134	9		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T157	16		T217	13		T292	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T8	1		T29	7		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16954	1			T3	130		T7	150		T48	126
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T241	4		T180	1		T284	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T134	8		T34	11		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	10		T60	7		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T141	11		T150	8		T212	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	8		T142	9		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T43	4		T24	7		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	11		T154	6		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T135	11		T140	2		T50	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	12		T144	6		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T209	18		T158	4		T240	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T56	11		T52	1		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T135	10		T150	9		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T59	10		T49	1		T135	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T12	11		T63	29		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T56	12		T64	6		T161	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T64	17		T141	9		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T140	14		T215	11		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	12		T152	8		T51	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T71	2		T134	7		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T292	9		T286	5		T274	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T29	3		T293	12		T318	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T215	8		T279	14		T171	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T241	8		T180	9		T317	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	4		T152	1		T141	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T71	9		T162	12		T225	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T171	12		T268	12		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T60	9		T284	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	1		T49	8		T134	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	1		T51	1		T149	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T157	14		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	9		T149	10		T157	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T208	1		T51	10		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	12		T6	10		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	1		T135	13		T147	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	3		T144	13		T221	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T209	1		T50	16		T158	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	1		T56	1		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T139	13		T135	12		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T59	1		T49	5		T135	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	5		T99	10		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T64	1		T72	21		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T64	1		T141	14		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T56	1		T140	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T5	11		T9	29		T10	32
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T8	1		T134	9		T139	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T1	12		T152	8		T141	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T71	2		T162	11		T225	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T171	9		T268	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T60	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	8		T215	8		T34	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	10		T212	10		T254	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T150	8		T212	6		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T142	9		T233	12		T224	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T141	11		T43	4		T24	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	11		T6	8		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T135	11		T140	2		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	12		T144	6		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T209	11		T50	3		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T56	11		T52	1		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T135	10		T209	7		T41	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T59	10		T49	1		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	11		T150	9		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T64	6		T72	21		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T64	17		T141	9		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T56	12		T140	14		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T63	29		T223	14		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	7		T154	7		T158	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33