Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22249

1

T1

39

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3986

1

T2

2

T12

26

T48

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20105

1

T1

16

T2

1

T3

130

auto[1]

6130

1

T1

23

T2

2

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	344	1			T158	23		T43	13		T26	1
values[0]	48	1			T319	23		T270	25		-	-
values[1]	813	1			T1	16		T2	2		T6	18
values[2]	866	1			T135	24		T152	9		T209	12
values[3]	638	1			T1	23		T8	1		T12	11
values[4]	517	1			T134	17		T139	15		T140	28
values[5]	3005	1			T5	11		T9	29		T10	32
values[6]	777	1			T64	25		T147	3		T152	10
values[7]	743	1			T2	1		T71	11		T147	12
values[8]	645	1			T60	16		T49	8		T156	1
values[9]	959	1			T12	15		T59	11		T72	20
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T2	2		T6	18		T48	1
values[1]	779	1			T8	1		T56	12		T209	12
values[2]	564	1			T1	23		T12	11		T134	17
values[3]	2864	1			T5	11		T9	29		T10	32
values[4]	801	1			T49	6		T64	7		T147	3
values[5]	771	1			T2	1		T64	18		T147	12
values[6]	730	1			T71	11		T156	1		T149	1
values[7]	605	1			T60	16		T49	8		T208	1
values[8]	1065	1			T12	15		T59	11		T72	20
values[9]	63	1			T26	1		T107	3		T274	12
minimum	17021	1			T1	16		T3	130		T7	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T6	9		T56	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T2	1		T48	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	1		T56	12		T209	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T141	12		T27	1		T29	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	12		T135	11		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	11		T134	9		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T5	1		T9	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T48	1		T139	1		T140	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T49	4		T64	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T50	12		T51	13		T162	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T152	10		T51	4		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	1		T64	18		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T149	1		T187	1		T211	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T71	3		T156	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	4		T157	1		T45	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T60	8		T49	2		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T149	1		T215	21		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T12	13		T59	11		T72	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T107	3		T274	6		T271	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T26	1		T267	1		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16776	1			T1	13		T3	130		T7	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T158	3		T320	5		T218	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	9		T134	8		T135	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T147	12		T72	1		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T72	10		T149	5		T158	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T141	6		T27	4		T29	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	11		T135	8		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T134	8		T135	11		T99	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T5	10		T9	26		T10	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T139	14		T140	13		T51	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T49	2		T147	2		T215	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	7		T51	12		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T51	3		T144	12		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T147	11		T141	13		T154	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	5		T247	3		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T71	8		T191	21		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T53	4		T157	13		T177	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T60	8		T49	6		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T149	9		T215	22		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	2		T72	9		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T274	6		T271	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T267	14		T260	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	3		T48	1		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T158	2		T320	5		T218	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T43	5		T107	3		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T158	12		T26	1		T279	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T319	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T270	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	13		T2	1		T6	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T48	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T135	12		T209	12		T72	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T152	9		T141	12		T211	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	12		T8	1		T56	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	11		T135	11		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T209	8		T157	1		T187	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	9		T139	1		T140	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T5	1		T9	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	1		T50	12		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T64	7		T147	1		T152	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T64	18		T51	13		T191	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T149	1		T187	1		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T71	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T53	4		T157	1		T155	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T60	8		T49	2		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T149	1		T215	21		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	13		T59	11		T72	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T43	8		T321	3		T265	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T158	11		T279	15		T108	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T319	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T270	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	3		T6	9		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T147	12		T72	1		T158	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	12		T72	10		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T141	6		T154	7		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	11		T135	8		T158	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T135	11		T99	8		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T157	16		T254	6		T322	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T134	8		T139	14		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T5	10		T9	26		T10	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T50	7		T51	8		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T147	2		T51	3		T215	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T51	12		T191	21		T31	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T144	12		T217	10		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T71	8		T147	11		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	4		T157	13		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T60	8		T49	6		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T149	9		T215	22		T191	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	2		T72	9		T217	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	1		T6	10		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	1		T48	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T56	1		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T141	7		T27	5		T29	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	12		T135	9		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T134	9		T135	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T5	11		T9	29		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	1		T139	15		T140	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T49	5		T64	1		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	16		T51	16		T162	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T152	1		T51	4		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	1		T64	1		T147	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T149	1		T187	1		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T71	9		T156	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T53	7		T157	14		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T60	9		T49	8		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T149	10		T215	24		T191	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T12	3		T59	1		T72	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T107	3		T274	7		T271	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T26	1		T267	15		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16947	1			T1	4		T3	130		T7	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T158	3		T320	6		T218	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	8		T56	12		T134	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T152	8		T150	8		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	11		T209	11		T72	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T141	11		T29	5		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	11		T135	10		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	10		T134	8		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T12	11		T63	29		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T140	14		T142	14		T212	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T49	1		T64	6		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	3		T51	9		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T152	9		T51	3		T144	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T64	17		T141	9		T154	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T211	14		T43	6		T247	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T71	2		T191	18		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T53	1		T45	9		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	7		T233	12		T37	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T215	19		T155	2		T43	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	12		T59	10		T72	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T274	5		T271	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T260	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T1	12		T239	3		T255	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T158	2		T320	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T43	9		T107	3		T321	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T158	12		T26	1		T279	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T319	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T270	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	4		T2	1		T6	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T48	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T135	13		T209	1		T72	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T152	1		T141	7		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	12		T8	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	1		T135	12		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T209	1		T157	17		T187	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T134	9		T139	15		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	11		T9	29		T10	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T48	1		T50	16		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T64	1		T147	3		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T64	1		T51	16		T191	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	1		T187	1		T144	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T71	9		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T53	7		T157	14		T155	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T60	9		T49	8		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T149	10		T215	24		T191	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	3		T59	1		T72	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T43	4		T285	8		T271	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T158	11		T279	14		T307	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T319	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T270	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	12		T6	8		T56	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	8		T158	6		T34	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T135	11		T209	11		T72	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T152	8		T141	11		T211	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	11		T56	11		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	10		T135	10		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T209	7		T254	2		T322	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T134	8		T140	14		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T12	11		T63	29		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	3		T162	11		T225	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T64	6		T152	9		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T64	17		T51	9		T191	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	6		T211	14		T43	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T71	2		T141	9		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T53	1		T155	2		T163	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	7		T233	12		T104	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T215	19		T45	9		T233	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	12		T59	10		T72	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33