Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T71	9		T139	13		T156	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	4		T64	1		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	1		T153	1		T221	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	8		T135	13		T162	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	12		T6	10		T51	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	12		T140	14		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T59	1		T64	1		T141	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T51	16		T150	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T134	9		T156	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T2	2		T60	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T135	9		T51	1		T215	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	1		T140	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T5	11		T9	29		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T215	24		T143	1		T217	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T56	2		T152	1		T99	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T134	9		T209	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	1		T8	1		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T49	5		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T12	5		T170	4		T38	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T154	8		T230	1		T231	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16904	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T24	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T71	2		T50	3		T158	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	12		T64	17		T72	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T166	12		T239	10		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	11		T162	11		T45	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	11		T6	8		T150	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T135	10		T140	14		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T59	10		T64	6		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T51	9		T150	9		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T134	7		T152	9		T72	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	7		T240	11		T241	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	10		T215	11		T41	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	2		T233	7		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T12	12		T63	29		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T215	19		T29	3		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T56	23		T152	8		T191	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	8		T209	7		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T224	17		T242	9		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	10		T49	1		T209	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T12	11		T38	14		T243	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T154	6		T230	4		T234	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T209	1		T206	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T168	1		T181	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T230	13		T236	1		T237	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	15		T156	9		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T64	1		T147	12		T72	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	10		T71	9		T139	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	4		T135	13		T147	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	12		T48	1		T51	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T49	8		T140	14		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T59	1		T64	1		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T135	12		T51	16		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T156	1		T152	1		T72	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T60	9		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T134	9		T51	1		T53	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	1		T140	12		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	3		T135	9		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	1		T134	9		T215	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T5	11		T9	29		T10	32
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T209	1		T96	1		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	1		T8	1		T12	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T12	1		T49	5		T51	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T209	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T237	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	2		T155	9		T24	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T64	17		T72	11		T211	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	8		T71	2		T50	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T135	11		T162	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	11		T150	8		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	14		T52	1		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T59	10		T64	6		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	10		T51	9		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T152	9		T72	10		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	7		T246	7		T241	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T134	7		T53	1		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	2		T233	7		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	12		T135	10		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T134	8		T215	19		T29	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T56	11		T63	29		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T209	7		T142	14		T238	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	11		T56	12		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	10		T49	1		T51	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33