Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22888

1

T1

16

T2

2

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3347

1

T1

23

T2

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20423

1

T1

16

T2

2

T3

130

auto[1]

5812

1

T1

23

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T247	10		T237	18		-	-
values[0]	12	1			T109	5		T248	6		T249	1
values[1]	540	1			T1	16		T56	12		T51	10
values[2]	627	1			T2	1		T59	11		T134	16
values[3]	1008	1			T2	1		T6	18		T49	6
values[4]	3224	1			T1	23		T5	11		T9	29
values[5]	506	1			T2	1		T210	1		T72	24
values[6]	919	1			T135	24		T147	13		T152	10
values[7]	768	1			T48	2		T147	3		T99	10
values[8]	549	1			T60	16		T64	7		T156	1
values[9]	1174	1			T8	1		T12	31		T56	13
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	600	1			T1	16		T56	12		T152	9
values[1]	794	1			T2	1		T59	11		T49	6
values[2]	954	1			T2	1		T6	18		T71	11
values[3]	3166	1			T1	23		T5	11		T9	29
values[4]	680	1			T2	1		T210	1		T147	13
values[5]	828	1			T48	1		T135	24		T152	10
values[6]	714	1			T48	1		T147	3		T99	10
values[7]	580	1			T60	16		T49	8		T64	7
values[8]	841	1			T8	1		T12	16		T56	13
values[9]	157	1			T12	15		T14	3		T163	10
minimum	16921	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	13		T56	12		T51	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T152	9		T51	4		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T51	13		T72	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T59	11		T49	4		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	1		T6	9		T71	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	3		T208	1		T209	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T5	1		T9	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	12		T64	18		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T72	13		T153	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	1		T210	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	1		T152	10		T209	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T135	12		T142	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T48	1		T147	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	4		T150	9		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T156	1		T141	13		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T60	8		T49	2		T64	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T134	9		T140	15		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T12	12		T56	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T14	3		T165	10		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T12	13		T163	2		T250	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16734	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	3		T51	8		T99	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	3		T154	7		T158	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	12		T72	9		T217	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	2		T134	8		T139	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T6	9		T71	8		T149	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T140	11		T215	15		T157	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T5	10		T9	26		T10	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	11		T156	8		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T72	11		T191	1		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T147	12		T50	7		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T226	11		T225	10		T160	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	12		T158	2		T155	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T147	2		T99	9		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	4		T252	11		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T141	22		T34	3		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T60	8		T49	6		T135	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T134	8		T140	13		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	4		T144	12		T191	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T165	8		T170	3		T250	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T12	2		T163	8		T250	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	1		T60	1		T49	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T247	7		T237	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T109	1		T249	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T248	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	13		T56	12		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	3		T149	1		T154	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	1		T99	1		T72	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T59	11		T134	8		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	1		T6	9		T71	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	4		T139	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T5	1		T9	3		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T64	18		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T72	13		T153	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T2	1		T210	1		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T152	10		T209	8		T212	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T135	12		T147	1		T50	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	2		T147	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T150	9		T155	10		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	1		T141	3		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	8		T64	7		T135	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T134	9		T140	15		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T8	1		T12	25		T56	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	3		T237	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T109	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T248	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	3		T51	8		T141	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T149	5		T154	7		T158	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T99	8		T72	9		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T134	8		T139	14		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	9		T71	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T49	2		T139	12		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T5	10		T9	26		T10	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	11		T156	8		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T72	11		T191	1		T254	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T215	8		T216	8		T169	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	11		T225	10		T170	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T135	12		T147	12		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T147	2		T99	9		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T155	13		T27	12		T31	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T141	9		T34	3		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T60	8		T135	8		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T134	8		T140	13		T141	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	6		T49	6		T135	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	4		T56	1		T51	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	1		T51	4		T52	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	1		T51	16		T72	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T59	1		T49	5		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T2	1		T6	10		T71	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T140	12		T208	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T5	11		T9	29		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	12		T64	1		T156	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T72	13		T153	1		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T210	1		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	1		T152	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T135	13		T142	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	1		T147	3		T99	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	7		T150	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T156	1		T141	24		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T60	9		T49	8		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T134	9		T140	14		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T12	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T14	3		T165	9		T170	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T12	3		T163	9		T250	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16897	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	12		T56	11		T141	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T152	8		T51	3		T52	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T51	9		T72	10		T166	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	10		T49	1		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	8		T71	2		T24	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	2		T209	11		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T12	10		T63	29		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	11		T64	17		T111	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T72	11		T34	11		T45	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	3		T215	8		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T152	9		T209	7		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T135	11		T158	2		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	9		T155	9		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	1		T150	8		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T141	11		T34	3		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	7		T64	6		T135	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T134	8		T140	14		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	11		T56	12		T144	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T165	9		T241	8		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T12	12		T163	1		T250	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T211	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T251	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T247	4		T237	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T109	5		T249	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T248	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	4		T56	1		T51	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T52	2		T149	6		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T99	9		T72	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	1		T134	9		T139	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T2	1		T6	10		T71	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T49	5		T139	13		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T5	11		T9	29		T10	32
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	12		T64	1		T156	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T72	13		T153	1		T191	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T210	1		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T152	1		T209	1		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T135	13		T147	13		T50	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T48	2		T147	3		T99	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T150	1		T155	14		T27	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	1		T141	10		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T60	9		T64	1		T135	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T134	9		T140	14		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T8	1		T12	8		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	6		T237	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	12		T56	11		T141	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T52	1		T154	6		T158	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T72	10		T161	7		T256	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T59	10		T134	7		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	8		T71	2		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	1		T140	2		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T12	10		T63	29		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	11		T64	17		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T72	11		T254	2		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T215	8		T222	10		T257	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	9		T209	7		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T135	11		T50	3		T142	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T150	9		T155	9		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	8		T155	9		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T141	2		T34	3		T166	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T60	7		T64	6		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T134	8		T140	14		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	23		T56	12		T135	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33