Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22898

1

T1

16

T2

2

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3337

1

T1

23

T2

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20402

1

T1

16

T2

2

T3

130

auto[1]

5833

1

T1

23

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T8	1		T56	13		T191	40
values[0]	5	1			T109	5		-	-		-	-
values[1]	552	1			T1	16		T56	12		T51	10
values[2]	562	1			T59	11		T134	16		T139	15
values[3]	1062	1			T2	2		T6	18		T49	6
values[4]	3196	1			T1	23		T5	11		T9	29
values[5]	610	1			T2	1		T210	1		T72	24
values[6]	828	1			T135	24		T147	13		T152	10
values[7]	774	1			T48	2		T99	10		T149	1
values[8]	584	1			T60	16		T64	7		T156	1
values[9]	923	1			T12	31		T49	8		T134	17
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	404	1			T1	16		T152	9		T51	17
values[1]	776	1			T2	1		T59	11		T49	6
values[2]	1016	1			T2	1		T6	18		T71	11
values[3]	3111	1			T1	23		T5	11		T9	29
values[4]	685	1			T2	1		T210	1		T147	13
values[5]	810	1			T48	1		T135	24		T152	10
values[6]	746	1			T48	1		T147	3		T99	10
values[7]	552	1			T60	16		T49	8		T64	7
values[8]	930	1			T8	1		T12	16		T56	13
values[9]	80	1			T12	15		T14	3		T163	10
minimum	17125	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	13		T51	2		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T152	9		T51	4		T154	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T51	13		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T59	11		T49	4		T134	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T2	1		T6	9		T71	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	3		T208	1		T209	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T5	1		T9	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	12		T64	18		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T72	13		T153	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	1		T210	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T48	1		T152	10		T209	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T135	12		T50	12		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	1		T147	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T150	9		T211	13		T258	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T156	1		T141	13		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T60	8		T49	2		T64	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T134	9		T140	15		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T12	12		T56	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T14	3		T250	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T12	13		T163	2		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16798	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T52	3		T162	12		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	3		T51	8		T99	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T51	3		T154	7		T158	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T51	12		T217	12		T166	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	2		T134	8		T139	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	9		T71	8		T72	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T140	11		T215	15		T157	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T5	10		T9	26		T10	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	11		T156	8		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T72	11		T191	1		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T147	12		T215	8		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T226	11		T216	6		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	12		T50	7		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	2		T99	9		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T252	11		T253	10		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	22		T34	3		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	8		T49	6		T135	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T134	8		T140	13		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	4		T144	12		T191	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	2		T163	8		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T162	11		T259	3		T243	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T221	1		T154	8		T158	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T8	1		T56	13		T191	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T109	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	13		T56	12		T51	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T52	3		T154	7		T158	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T99	1		T217	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	11		T134	8		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	2		T6	9		T71	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	4		T139	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T5	1		T9	3		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T64	18		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	13		T153	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	1		T210	1		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T152	10		T209	8		T212	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	12		T147	1		T50	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T48	2		T99	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T150	9		T211	13		T155	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T156	1		T147	1		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T60	8		T64	7		T135	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T134	9		T140	15		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	25		T49	2		T135	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T221	12		T154	10		T158	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T191	21		T260	3		T261	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T109	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	3		T51	8		T141	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T154	7		T158	11		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T99	8		T217	12		T262	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T134	8		T139	14		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	9		T71	8		T51	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T49	2		T139	12		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T5	10		T9	26		T10	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	11		T156	8		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T72	11		T191	1		T254	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T215	8		T142	13		T216	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	11		T226	11		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T135	12		T147	12		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T99	9		T155	9		T216	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	13		T27	12		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T147	2		T141	9		T34	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T60	8		T135	8		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T134	8		T140	13		T141	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	6		T49	6		T135	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	4		T51	10		T99	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T152	1		T51	4		T154	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	1		T51	16		T217	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	1		T49	5		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T2	1		T6	10		T71	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T140	12		T208	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T5	11		T9	29		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	12		T64	1		T156	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T72	13		T153	1		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T210	1		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T48	1		T152	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	13		T50	16		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	1		T147	3		T99	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	1		T211	1		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T156	1		T141	24		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	9		T49	8		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T134	9		T140	14		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T12	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T14	3		T250	2		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T12	3		T163	9		T37	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16942	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T52	2		T162	12		T259	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T1	12		T141	11		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T152	8		T51	3		T154	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T51	9		T166	17		T263	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	10		T49	1		T134	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	8		T71	2		T72	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	2		T209	11		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T12	10		T63	29		T223	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	11		T64	17		T111	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T72	11		T34	11		T45	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T215	8		T142	9		T245	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T152	9		T209	7		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T135	11		T50	3		T158	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	9		T155	9		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T150	8		T211	12		T258	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T141	11		T34	3		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T60	7		T64	6		T135	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T134	8		T140	14		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	11		T56	12		T144	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T12	12		T163	1		T260	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T56	11		T211	14		T107	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T52	1		T162	11		T243	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T221	13		T154	11		T158	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T8	1		T56	1		T191	22
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T109	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	4		T56	1		T51	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T52	2		T154	8		T158	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T99	9		T217	13		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	1		T134	9		T139	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T2	2		T6	10		T71	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T49	5		T139	13		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T5	11		T9	29		T10	32
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	12		T64	1		T156	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T72	13		T153	1		T191	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T210	1		T215	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T152	1		T209	1		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T135	13		T147	13		T50	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	2		T99	10		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T150	1		T211	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T156	1		T147	3		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T60	9		T64	1		T135	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T134	9		T140	14		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	8		T49	8		T135	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T154	7		T158	4		T247	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T56	12		T191	18		T41	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	12		T56	11		T141	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T52	1		T154	6		T158	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T161	7		T256	11		T264	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T59	10		T134	7		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	8		T71	2		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	1		T140	2		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T12	10		T63	29		T223	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	11		T64	17		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T72	11		T254	2		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T215	8		T142	9		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T152	9		T209	7		T212	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T135	11		T50	3		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T150	9		T155	9		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T150	8		T211	12		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T141	2		T34	3		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T60	7		T64	6		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T134	8		T140	14		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	23		T135	10		T215	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33