Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22714

1

T1

39

T2

3

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3521

1

T6

18

T12

11

T48

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19689

1

T1

23

T2

2

T3

126

auto[1]

6546

1

T1

16

T2

1

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	786	1			T3	4		T7	8		T48	8
values[0]	19	1			T274	1		T275	18		-	-
values[1]	618	1			T2	1		T12	16		T56	13
values[2]	3141	1			T5	11		T9	29		T10	32
values[3]	722	1			T134	17		T140	28		T51	7
values[4]	697	1			T12	11		T60	16		T135	19
values[5]	683	1			T56	12		T49	6		T156	1
values[6]	654	1			T2	1		T134	16		T139	15
values[7]	707	1			T1	16		T2	1		T12	15
values[8]	914	1			T1	23		T8	1		T64	7
values[9]	851	1			T6	18		T48	1		T156	9
minimum	16443	1			T3	126		T7	142		T48	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	778	1			T2	1		T135	24		T147	3
values[1]	2903	1			T5	11		T9	29		T10	32
values[2]	825	1			T60	16		T134	17		T140	28
values[3]	704	1			T12	11		T56	12		T49	6
values[4]	606	1			T139	15		T209	8		T215	26
values[5]	714	1			T1	16		T2	1		T49	8
values[6]	831	1			T1	23		T2	1		T8	1
values[7]	790	1			T64	7		T71	11		T210	1
values[8]	862	1			T6	18		T48	2		T156	9
values[9]	174	1			T64	18		T163	23		T253	11
minimum	17048	1			T3	130		T7	150		T12	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T135	12		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T141	12		T157	1		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T5	1		T9	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	11		T149	1		T215	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T134	9		T140	15		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T60	8		T99	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	12		T49	4		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	11		T140	3		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T139	1		T142	1		T144	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T209	8		T215	12		T212	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	13		T2	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T134	8		T51	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	12		T2	1		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T50	12		T51	2		T211	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T135	11		T152	10		T99	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T64	7		T71	3		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	1		T156	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	9		T48	1		T72	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T64	18		T159	1		T276	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T163	12		T253	1		T240	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16785	1			T3	130		T7	150		T12	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T47	1		T29	4		T242	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	12		T147	2		T141	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T141	6		T157	16		T31	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T5	10		T9	26		T10	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T215	15		T154	8		T217	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T134	8		T140	13		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T60	8		T158	4		T163	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	2		T135	8		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T140	11		T72	1		T141	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T139	14		T144	12		T29	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T215	14		T34	3		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	3		T49	6		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	8		T149	5		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	11		T12	2		T154	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	7		T51	8		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T135	11		T99	17		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T71	8		T147	11		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T156	8		T51	12		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	9		T72	10		T191	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T159	7		T277	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T163	11		T253	10		T240	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	4		T48	1		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T29	6		T242	8		T278	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	515	1			T3	4		T7	8		T48	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T191	19		T27	1		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T274	1		T275	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T12	12		T56	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T157	1		T47	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T5	1		T9	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T59	11		T149	1		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T134	9		T140	15		T51	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T99	1		T153	1		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T135	11		T147	1		T152	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	11		T60	8		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T56	12		T49	4		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T140	3		T209	8		T141	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T139	1		T52	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T134	8		T51	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	13		T2	1		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T50	12		T51	2		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	12		T8	1		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T64	7		T71	3		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T156	1		T135	11		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	9		T48	1		T72	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16280	1			T3	126		T7	142		T48	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T155	13		T31	11		T159	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T191	21		T27	12		T170	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	4		T135	12		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T157	16		T29	6		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T5	10		T9	26		T10	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T141	6		T215	15		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T134	8		T140	13		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T169	14		T163	8		T279	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T135	8		T147	12		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	8		T72	1		T157	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T49	2		T29	8		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T140	11		T141	13		T215	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T139	14		T53	4		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	8		T142	13		T177	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	3		T12	2		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	7		T51	8		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	11		T99	17		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T71	8		T147	11		T158	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T156	8		T135	11		T51	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	9		T72	10		T191	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T135	13		T147	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T141	7		T157	17		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	11		T9	29		T10	32
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T59	1		T149	1		T215	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T134	9		T140	14		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T60	9		T99	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T56	1		T49	5		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T140	12		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T139	15		T142	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T209	1		T215	15		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	4		T2	1		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	9		T51	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	12		T2	1		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	16		T51	10		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T135	12		T152	1		T99	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T64	1		T71	9		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T48	1		T156	9		T51	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	10		T48	1		T72	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T64	1		T159	8		T276	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T163	12		T253	11		T240	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16931	1			T3	130		T7	150		T12	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T47	1		T29	7		T242	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T135	11		T141	2		T24	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T141	11		T238	14		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T63	29		T223	14		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T59	10		T215	11		T280	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T134	8		T140	14		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	7		T158	4		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	11		T49	1		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	10		T140	2		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	6		T29	7		T233	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T209	7		T215	11		T212	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	12		T52	1		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T134	7		T150	9		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	11		T12	12		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T50	3		T211	12		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T135	10		T152	9		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T64	6		T71	2		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	9		T155	9		T41	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	8		T72	11		T191	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T64	17		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T163	11		T240	11		T275	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T12	11		T56	12		T154	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T29	3		T242	4		T281	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	515	1			T3	4		T7	8		T48	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T191	22		T27	13		T170	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	1		T275	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	1		T12	5		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T157	17		T47	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T5	11		T9	29		T10	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T59	1		T149	1		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T134	9		T140	14		T51	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T99	1		T153	1		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T135	9		T147	13		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T60	9		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T56	1		T49	5		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T140	12		T209	1		T141	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T139	15		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T134	9		T51	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	4		T2	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	16		T51	10		T149	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T1	12		T8	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T64	1		T71	9		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T156	9		T135	12		T51	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	10		T48	1		T72	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16443	1			T3	126		T7	142		T48	118
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T64	17		T155	9		T41	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T191	18		T241	15		T282	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T275	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	11		T56	12		T135	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T29	3		T242	4		T160	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T63	29		T223	14		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T59	10		T141	11		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T134	8		T140	14		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T163	1		T279	14		T239	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T135	10		T152	8		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	10		T60	7		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T56	11		T49	1		T29	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	2		T209	7		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T52	1		T53	1		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	7		T150	9		T142	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T1	12		T12	12		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T50	3		T211	12		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	11		T152	9		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T64	6		T71	2		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T135	10		T51	9		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	8		T72	11		T155	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33