Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22860

1

T1

39

T2

3

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3375

1

T6

18

T12

11

T56

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19584

1

T1

23

T2

2

T3

126

auto[1]

6651

1

T1

16

T2

1

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	450	1			T3	4		T7	8		T48	7
values[0]	47	1			T47	1		T250	11		T275	18
values[1]	590	1			T2	1		T12	16		T56	13
values[2]	3151	1			T5	11		T9	29		T10	32
values[3]	710	1			T60	16		T134	17		T140	28
values[4]	696	1			T135	19		T147	13		T140	14
values[5]	693	1			T12	11		T56	12		T49	6
values[6]	630	1			T2	1		T134	16		T139	15
values[7]	722	1			T1	16		T2	1		T12	15
values[8]	875	1			T1	23		T8	1		T48	1
values[9]	1228	1			T6	18		T48	1		T64	18
minimum	16443	1			T3	126		T7	142		T48	118

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	870	1			T2	1		T12	16		T56	13
values[1]	2911	1			T5	11		T9	29		T10	32
values[2]	823	1			T60	16		T134	17		T140	28
values[3]	725	1			T12	11		T56	12		T49	6
values[4]	622	1			T139	15		T209	8		T142	1
values[5]	688	1			T1	16		T2	1		T49	8
values[6]	792	1			T1	23		T2	1		T8	1
values[7]	858	1			T48	1		T64	7		T71	11
values[8]	797	1			T6	18		T48	1		T64	18
values[9]	221	1			T72	22		T28	6		T163	23
minimum	16928	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	1		T12	12		T135	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T56	13		T141	15		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T5	1		T9	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T59	11		T149	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T134	9		T140	15		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	8		T99	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T56	12		T49	4		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	11		T208	1		T72	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T139	1		T142	1		T212	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T209	8		T144	7		T45	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	13		T2	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	8		T208	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	12		T2	1		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	12		T51	2		T211	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T48	1		T64	7		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T71	3		T210	1		T135	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	1		T64	18		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	9		T153	1		T191	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T72	12		T258	10		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T28	6		T163	12		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16730	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T207	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	4		T135	12		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T141	15		T157	16		T29	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T5	10		T9	26		T10	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T154	8		T217	24		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T134	8		T140	13		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	8		T158	4		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	2		T135	8		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T72	1		T215	14		T157	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	14		T34	3		T29	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T144	12		T247	2		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	3		T49	6		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T134	8		T149	5		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	11		T12	2		T154	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	7		T51	8		T226	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T99	8		T158	2		T155	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T71	8		T135	11		T147	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T156	8		T51	12		T149	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	9		T191	21		T27	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T72	10		T159	7		T277	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T163	11		T253	10		T240	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T207	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	437	1			T3	4		T7	8		T48	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T250	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T47	1		T275	18		T278	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	1		T12	12		T135	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T56	13		T141	3		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T5	1		T9	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T59	11		T149	1		T141	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T134	9		T140	15		T51	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T60	8		T99	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T135	11		T147	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T208	1		T72	1		T211	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	12		T49	4		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	11		T209	8		T215	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T139	1		T52	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	8		T208	1		T51	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	13		T2	1		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T71	3		T50	12		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T1	12		T8	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T210	1		T147	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T48	1		T64	18		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T6	9		T135	11		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16280	1			T3	126		T7	142		T48	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T284	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T250	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T278	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	4		T135	12		T147	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T141	9		T157	16		T29	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T5	10		T9	26		T10	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	6		T154	8		T217	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T134	8		T140	13		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	8		T217	10		T216	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T135	8		T147	12		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T72	1		T158	4		T279	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	2		T141	13		T157	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T215	14		T157	15		T221	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T139	14		T53	4		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	8		T51	8		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	3		T12	2		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T71	8		T50	7		T149	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	11		T99	8		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	11		T99	9		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T156	8		T51	12		T72	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T6	9		T135	11		T191	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	1		T12	5		T135	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T56	1		T141	17		T157	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T5	11		T9	29		T10	32
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T59	1		T149	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T134	9		T140	14		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T60	9		T99	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T56	1		T49	5		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T208	1		T72	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T139	15		T142	1		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T209	1		T144	13		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	4		T2	1		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T134	9		T208	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	12		T2	1		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	16		T51	10		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T48	1		T64	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T71	9		T210	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T48	1		T64	1		T156	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	10		T153	1		T191	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T72	11		T258	1		T159	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T28	6		T163	12		T253	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16891	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T207	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	11		T135	11		T154	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T56	12		T141	13		T29	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T63	29		T223	14		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T59	10		T280	9		T178	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T134	8		T140	14		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T60	7		T158	4		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	11		T49	1		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	10		T215	11		T211	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T212	10		T34	3		T29	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T209	7		T144	6		T45	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	12		T52	1		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T134	7		T150	9		T142	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	11		T12	12		T154	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	3		T211	12		T226	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T64	6		T152	9		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T71	2		T135	10		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T64	17		T51	9		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	8		T191	18		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T72	11		T258	9		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T163	11		T240	11		T285	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T166	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T207	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	437	1			T3	4		T7	8		T48	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T284	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T250	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T47	1		T275	1		T278	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	1		T12	5		T135	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T56	1		T141	10		T157	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T5	11		T9	29		T10	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T59	1		T149	1		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T134	9		T140	14		T51	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T60	9		T99	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T135	9		T147	13		T140	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T208	1		T72	2		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T56	1		T49	5		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T209	1		T215	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T139	15		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T134	9		T208	1		T51	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	4		T2	1		T12	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T71	9		T50	16		T149	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	12		T8	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T210	1		T147	12		T99	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T48	1		T64	1		T156	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T6	10		T135	12		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16443	1			T3	126		T7	142		T48	118
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T250	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T275	17		T278	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	11		T135	11		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T56	12		T141	2		T29	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T63	29		T223	14		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T59	10		T141	11		T29	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T134	8		T140	14		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T60	7		T163	1		T37	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T135	10		T140	2		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T211	14		T158	4		T279	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	11		T49	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	10		T209	7		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T52	1		T53	1		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	7		T142	9		T144	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	12		T12	12		T154	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T71	2		T50	3		T211	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	11		T64	6		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T226	10		T165	9		T286	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T64	17		T51	9		T72	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T6	8		T135	10		T191	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33